Macros
#define	XQSPIPSU_HW_H
	< prevent circular inclusions More...

#define	XQspiPsu_In32 Xil_In32
	Read the 32 bit register value. More...

#define	XQspiPsu_Out32 Xil_Out32
	Write the 32 bit register value. More...

#define	XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
	Read a register. More...

#define	XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
	Write to a register. More...

Device Base Address
Below macros gives QSPI, QSPIPSU base address.
#define	XQSPIPS_BASEADDR 0XFF0F0000U
	QSPI Base Address. More...

#define	XQSPIPSU_BASEADDR 0xFF0F0100U

#define	XQSPIPSU_OFFSET 0x100U

XQSPIPS Enable Register information
QSPIPSU Enable Register
#define	XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
	Register: XQSPIPS_EN_REG. More...

#define	XQSPIPS_EN_SHIFT 0U

#define	XQSPIPS_EN_WIDTH 1U

#define	XQSPIPS_EN_MASK 0X00000001U

XQSPIPSU configuration Register information
This register contains bits for configuring GQSPI controller
#define	XQSPIPSU_CFG_OFFSET 0X00000000U
	Register: XQSPIPSU_CFG. More...

#define	XQSPIPSU_CFG_MODE_EN_SHIFT 30U

#define	XQSPIPSU_CFG_MODE_EN_WIDTH 2U

#define	XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U

#define	XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U

#define	XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29U

#define	XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1U

#define	XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U

#define	XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28U

#define	XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1U

#define	XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U

#define	XQSPIPSU_CFG_ENDIAN_SHIFT 26U

#define	XQSPIPSU_CFG_ENDIAN_WIDTH 1U

#define	XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U

#define	XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20U

#define	XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1U

#define	XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U

#define	XQSPIPSU_CFG_WP_HOLD_SHIFT 19U

#define	XQSPIPSU_CFG_WP_HOLD_WIDTH 1U

#define	XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U

#define	XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3U

#define	XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3U

#define	XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U

#define	XQSPIPSU_CFG_CLK_PHA_SHIFT 2U

#define	XQSPIPSU_CFG_CLK_PHA_WIDTH 1U

#define	XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U

#define	XQSPIPSU_CFG_CLK_POL_SHIFT 1U

#define	XQSPIPSU_CFG_CLK_POL_WIDTH 1U

#define	XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U

XQSPIPSU LQSPI Register information
This register contains bits for configuring LQSPI
#define	XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U
	Register: XQSPIPSU_LQSPI. More...

#define	XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U
	LQSPI mode enable. More...

#define	XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U
	Both memories or one. More...

#define	XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000U
	Separate memory bus. More...

#define	XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000U
	Upper memory page. More...

#define	XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000U
	Upper memory page. More...

#define	XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000U
	Enable mode bits. More...

#define	XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000U
	Mode on. More...

#define	XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000U
	Mode value for dual I/O or quad I/O. More...

#define	XQSPIPS_LQSPI_CR_INST_MASK 0x000000FFU
	Read instr code. More...

#define	XQSPIPS_LQSPI_CR_RST_STATE 0x80000003U
	Default LQSPI CR value. More...

#define	XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013U
	Default 4 Byte LQSPI CR value. More...

#define	XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1U
	Default LQSPI CFG value. More...

XQSPIPSU Interrupt Status Register information
QSPIPSU Interrupt Status Register
#define	XQSPIPSU_ISR_OFFSET 0X00000004U
	Register: XQSPIPSU_ISR. More...

#define	XQSPIPSU_ISR_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_ISR_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_ISR_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_ISR_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_ISR_RXFULL_SHIFT 5U

#define	XQSPIPSU_ISR_RXFULL_WIDTH 1U

#define	XQSPIPSU_ISR_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_ISR_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_ISR_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_ISR_TXFULL_SHIFT 3U

#define	XQSPIPSU_ISR_TXFULL_WIDTH 1U

#define	XQSPIPSU_ISR_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U

#define	XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U

XQSPIPSU Interrupt Enable Register information
This register bits for enabling interrupts
#define	XQSPIPSU_IER_OFFSET 0X00000008U
	Register: XQSPIPSU_IER. More...

#define	XQSPIPSU_IER_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_IER_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_IER_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_IER_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_IER_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_IER_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_IER_RXFULL_SHIFT 5U

#define	XQSPIPSU_IER_RXFULL_WIDTH 1U

#define	XQSPIPSU_IER_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_IER_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_IER_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_IER_TXFULL_SHIFT 3U

#define	XQSPIPSU_IER_TXFULL_WIDTH 1U

#define	XQSPIPSU_IER_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_IER_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_IER_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U

XQSPIPSU Interrupt Disable Register information
This register bits for disabling interrupts
#define	XQSPIPSU_IDR_OFFSET 0X0000000CU
	Register: XQSPIPSU_IDR. More...

#define	XQSPIPSU_IDR_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_IDR_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_IDR_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_IDR_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_IDR_RXFULL_SHIFT 5U

#define	XQSPIPSU_IDR_RXFULL_WIDTH 1U

#define	XQSPIPSU_IDR_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_IDR_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_IDR_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_IDR_TXFULL_SHIFT 3U

#define	XQSPIPSU_IDR_TXFULL_WIDTH 1U

#define	XQSPIPSU_IDR_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U

#define	XQSPIPSU_IDR_ALL_MASK 0X0FBEU

XQSPIPSU Interrupt Mask Register information
This register bits for masking interrupts
#define	XQSPIPSU_IMR_OFFSET 0X00000010U
	Register: XQSPIPSU_IMR. More...

#define	XQSPIPSU_IMR_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_IMR_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_IMR_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_IMR_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_IMR_RXFULL_SHIFT 5U

#define	XQSPIPSU_IMR_RXFULL_WIDTH 1U

#define	XQSPIPSU_IMR_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_IMR_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_IMR_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_IMR_TXFULL_SHIFT 3U

#define	XQSPIPSU_IMR_TXFULL_WIDTH 1U

#define	XQSPIPSU_IMR_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U

XQSPIPSU Enable Register information
This register bits for enabling QSPI controller
#define	XQSPIPSU_EN_OFFSET 0X00000014U
	Register: XQSPIPSU_EN_REG. More...

#define	XQSPIPSU_EN_SHIFT 0U

#define	XQSPIPSU_EN_WIDTH 1U

#define	XQSPIPSU_EN_MASK 0X00000001U

XQSPIPSU TX Data Register information
This register bits for configuring TXFIFO
#define	XQSPIPSU_TXD_OFFSET 0X0000001CU
	Register: XQSPIPSU_TXD. More...

#define	XQSPIPSU_TXD_SHIFT 0U

#define	XQSPIPSU_TXD_WIDTH 32U

#define	XQSPIPSU_TXD_MASK 0XFFFFFFFFU

#define	XQSPIPSU_TXD_DEPTH 64

XQSPIPSU RX Data Register information
This register bits for configuring RXFIFO
#define	XQSPIPSU_RXD_OFFSET 0X00000020U
	Register: XQSPIPSU_RXD. More...

#define	XQSPIPSU_RXD_SHIFT 0U

#define	XQSPIPSU_RXD_WIDTH 32U

#define	XQSPIPSU_RXD_MASK 0XFFFFFFFFU

XQSPIPSU TX/RX Threshold Register information
This register bits for configuring TX/RX Threshold
#define	XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U
	Register: XQSPIPSU_TX_THRESHOLD. More...

#define	XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0U

#define	XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6U

#define	XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU

#define	XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U

#define	XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU

#define	XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0U

#define	XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6U

#define	XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU

#define	XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U

#define	XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U

XQSPIPSU GPIO Register information
#define	XQSPIPSU_GPIO_OFFSET 0X00000030U
	Register: XQSPIPSU_GPIO. More...

#define	XQSPIPSU_GPIO_WP_N_SHIFT 0U

#define	XQSPIPSU_GPIO_WP_N_WIDTH 1U

#define	XQSPIPSU_GPIO_WP_N_MASK 0X00000001U

XQSPIPSU Loopback Master Clock Delay Adjustment Register information
This register contains bits for configuring loopback
#define	XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U
	Register: XQSPIPSU_LPBK_DLY_ADJ. More...

#define	XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5U

#define	XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1U

#define	XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U

XQSPIPSU GEN_FIFO Register information
This register contains bits for configuring GENFIFO
#define	XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U
	Register: XQSPIPSU_GEN_FIFO. More...

#define	XQSPIPSU_GEN_FIFO_DATA_SHIFT 0U

#define	XQSPIPSU_GEN_FIFO_DATA_WIDTH 20U

#define	XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU

XQSPIPSU Select Register information
This register contains bits for selection GQSPI/LQSPI controller
#define	XQSPIPSU_SEL_OFFSET 0X00000044U
	Register: XQSPIPSU_SEL. More...

#define	XQSPIPSU_SEL_SHIFT 0U

#define	XQSPIPSU_SEL_WIDTH 1U

#define	XQSPIPSU_SEL_LQSPI_MASK 0X0U

#define	XQSPIPSU_SEL_GQSPI_MASK 0X00000001U

XQSPIPSU FIFO Control Register information
This register contains bits for controlling TXFIFO and RXFIFO
#define	XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU
	Register: XQSPIPSU_FIFO_CTRL. More...

#define	XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2U

#define	XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1U

#define	XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U

#define	XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1U

#define	XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1U

#define	XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U

#define	XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0U

#define	XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1U

#define	XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U

XQSPIPSU GENFIFO Threshold Register information
This register contains bits for configuring GENFIFO threshold
#define	XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U
	Register: XQSPIPSU_GF_THRESHOLD. More...

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0U

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5U

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001FU

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U

XQSPIPSU Poll configuration Register information
This register contains bits for configuring Poll feature
#define	XQSPIPSU_POLL_CFG_OFFSET 0X00000054U
	Register: XQSPIPSU_POLL_CFG. More...

#define	XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31U

#define	XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1U

#define	XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U

#define	XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30U

#define	XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1U

#define	XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U

#define	XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8U

#define	XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8U

#define	XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U

#define	XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0U

#define	XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8U

#define	XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU

#define	XQSPIPSU_P_TO_OFFSET 0X00000058U

#define	XQSPIPSU_P_TO_VALUE_SHIFT 0U

#define	XQSPIPSU_P_TO_VALUE_WIDTH 32U

#define	XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU

XQSPIPSU Transfer Status Register information
This register contains bits for transfer status
#define	XQSPIPSU_XFER_STS_OFFSET 0X0000005CU
	Register: XQSPIPSU_XFER_STS. More...

#define	XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0U

#define	XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32U

#define	XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU

XQSPIPSU GEN_FIFO Snapshot Register information
This register contains bits for configuring GENFIFO
#define	XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U
	Register: XQSPIPSU_GF_SNAPSHOT. More...

#define	XQSPIPSU_GF_SNAPSHOT_SHIFT 0U

#define	XQSPIPSU_GF_SNAPSHOT_WIDTH 20U

#define	XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU

XQSPIPSU Receive Data Copy Register information
#define	XQSPIPSU_RX_COPY_OFFSET 0X00000064U
	Register: XQSPIPSU_RX_COPY. More...

#define	XQSPIPSU_RX_COPY_UPPER_SHIFT 8U

#define	XQSPIPSU_RX_COPY_UPPER_WIDTH 8U

#define	XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U

#define	XQSPIPSU_RX_COPY_LOWER_SHIFT 0U

#define	XQSPIPSU_RX_COPY_LOWER_WIDTH 8U

#define	XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU

XQSPIPSU Module Identification Register information
#define	XQSPIPSU_MOD_ID_OFFSET 0X000000FCU
	Register: XQSPIPSU_MOD_ID. More...

#define	XQSPIPSU_MOD_ID_SHIFT 0U

#define	XQSPIPSU_MOD_ID_WIDTH 32U

#define	XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU

XQSPIPSU DMA Transfer Register information
This register contains bits for configuring DMA
#define	XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U
	Register: XQSPIPSU_QSPIDMA_DST_ADDR. More...

#define	XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU

#define	XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U

#define	XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27U

#define	XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU

#define	XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U

#define	XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13U

#define	XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U

#define	XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8U

#define	XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U

#define	XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4U

#define	XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU

#define	XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U

#define	XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU

#define	XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU

#define	XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U

#define	XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32U

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU

XQSPIPSU Generic FIFO masks information
Generic FIFO masks information
#define	XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU
	Generic FIFO masks. More...

#define	XQSPIPSU_GENFIFO_DATA_XFER 0x100U

#define	XQSPIPSU_GENFIFO_EXP 0x200U

#define	XQSPIPSU_GENFIFO_MODE_SPI 0x400U

#define	XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U

#define	XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U

#define	XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */

#define	XQSPIPSU_GENFIFO_CS_LOWER 0x1000U

#define	XQSPIPSU_GENFIFO_CS_UPPER 0x2000U

#define	XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U

#define	XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U

#define	XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */

#define	XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */

#define	XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */

#define	XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */

#define	XQSPIPSU_GENFIFO_STRIPE 0x40000U

#define	XQSPIPSU_GENFIFO_POLL 0x80000U

XQSPIPSU RX Data Delay Register information
#define	XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U
	QSPI Data delay register. More...

#define	XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT 31U

#define	XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH 1U

#define	XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK 0X80000000U

#define	XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT 28U

#define	XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH 3U

#define	XQSPIPSU_DATA_DLY_ADJ_DLY_MASK 0X70000000U

TAPDLY Bypass register information
#define	IOU_TAPDLY_BYPASS_OFFSET 0X00000390U
	Tapdelay Bypass register. More...

#define	IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U

#define	IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U

#define	IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U

#define	IOU_TAPDLY_RESET_STATE 0x7U

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