Data Structures
struct	XQspiPsu_Msg
	This typedef contains configuration information for a flash message. More...

struct	XQspiPsu_Config
	This typedef contains configuration information for the device. More...

struct	XQspiPsu
	The XQspiPsu driver instance data. More...

Macros
#define	MAX_DELAY_CNT 1000000000U
	Max delay count. More...

#define	XQSPIPSU_H_
	< prevent circular inclusions More...

#define	BYTES256_PER_PAGE 256U
	Definitions for Intel, STM, Winbond and Spansion Serial Flash Device geometry. More...

#define	BYTES512_PER_PAGE 512U
	512 Bytes per Page More...

#define	BYTES1024_PER_PAGE 1024U
	1024 Bytes per Page More...

#define	PAGES16_PER_SECTOR 16U
	16 Pages per Sector More...

#define	PAGES128_PER_SECTOR 128U
	128 Pages per Sector More...

#define	PAGES256_PER_SECTOR 256U
	256 Pages per Sector More...

#define	PAGES512_PER_SECTOR 512U
	512 Pages per Sector More...

#define	PAGES1024_PER_SECTOR 1024U
	1024 Pages per Sector More...

#define	NUM_OF_SECTORS2 2U
	2 Sectors More...

#define	NUM_OF_SECTORS4 4U
	4 Sectors More...

#define	NUM_OF_SECTORS8 8U
	8 Sector More...

#define	NUM_OF_SECTORS16 16U
	16 Sectors More...

#define	NUM_OF_SECTORS32 32U
	32 Sectors More...

#define	NUM_OF_SECTORS64 64U
	64 Sectors More...

#define	NUM_OF_SECTORS128 128U
	128 Sectors More...

#define	NUM_OF_SECTORS256 256U
	256 Sectors More...

#define	NUM_OF_SECTORS512 512U
	512 Sectors More...

#define	NUM_OF_SECTORS1024 1024U
	1024 Sectors More...

#define	NUM_OF_SECTORS2048 2048U
	2048 Sectors More...

#define	NUM_OF_SECTORS4096 4096U
	4096 Sectors More...

#define	NUM_OF_SECTORS8192 8192U
	8192 Sectors More...

#define	SECTOR_SIZE_64K 0X10000U
	64K Sector More...

#define	SECTOR_SIZE_128K 0X20000U
	128K Sector More...

#define	SECTOR_SIZE_256K 0X40000U
	256K Sector More...

#define	SECTOR_SIZE_512K 0X80000U
	512K Sector More...

#define	XQSPIPSU_READMODE_DMA 0x0U
	DMA read mode. More...

#define	XQSPIPSU_READMODE_IO 0x1U
	IO read mode. More...

#define	XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U
	Select lower flash. More...

#define	XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U
	Select upper flash. More...

#define	XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U
	Select both flash. More...

#define	XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U
	Select lower bus flash. More...

#define	XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U
	Select upper bus flash. More...

#define	XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U
	Select both bus flash. More...

#define	XQSPIPSU_SELECT_MODE_SPI 0x1U
	Select SPI mode. More...

#define	XQSPIPSU_SELECT_MODE_DUALSPI 0x2U
	Select dual SPI mode. More...

#define	XQSPIPSU_SELECT_MODE_QUADSPI 0x4U
	Select quad SPI mode. More...

#define	XQSPIPSU_GENFIFO_CS_SETUP 0x05U
	Chip select setup in GENFIO. More...

#define	XQSPIPSU_GENFIFO_CS_HOLD 0x04U
	Chip select hold in GENFIFO. More...

#define	XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U
	Clk Active low option. More...

#define	XQSPIPSU_CLK_PHASE_1_OPTION 0x4U
	Clk phase 1 option. More...

#define	XQSPIPSU_MANUAL_START_OPTION 0x8U
	Manual start option. More...

#define	XQSPIPSU_LQSPI_MODE_OPTION 0x20U
	LQSPI mode option. More...

#define	XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB 1U
	LQSPI less Than 16 MB. More...

#define	XQSPIPSU_GENFIFO_EXP_START 0x100U
	Genfifo start. More...

#define	XQSPIPSU_DMA_BYTES_MAX 0x10000000U
	DMA bytes max. More...

#define	XQSPIPSU_CLK_PRESCALE_2 0x00U
	Clock prescale 2. More...

#define	XQSPIPSU_CLK_PRESCALE_4 0x01U
	Clock prescale 4. More...

#define	XQSPIPSU_CLK_PRESCALE_8 0x02U
	Clock prescale 8. More...

#define	XQSPIPSU_CLK_PRESCALE_16 0x03U
	Clock prescale 16. More...

#define	XQSPIPSU_CLK_PRESCALE_32 0x04U
	Clock prescale 32. More...

#define	XQSPIPSU_CLK_PRESCALE_64 0x05U
	Clock prescale 64. More...

#define	XQSPIPSU_CLK_PRESCALE_128 0x06U
	Clock prescale 128. More...

#define	XQSPIPSU_CLK_PRESCALE_256 0x07U
	Clock prescale 256. More...

#define	XQSPIPSU_CR_PRESC_MAXIMUM 7U
	Prescale max. More...

#define	XQSPIPSU_CONNECTION_MODE_SINGLE 0U
	Single mode connection. More...

#define	XQSPIPSU_CONNECTION_MODE_STACKED 1U
	Stacked mode connection. More...

#define	XQSPIPSU_CONNECTION_MODE_PARALLEL 2U
	Parallel mode connection. More...

#define	XQSPIPSU_FREQ_37_5MHZ 37500000U
	Frequency 375 Mhz. More...

#define	XQSPIPSU_FREQ_40MHZ 40000000U
	Frequency 40 Mhz. More...

#define	XQSPIPSU_FREQ_100MHZ 100000000U
	Frequency 100 Mhz. More...

#define	XQSPIPSU_FREQ_150MHZ 150000000U
	Frequency 150 Mhz. More...

#define	XQSPIPSU_MSG_FLAG_STRIPE 0x1U
	Stripe Msg flag. More...

#define	XQSPIPSU_MSG_FLAG_RX 0x2U
	Rx Msg flag. More...

#define	XQSPIPSU_MSG_FLAG_TX 0x4U
	Tx Msg flag. More...

#define	XQSPIPSU_MSG_FLAG_POLL 0x8U
	POLL Msg flag. More...

#define	XQSPIPSU_RXADDR_OVER_32BIT 0x100000000U
	Rx address over 32 bit. More...

#define	XQSPIPSU_SET_WP 1
	GQSPI configuration to toggle WP of flash. More...

#define	XQspiPsu_Select(InstancePtr, Mask)
	select QSPI controller More...

#define	XQspiPsu_Enable(InstancePtr)
	Enable QSPI Controller. More...

#define	XQspiPsu_Disable(InstancePtr)
	Disable QSPI controller. More...

#define	XQspiPsu_GetLqspiConfigReg(InstancePtr)
	Read Configuration register of LQSPI Controller. More...

#define	XQSPIPSU_HW_H
	< prevent circular inclusions More...

#define	XQspiPsu_In32 Xil_In32
	Read the 32 bit register value. More...

#define	XQspiPsu_Out32 Xil_Out32
	Write the 32 bit register value. More...

#define	XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
	Read a register. More...

#define	XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
	Write to a register. More...

#define	XQSPIPSU_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
	Number of options in option table. More...

#define	MAX_DELAY_CNT 1000000000U
	Max delay count. More...

Typedefs
typedef void(*	XQspiPsu_StatusHandler )(const void *CallBackRef, u32 StatusEvent, u32 ByteCount)
	The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device. More...

Functions
s32	XQspiPsu_CfgInitialize (XQspiPsu InstancePtr, const XQspiPsu_Config ConfigPtr, UINTPTR EffectiveAddr)
	Initializes a specific XQspiPsu instance as such the driver is ready to use. More...

void	XQspiPsu_Idle (const XQspiPsu *InstancePtr)
	Stops the transfer of data to internal DST FIFO from stream interface and also stops the issuing of new write commands to memory. More...

void	XQspiPsu_Reset (XQspiPsu *InstancePtr)
	Resets the QSPIPSU device. More...

void	XQspiPsu_Abort (XQspiPsu *InstancePtr)
	Aborts a transfer in progress. More...

void	XQspiPsu_PollDataHandler (XQspiPsu *InstancePtr, u32 StatusReg)
	This is the handler for polling functionality of controller. More...

s32	XQspiPsu_PolledTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)
	This function performs a transfer on the bus in polled mode. More...

s32	XQspiPsu_InterruptTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)
	This function initiates a transfer on the bus and enables interrupts. More...

s32	XQspiPsu_InterruptHandler (XQspiPsu *InstancePtr)
	Handles interrupt based transfers by acting on GENFIFO and DMA interurpts. More...

void	XQspiPsu_SetStatusHandler (XQspiPsu InstancePtr, void CallBackRef, XQspiPsu_StatusHandler FuncPointer)
	Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. More...

void	XQspiPsu_WriteProtectToggle (const XQspiPsu *InstancePtr, u32 Toggle)
	This API enables/ disables Write Protect pin on the flash parts. More...

s32	XQspiPsu_StartDmaTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)
	This function start a DMA transfer. More...

s32	XQspiPsu_CheckDmaDone (XQspiPsu *InstancePtr)
	This function check for DMA transfer complete. More...

XQspiPsu_Config *	XQspiPsu_LookupConfig (u16 DeviceId)
	Looks up the device configuration based on the unique device ID. More...

s32	XQspiPsu_SetClkPrescaler (const XQspiPsu *InstancePtr, u8 Prescaler)
	Configures the clock according to the prescaler passed. More...

void	XQspiPsu_SelectFlash (XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
	This function should be used to tell the QSPIPSU driver the HW flash configuration being used. More...

s32	XQspiPsu_SetOptions (XQspiPsu *InstancePtr, u32 Options)
	This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. More...

s32	XQspiPsu_ClearOptions (XQspiPsu *InstancePtr, u32 Options)
	This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. More...

u32	XQspiPsu_GetOptions (const XQspiPsu *InstancePtr)
	This function gets the options for the QSPIPSU device. More...

s32	XQspiPsu_SetReadMode (XQspiPsu *InstancePtr, u32 Mode)
	This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options. More...

void	XQspiPsu_SetWP (const XQspiPsu *InstancePtr, u8 Value)
	This function sets the Write Protect and Hold options for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Write Protect and Hold options. More...

void	XQspiPsu_GenFifoEntryData (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	This function writes the GENFIFO entries to transmit the messages requested. More...

void	XQspiPsu_PollDataConfig (XQspiPsu InstancePtr, XQspiPsu_Msg FlashMsg)
	This function enables the polling functionality of controller. More...

s32	XQspiPsu_PolledMessageTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)
	This function performs a transfer on the bus in polled mode. More...

void	XQspiPsu_IntrDataTransfer (XQspiPsu InstancePtr, u32 QspiPsuStatusReg, u8 *DeltaMsgCnt)
	This function transfers Tx and Rx data. More...

void	XQspiPsu_IntrDummyDataTransfer (XQspiPsu *InstancePtr, u32 QspiPsuStatusReg, u8 DeltaMsgCnt)
	This function transfers Dummy byte. More...

void	XQspiPsu_FillTxFifo (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 Size)
	Fills the TX FIFO as long as there is room in the FIFO or the bytes required to be transmitted. More...

void	XQspiPsu_TXSetup (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	This function checks the TX buffer in the message and setup the TX FIFO as required. More...

void	XQspiPsu_SetupRxDma (const XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	This function sets up the RX DMA operation. More...

void	XQspiPsu_Setup64BRxDma (const XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	This function sets up the RX DMA operation on a 32bit Machine For 64bit Dma transfers. More...

u32	XQspiPsu_SetIOMode (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	This function reads remaining bytes, after the completion of a DMA transfer, using IO mode. More...

void	XQspiPsu_RXSetup (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	This function checks the RX buffers in the message and setup the RX DMA as required. More...

void	XQspiPsu_TXRXSetup (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 *GenFifoEntry)
	This function checks the TX/RX buffers in the message and setups up the GENFIFO entries, TX FIFO or RX DMA as required. More...

void	XQspiPsu_GenFifoEntryDataLen (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 *GenFifoEntry)
	This function writes the Data length to GENFIFO entries that need to be transmitted or received. More...

u32	XQspiPsu_CreatePollDataConfig (const XQspiPsu InstancePtr, const XQspiPsu_Msg FlashMsg)
	This function creates Poll config register data to write. More...

u32	XQspiPsu_SelectSpiMode (u8 SpiMode)
	Selects SPI mode - x1 or x2 or x4. More...

void	XQspiPsu_SetDefaultConfig (XQspiPsu *InstancePtr)
	Enable and initialize DMA Mode, set little endain, disable poll timeout, clear prescalar bits and reset thresholds. More...

void	XQspiPsu_ReadRxFifo (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, s32 Size)
	Read the specified number of bytes from RX FIFO. More...

void	XQspiPsu_IORead (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 StatusReg)
	This function reads data from RXFifo in IO mode. More...

s32	XQspiPsu_PolledSendData (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, s32 Index)
	This function transfers Tx data on the bus in polled mode. More...

s32	XQspiPsu_PolledRecvData (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, s32 Index, u32 *IOPending)
	This function transfers Rx data on the bus in polled mode. More...

void	XQspiPsu_IntrSendData (XQspiPsu InstancePtr, u32 QspiPsuStatusReg, u8 DeltaMsgCnt)
	This function performs a transfer of Tx data on the bus in interrupt mode. More...

void	XQspiPsu_IntrRecvData (XQspiPsu InstancePtr, u32 QspiPsuStatusReg, u32 DmaIntrStatusReg, u8 DeltaMsgCnt)
	This function performs a transfer of Rx data on the busin interrupt mode. More...

Variables
XQspiPsu_Config	XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES]
	This table contains configuration information for each QSPIPSU device in the system. More...

XQspiPsu_Config	XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES]
	This table contains configuration information for each QSPIPSU device in the system. More...

Device Base Address
Below macros gives QSPI, QSPIPSU base address.
#define	XQSPIPS_BASEADDR 0XFF0F0000U
	QSPI Base Address. More...

#define	XQSPIPSU_BASEADDR 0xFF0F0100U

#define	XQSPIPSU_OFFSET 0x100U

XQSPIPS Enable Register information
QSPIPSU Enable Register
#define	XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
	Register: XQSPIPS_EN_REG. More...

#define	XQSPIPS_EN_SHIFT 0U

#define	XQSPIPS_EN_WIDTH 1U

#define	XQSPIPS_EN_MASK 0X00000001U

XQSPIPSU configuration Register information
This register contains bits for configuring GQSPI controller
#define	XQSPIPSU_CFG_OFFSET 0X00000000U
	Register: XQSPIPSU_CFG. More...

#define	XQSPIPSU_CFG_MODE_EN_SHIFT 30U

#define	XQSPIPSU_CFG_MODE_EN_WIDTH 2U

#define	XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U

#define	XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U

#define	XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29U

#define	XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1U

#define	XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U

#define	XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28U

#define	XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1U

#define	XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U

#define	XQSPIPSU_CFG_ENDIAN_SHIFT 26U

#define	XQSPIPSU_CFG_ENDIAN_WIDTH 1U

#define	XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U

#define	XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20U

#define	XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1U

#define	XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U

#define	XQSPIPSU_CFG_WP_HOLD_SHIFT 19U

#define	XQSPIPSU_CFG_WP_HOLD_WIDTH 1U

#define	XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U

#define	XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3U

#define	XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3U

#define	XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U

#define	XQSPIPSU_CFG_CLK_PHA_SHIFT 2U

#define	XQSPIPSU_CFG_CLK_PHA_WIDTH 1U

#define	XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U

#define	XQSPIPSU_CFG_CLK_POL_SHIFT 1U

#define	XQSPIPSU_CFG_CLK_POL_WIDTH 1U

#define	XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U

XQSPIPSU LQSPI Register information
This register contains bits for configuring LQSPI
#define	XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U
	Register: XQSPIPSU_LQSPI. More...

#define	XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U
	LQSPI mode enable. More...

#define	XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U
	Both memories or one. More...

#define	XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000U
	Separate memory bus. More...

#define	XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000U
	Upper memory page. More...

#define	XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000U
	Upper memory page. More...

#define	XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000U
	Enable mode bits. More...

#define	XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000U
	Mode on. More...

#define	XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000U
	Mode value for dual I/O or quad I/O. More...

#define	XQSPIPS_LQSPI_CR_INST_MASK 0x000000FFU
	Read instr code. More...

#define	XQSPIPS_LQSPI_CR_RST_STATE 0x80000003U
	Default LQSPI CR value. More...

#define	XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013U
	Default 4 Byte LQSPI CR value. More...

#define	XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1U
	Default LQSPI CFG value. More...

XQSPIPSU Interrupt Status Register information
QSPIPSU Interrupt Status Register
#define	XQSPIPSU_ISR_OFFSET 0X00000004U
	Register: XQSPIPSU_ISR. More...

#define	XQSPIPSU_ISR_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_ISR_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_ISR_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_ISR_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_ISR_RXFULL_SHIFT 5U

#define	XQSPIPSU_ISR_RXFULL_WIDTH 1U

#define	XQSPIPSU_ISR_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_ISR_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_ISR_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_ISR_TXFULL_SHIFT 3U

#define	XQSPIPSU_ISR_TXFULL_WIDTH 1U

#define	XQSPIPSU_ISR_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U

#define	XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U

XQSPIPSU Interrupt Enable Register information
This register bits for enabling interrupts
#define	XQSPIPSU_IER_OFFSET 0X00000008U
	Register: XQSPIPSU_IER. More...

#define	XQSPIPSU_IER_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_IER_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_IER_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_IER_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_IER_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_IER_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_IER_RXFULL_SHIFT 5U

#define	XQSPIPSU_IER_RXFULL_WIDTH 1U

#define	XQSPIPSU_IER_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_IER_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_IER_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_IER_TXFULL_SHIFT 3U

#define	XQSPIPSU_IER_TXFULL_WIDTH 1U

#define	XQSPIPSU_IER_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_IER_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_IER_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U

XQSPIPSU Interrupt Disable Register information
This register bits for disabling interrupts
#define	XQSPIPSU_IDR_OFFSET 0X0000000CU
	Register: XQSPIPSU_IDR. More...

#define	XQSPIPSU_IDR_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_IDR_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_IDR_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_IDR_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_IDR_RXFULL_SHIFT 5U

#define	XQSPIPSU_IDR_RXFULL_WIDTH 1U

#define	XQSPIPSU_IDR_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_IDR_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_IDR_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_IDR_TXFULL_SHIFT 3U

#define	XQSPIPSU_IDR_TXFULL_WIDTH 1U

#define	XQSPIPSU_IDR_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U

#define	XQSPIPSU_IDR_ALL_MASK 0X0FBEU

XQSPIPSU Interrupt Mask Register information
This register bits for masking interrupts
#define	XQSPIPSU_IMR_OFFSET 0X00000010U
	Register: XQSPIPSU_IMR. More...

#define	XQSPIPSU_IMR_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_IMR_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_IMR_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_IMR_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_IMR_RXFULL_SHIFT 5U

#define	XQSPIPSU_IMR_RXFULL_WIDTH 1U

#define	XQSPIPSU_IMR_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_IMR_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_IMR_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_IMR_TXFULL_SHIFT 3U

#define	XQSPIPSU_IMR_TXFULL_WIDTH 1U

#define	XQSPIPSU_IMR_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U

XQSPIPSU Enable Register information
This register bits for enabling QSPI controller
#define	XQSPIPSU_EN_OFFSET 0X00000014U
	Register: XQSPIPSU_EN_REG. More...

#define	XQSPIPSU_EN_SHIFT 0U

#define	XQSPIPSU_EN_WIDTH 1U

#define	XQSPIPSU_EN_MASK 0X00000001U

XQSPIPSU TX Data Register information
This register bits for configuring TXFIFO
#define	XQSPIPSU_TXD_OFFSET 0X0000001CU
	Register: XQSPIPSU_TXD. More...

#define	XQSPIPSU_TXD_SHIFT 0U

#define	XQSPIPSU_TXD_WIDTH 32U

#define	XQSPIPSU_TXD_MASK 0XFFFFFFFFU

#define	XQSPIPSU_TXD_DEPTH 64

XQSPIPSU RX Data Register information
This register bits for configuring RXFIFO
#define	XQSPIPSU_RXD_OFFSET 0X00000020U
	Register: XQSPIPSU_RXD. More...

#define	XQSPIPSU_RXD_SHIFT 0U

#define	XQSPIPSU_RXD_WIDTH 32U

#define	XQSPIPSU_RXD_MASK 0XFFFFFFFFU

XQSPIPSU TX/RX Threshold Register information
This register bits for configuring TX/RX Threshold
#define	XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U
	Register: XQSPIPSU_TX_THRESHOLD. More...

#define	XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0U

#define	XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6U

#define	XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU

#define	XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U

#define	XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU

#define	XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0U

#define	XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6U

#define	XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU

#define	XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U

#define	XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U

XQSPIPSU GPIO Register information
#define	XQSPIPSU_GPIO_OFFSET 0X00000030U
	Register: XQSPIPSU_GPIO. More...

#define	XQSPIPSU_GPIO_WP_N_SHIFT 0U

#define	XQSPIPSU_GPIO_WP_N_WIDTH 1U

#define	XQSPIPSU_GPIO_WP_N_MASK 0X00000001U

XQSPIPSU Loopback Master Clock Delay Adjustment Register information
This register contains bits for configuring loopback
#define	XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U
	Register: XQSPIPSU_LPBK_DLY_ADJ. More...

#define	XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5U

#define	XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1U

#define	XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U

XQSPIPSU GEN_FIFO Register information
This register contains bits for configuring GENFIFO
#define	XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U
	Register: XQSPIPSU_GEN_FIFO. More...

#define	XQSPIPSU_GEN_FIFO_DATA_SHIFT 0U

#define	XQSPIPSU_GEN_FIFO_DATA_WIDTH 20U

#define	XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU

XQSPIPSU Select Register information
This register contains bits for selection GQSPI/LQSPI controller
#define	XQSPIPSU_SEL_OFFSET 0X00000044U
	Register: XQSPIPSU_SEL. More...

#define	XQSPIPSU_SEL_SHIFT 0U

#define	XQSPIPSU_SEL_WIDTH 1U

#define	XQSPIPSU_SEL_LQSPI_MASK 0X0U

#define	XQSPIPSU_SEL_GQSPI_MASK 0X00000001U

XQSPIPSU FIFO Control Register information
This register contains bits for controlling TXFIFO and RXFIFO
#define	XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU
	Register: XQSPIPSU_FIFO_CTRL. More...

#define	XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2U

#define	XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1U

#define	XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U

#define	XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1U

#define	XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1U

#define	XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U

#define	XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0U

#define	XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1U

#define	XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U

XQSPIPSU GENFIFO Threshold Register information
This register contains bits for configuring GENFIFO threshold
#define	XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U
	Register: XQSPIPSU_GF_THRESHOLD. More...

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0U

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5U

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001FU

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U

XQSPIPSU Poll configuration Register information
This register contains bits for configuring Poll feature
#define	XQSPIPSU_POLL_CFG_OFFSET 0X00000054U
	Register: XQSPIPSU_POLL_CFG. More...

#define	XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31U

#define	XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1U

#define	XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U

#define	XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30U

#define	XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1U

#define	XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U

#define	XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8U

#define	XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8U

#define	XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U

#define	XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0U

#define	XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8U

#define	XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU

#define	XQSPIPSU_P_TO_OFFSET 0X00000058U

#define	XQSPIPSU_P_TO_VALUE_SHIFT 0U

#define	XQSPIPSU_P_TO_VALUE_WIDTH 32U

#define	XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU

XQSPIPSU Transfer Status Register information
This register contains bits for transfer status
#define	XQSPIPSU_XFER_STS_OFFSET 0X0000005CU
	Register: XQSPIPSU_XFER_STS. More...

#define	XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0U

#define	XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32U

#define	XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU

XQSPIPSU GEN_FIFO Snapshot Register information
This register contains bits for configuring GENFIFO
#define	XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U
	Register: XQSPIPSU_GF_SNAPSHOT. More...

#define	XQSPIPSU_GF_SNAPSHOT_SHIFT 0U

#define	XQSPIPSU_GF_SNAPSHOT_WIDTH 20U

#define	XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU

XQSPIPSU Receive Data Copy Register information
#define	XQSPIPSU_RX_COPY_OFFSET 0X00000064U
	Register: XQSPIPSU_RX_COPY. More...

#define	XQSPIPSU_RX_COPY_UPPER_SHIFT 8U

#define	XQSPIPSU_RX_COPY_UPPER_WIDTH 8U

#define	XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U

#define	XQSPIPSU_RX_COPY_LOWER_SHIFT 0U

#define	XQSPIPSU_RX_COPY_LOWER_WIDTH 8U

#define	XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU

XQSPIPSU Module Identification Register information
#define	XQSPIPSU_MOD_ID_OFFSET 0X000000FCU
	Register: XQSPIPSU_MOD_ID. More...

#define	XQSPIPSU_MOD_ID_SHIFT 0U

#define	XQSPIPSU_MOD_ID_WIDTH 32U

#define	XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU

XQSPIPSU DMA Transfer Register information
This register contains bits for configuring DMA
#define	XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U
	Register: XQSPIPSU_QSPIDMA_DST_ADDR. More...

#define	XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU

#define	XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U

#define	XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27U

#define	XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU

#define	XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U

#define	XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13U

#define	XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U

#define	XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8U

#define	XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U

#define	XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4U

#define	XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU

#define	XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U

#define	XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU

#define	XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU

#define	XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U

#define	XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32U

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU

XQSPIPSU Generic FIFO masks information
Generic FIFO masks information
#define	XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU
	Generic FIFO masks. More...

#define	XQSPIPSU_GENFIFO_DATA_XFER 0x100U

#define	XQSPIPSU_GENFIFO_EXP 0x200U

#define	XQSPIPSU_GENFIFO_MODE_SPI 0x400U

#define	XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U

#define	XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U

#define	XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */

#define	XQSPIPSU_GENFIFO_CS_LOWER 0x1000U

#define	XQSPIPSU_GENFIFO_CS_UPPER 0x2000U

#define	XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U

#define	XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U

#define	XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */

#define	XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */

#define	XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */

#define	XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */

#define	XQSPIPSU_GENFIFO_STRIPE 0x40000U

#define	XQSPIPSU_GENFIFO_POLL 0x80000U

XQSPIPSU RX Data Delay Register information
#define	XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U
	QSPI Data delay register. More...

#define	XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT 31U

#define	XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH 1U

#define	XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK 0X80000000U

#define	XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT 28U

#define	XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH 3U

#define	XQSPIPSU_DATA_DLY_ADJ_DLY_MASK 0X70000000U

TAPDLY Bypass register information
#define	IOU_TAPDLY_BYPASS_OFFSET 0X00000390U
	Tapdelay Bypass register. More...

#define	IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U

#define	IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U

#define	IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U

#define	IOU_TAPDLY_RESET_STATE 0x7U

Macro Definition Documentation

#define BYTES1024_PER_PAGE 1024U

1024 Bytes per Page

#define BYTES256_PER_PAGE 256U

Definitions for Intel, STM, Winbond and Spansion Serial Flash Device geometry.

256 Bytes per Page

#define BYTES512_PER_PAGE 512U

512 Bytes per Page

#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390U

Tapdelay Bypass register.

#define MAX_DELAY_CNT 1000000000U

Max delay count.

Referenced by XQspiPsu_PolledRecvData(), and XQspiPsu_PolledSendData().

#define MAX_DELAY_CNT 1000000000U

Max delay count.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashReadID(), FlashRegisterWrite(), FlashWrite(), MultiDieRead(), XQspiPsu_Abort(), XQspiPsu_CheckDmaDone(), XQspiPsu_PolledTransfer(), and XQspiPsu_StartDmaTransfer().

#define NUM_OF_SECTORS1024 1024U

1024 Sectors

#define NUM_OF_SECTORS128 128U

128 Sectors

#define NUM_OF_SECTORS16 16U

16 Sectors

#define NUM_OF_SECTORS2 2U

2 Sectors

#define NUM_OF_SECTORS2048 2048U

2048 Sectors

#define NUM_OF_SECTORS256 256U

256 Sectors

#define NUM_OF_SECTORS32 32U

32 Sectors

#define NUM_OF_SECTORS4 4U

4 Sectors

#define NUM_OF_SECTORS4096 4096U

4096 Sectors

#define NUM_OF_SECTORS512 512U

512 Sectors

#define NUM_OF_SECTORS64 64U

64 Sectors

#define NUM_OF_SECTORS8 8U

8 Sector

#define NUM_OF_SECTORS8192 8192U

8192 Sectors

#define PAGES1024_PER_SECTOR 1024U

1024 Pages per Sector

#define PAGES128_PER_SECTOR 128U

128 Pages per Sector

#define PAGES16_PER_SECTOR 16U

16 Pages per Sector

#define PAGES256_PER_SECTOR 256U

256 Pages per Sector

#define PAGES512_PER_SECTOR 512U

512 Pages per Sector

#define SECTOR_SIZE_128K 0X20000U

128K Sector

#define SECTOR_SIZE_256K 0X40000U

256K Sector

#define SECTOR_SIZE_512K 0X80000U

512K Sector

#define SECTOR_SIZE_64K 0X10000U

64K Sector

#define XQSPIPS_BASEADDR 0XFF0F0000U

QSPI Base Address.

Referenced by XQspiPsu_SetOptions().

#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )

Register: XQSPIPS_EN_REG.

#define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1U

Default LQSPI CFG value.

Referenced by XQspiPsu_SetOptions().

#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013U

Default 4 Byte LQSPI CR value.

Referenced by XQspiPsu_SetOptions().

#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FFU

Read instr code.

#define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003U

Default LQSPI CR value.

Referenced by XQspiPsu_SetOptions().

#define XQSPIPSU_CFG_OFFSET 0X00000000U

Register: XQSPIPSU_CFG.

Referenced by XQspiPsu_Abort(), XQspiPsu_CheckDmaDone(), XQspiPsu_ClearOptions(), XQspiPsu_GenFifoEntryData(), XQspiPsu_GetOptions(), XQspiPsu_IntrDummyDataTransfer(), XQspiPsu_PollDataConfig(), XQspiPsu_PolledMessageTransfer(), XQspiPsu_SetClkPrescaler(), XQspiPsu_SetDefaultConfig(), XQspiPsu_SetIOMode(), XQspiPsu_SetOptions(), XQspiPsu_SetReadMode(), XQspiPsu_SetWP(), and XQspiPsu_StartDmaTransfer().

#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U

Clk Active low option.

#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4U

Clk phase 1 option.

#define XQSPIPSU_CLK_PRESCALE_128 0x06U

Clock prescale 128.

#define XQSPIPSU_CLK_PRESCALE_16 0x03U

Clock prescale 16.

#define XQSPIPSU_CLK_PRESCALE_2 0x00U

Clock prescale 2.

#define XQSPIPSU_CLK_PRESCALE_256 0x07U

Clock prescale 256.

#define XQSPIPSU_CLK_PRESCALE_32 0x04U

Clock prescale 32.

#define XQSPIPSU_CLK_PRESCALE_4 0x01U

Clock prescale 4.

#define XQSPIPSU_CLK_PRESCALE_64 0x05U

Clock prescale 64.

#define XQSPIPSU_CLK_PRESCALE_8 0x02U

Clock prescale 8.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2U

Parallel mode connection.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashWrite(), GetRealAddr(), MultiDieRead(), QspiPsuConfigurePoll(), QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

#define XQSPIPSU_CONNECTION_MODE_SINGLE 0U

Single mode connection.

Referenced by GetRealAddr(), MultiDieRead(), and XQspiPsu_WriteProtectToggle().

#define XQSPIPSU_CONNECTION_MODE_STACKED 1U

Stacked mode connection.

Referenced by DieErase(), FlashErase(), and GetRealAddr().

#define XQSPIPSU_CR_PRESC_MAXIMUM 7U

Prescale max.

Referenced by XQspiPsu_SetClkPrescaler().

#define XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U

QSPI Data delay register.

#define XQspiPsu_Disable ( InstancePtr )

Value:

XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPSU_EN_OFFSET, 0x0U)

XQSPIPSU_EN_OFFSET

#define XQSPIPSU_EN_OFFSET

Register: XQSPIPSU_EN_REG.

Definition: xqspipsu_hw.h:380

XQspiPsu_Out32

#define XQspiPsu_Out32

Write the 32 bit register value.

Definition: xqspipsu_hw.h:965

Disable QSPI controller.

#define XQSPIPSU_DMA_BYTES_MAX 0x10000000U

DMA bytes max.

Referenced by XQspiPsu_InterruptTransfer(), XQspiPsu_PolledTransfer(), and XQspiPsu_StartDmaTransfer().

#define XQSPIPSU_EN_OFFSET 0X00000014U

Register: XQSPIPSU_EN_REG.

Referenced by XQspiPsu_Idle(), and XQspiPsu_SetOptions().

#define XQspiPsu_Enable ( InstancePtr )

Value:

XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)

XQSPIPSU_EN_OFFSET

#define XQSPIPSU_EN_OFFSET

Register: XQSPIPSU_EN_REG.

Definition: xqspipsu_hw.h:380

XQspiPsu_Out32

#define XQspiPsu_Out32

Write the 32 bit register value.

Definition: xqspipsu_hw.h:965

Enable QSPI Controller.

Referenced by XQspiPsu_CfgInitialize().

#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU

Register: XQSPIPSU_FIFO_CTRL.

Referenced by XQspiPsu_Abort().

#define XQSPIPSU_FREQ_100MHZ 100000000U

Frequency 100 Mhz.

#define XQSPIPSU_FREQ_150MHZ 150000000U

Frequency 150 Mhz.

#define XQSPIPSU_FREQ_37_5MHZ 37500000U

Frequency 375 Mhz.

Referenced by XQspiPsu_SetClkPrescaler().

#define XQSPIPSU_FREQ_40MHZ 40000000U

Frequency 40 Mhz.

#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U

Register: XQSPIPSU_GEN_FIFO.

Referenced by XQspiPsu_GenFifoEntryData(), XQspiPsu_GenFifoEntryDataLen(), and XQspiPsu_PollDataConfig().

#define XQSPIPSU_GENFIFO_CS_HOLD 0x04U

Chip select hold in GENFIFO.

#define XQSPIPSU_GENFIFO_CS_SETUP 0x05U

Chip select setup in GENFIO.

#define XQSPIPSU_GENFIFO_EXP_START 0x100U

Genfifo start.

Referenced by XQspiPsu_GenFifoEntryDataLen().

#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU

Generic FIFO masks.

Referenced by XQspiPsu_GenFifoEntryDataLen().

#define XQspiPsu_GetLqspiConfigReg ( InstancePtr )

Value:

XQspiPsu_In32((XQSPIPS_BASEADDR) + \

XQSPIPSU_LQSPI_CR_OFFSET)

XQSPIPSU_LQSPI_CR_OFFSET

#define XQSPIPSU_LQSPI_CR_OFFSET

Register: XQSPIPSU_LQSPI.

Definition: xqspipsu_hw.h:146

XQspiPsu_In32

#define XQspiPsu_In32

Read the 32 bit register value.

Definition: xqspipsu_hw.h:964

XQSPIPS_BASEADDR

#define XQSPIPS_BASEADDR

QSPI Base Address.

Definition: xqspipsu_hw.h:64

Read Configuration register of LQSPI Controller.

Referenced by XQspiPsu_LqspiRead().

#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U

Register: XQSPIPSU_GF_SNAPSHOT.

#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U

Register: XQSPIPSU_GF_THRESHOLD.

Referenced by XQspiPsu_SetDefaultConfig().

#define XQSPIPSU_GPIO_OFFSET 0X00000030U

Register: XQSPIPSU_GPIO.

Referenced by XQspiPsu_WriteProtectToggle().

#define XQSPIPSU_H_

< prevent circular inclusions

by using protection macros

#define XQSPIPSU_HW_H

< prevent circular inclusions

by using protection macros

#define XQSPIPSU_IDR_OFFSET 0X0000000CU

Register: XQSPIPSU_IDR.

Referenced by XQspiPsu_Abort(), XQspiPsu_IntrDummyDataTransfer(), and XQspiPsu_PollDataHandler().

#define XQSPIPSU_IER_OFFSET 0X00000008U

Register: XQSPIPSU_IER.

Referenced by XQspiPsu_InterruptTransfer(), and XQspiPsu_PollDataConfig().

#define XQSPIPSU_IMR_OFFSET 0X00000010U

Register: XQSPIPSU_IMR.

#define XQspiPsu_In32 Xil_In32

Read the 32 bit register value.

#define XQSPIPSU_ISR_OFFSET 0X00000004U

Register: XQSPIPSU_ISR.

Referenced by XQspiPsu_Abort(), XQspiPsu_CheckDmaDone(), XQspiPsu_IntrDataTransfer(), XQspiPsu_PolledMessageTransfer(), XQspiPsu_PolledRecvData(), XQspiPsu_PolledSendData(), XQspiPsu_PolledTransfer(), and XQspiPsu_StartDmaTransfer().

#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U

Register: XQSPIPSU_LPBK_DLY_ADJ.

Referenced by XQspiPsu_SetDefaultConfig().

#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000U

Upper memory page.

#define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U

LQSPI mode enable.

Referenced by XQspiPsu_LqspiRead(), and XQspiPsu_SetOptions().

#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000U

Mode value for dual I/O or quad I/O.

#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000U

Enable mode bits.

#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000U

Mode on.

#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U

Register: XQSPIPSU_LQSPI.

Referenced by XQspiPsu_SetOptions().

#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000U

Separate memory bus.

#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U

Both memories or one.

#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000U

Upper memory page.

#define XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB 1U

LQSPI less Than 16 MB.

Referenced by XQspiPsu_SetOptions().

#define XQSPIPSU_LQSPI_MODE_OPTION 0x20U

LQSPI mode option.

Referenced by XQspiPsu_SetOptions().

#define XQSPIPSU_MANUAL_START_OPTION 0x8U

Manual start option.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), QspiPsuWriteProtectFlashExample(), XQspiPsu_ClearOptions(), and XQspiPsu_SetOptions().

#define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU

Register: XQSPIPSU_MOD_ID.

#define XQSPIPSU_MSG_FLAG_POLL 0x8U

POLL Msg flag.

Referenced by QspiPsuConfigurePoll(), XQspiPsu_InterruptHandler(), and XQspiPsu_InterruptTransfer().

#define XQSPIPSU_MSG_FLAG_RX 0x2U

#define XQSPIPSU_MSG_FLAG_STRIPE 0x1U

Stripe Msg flag.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashWrite(), MultiDieRead(), QspiPsuConfigurePoll(), XQspiPsu_GenFifoEntryData(), and XQspiPsu_PollDataConfig().

#define XQSPIPSU_MSG_FLAG_TX 0x4U

Tx Msg flag.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashReadID(), FlashRegisterRead(), FlashRegisterWrite(), FlashWrite(), MultiDieRead(), XQspiPsu_InterruptHandler(), XQspiPsu_IntrDataTransfer(), XQspiPsu_PolledMessageTransfer(), and XQspiPsu_TXRXSetup().

#define XQSPIPSU_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))

Number of options in option table.

Referenced by XQspiPsu_ClearOptions(), XQspiPsu_GetOptions(), and XQspiPsu_SetOptions().

#define XQspiPsu_Out32 Xil_Out32

Write the 32 bit register value.

#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U

Register: XQSPIPSU_POLL_CFG.

Referenced by XQspiPsu_PollDataConfig().

#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U

Register: XQSPIPSU_QSPIDMA_DST_ADDR.

Referenced by XQspiPsu_Setup64BRxDma(), and XQspiPsu_SetupRxDma().

#define XQSPIPSU_READMODE_DMA 0x0U

DMA read mode.

Referenced by XQspiPsu_Abort(), XQspiPsu_CfgInitialize(), XQspiPsu_GenFifoEntryData(), XQspiPsu_InterruptTransfer(), XQspiPsu_IntrDataTransfer(), XQspiPsu_IntrDummyDataTransfer(), XQspiPsu_IntrRecvData(), XQspiPsu_PollDataHandler(), XQspiPsu_PolledMessageTransfer(), XQspiPsu_PolledRecvData(), XQspiPsu_RXSetup(), XQspiPsu_SetReadMode(), and XQspiPsu_StartDmaTransfer().

#define XQSPIPSU_READMODE_IO 0x1U

IO read mode.

Referenced by XQspiPsu_GenFifoEntryData(), XQspiPsu_SetIOMode(), XQspiPsu_SetReadMode(), and XQspiPsu_StartDmaTransfer().

#define XQspiPsu_ReadReg	(	BaseAddress,
		RegOffset
	)	XQspiPsu_In32((BaseAddress) + (RegOffset))

Read a register.

Parameters

BaseAddress	contains the base address of the device.
RegOffset	contains the offset from the 1st register of the device to the target register.

Returns: The value read from the register.

Note: C-Style signature: u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)

Referenced by XQspiPsu_Abort(), XQspiPsu_CheckDmaDone(), XQspiPsu_ClearOptions(), XQspiPsu_GenFifoEntryData(), XQspiPsu_GetOptions(), XQspiPsu_Idle(), XQspiPsu_IntrDataTransfer(), XQspiPsu_IntrDummyDataTransfer(), XQspiPsu_IORead(), XQspiPsu_PollDataConfig(), XQspiPsu_PollDataHandler(), XQspiPsu_PolledMessageTransfer(), XQspiPsu_PolledRecvData(), XQspiPsu_ReadRxFifo(), XQspiPsu_SetClkPrescaler(), XQspiPsu_SetDefaultConfig(), XQspiPsu_SetIOMode(), XQspiPsu_SetOptions(), XQspiPsu_SetReadMode(), XQspiPsu_SetWP(), and XQspiPsu_StartDmaTransfer().

#define XQSPIPSU_RX_COPY_OFFSET 0X00000064U

Register: XQSPIPSU_RX_COPY.

#define XQSPIPSU_RXADDR_OVER_32BIT 0x100000000U

Rx address over 32 bit.

Referenced by XQspiPsu_CheckDmaDone(), XQspiPsu_IntrRecvData(), XQspiPsu_PolledRecvData(), and XQspiPsu_RXSetup().

#define XQSPIPSU_RXD_OFFSET 0X00000020U

Register: XQSPIPSU_RXD.

Referenced by XQspiPsu_PollDataHandler(), and XQspiPsu_ReadRxFifo().

#define XQSPIPSU_SEL_OFFSET 0X00000044U

Register: XQSPIPSU_SEL.

#define XQspiPsu_Select	(	InstancePtr,
		Mask
	)

Value:

XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPSU_SEL_OFFSET, (Mask))

XQSPIPSU_SEL_OFFSET

#define XQSPIPSU_SEL_OFFSET

Register: XQSPIPSU_SEL.

Definition: xqspipsu_hw.h:504

XQspiPsu_Out32

#define XQspiPsu_Out32

Write the 32 bit register value.

Definition: xqspipsu_hw.h:965

select QSPI controller

Referenced by XQspiPsu_CfgInitialize().

#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U

Select both bus flash.

Referenced by GetRealAddr(), QspiPsuConfigurePoll(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U

Select lower bus flash.

Referenced by FlashErase(), GetRealAddr(), QspiPsuConfigurePoll(), QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), QspiPsuWriteProtectFlashExample(), XQspiPsu_CreatePollDataConfig(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U

Select upper bus flash.

Referenced by XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U

Select both flash.

Referenced by GetRealAddr(), QspiPsuConfigurePoll(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U

Select lower flash.

Referenced by FlashErase(), GetRealAddr(), QspiPsuConfigurePoll(), QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), QspiPsuWriteProtectFlashExample(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U

Select upper flash.

Referenced by FlashErase(), GetRealAddr(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2U

Select dual SPI mode.

Referenced by FlashRead(), MultiDieRead(), and XQspiPsu_SelectSpiMode().

#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4U

Select quad SPI mode.

Referenced by FlashRead(), MultiDieRead(), and XQspiPsu_SelectSpiMode().

#define XQSPIPSU_SELECT_MODE_SPI 0x1U

Select SPI mode.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashReadID(), FlashRegisterRead(), FlashRegisterWrite(), FlashWrite(), MultiDieRead(), QspiPsuConfigurePoll(), and XQspiPsu_SelectSpiMode().

#define XQSPIPSU_SET_WP 1

GQSPI configuration to toggle WP of flash.

Referenced by QspiPsuWriteProtectFlashExample().

#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U

Register: XQSPIPSU_TX_THRESHOLD.

Referenced by XQspiPsu_SetDefaultConfig().

#define XQSPIPSU_TXD_OFFSET 0X0000001CU

Register: XQSPIPSU_TXD.

Referenced by XQspiPsu_FillTxFifo().

#define XQspiPsu_WriteReg	(	BaseAddress,
		RegOffset,
		RegisterValue
	)	XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))

Write to a register.

Parameters

BaseAddress	contains the base address of the device.
RegOffset	contains the offset from the 1st register of the device to target register.
RegisterValue	is the value to be written to the register.

Returns: None.

Note: C-Style signature: void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset, u32 RegisterValue)XQSPIPSU_H

Referenced by XQspiPsu_Abort(), XQspiPsu_CheckDmaDone(), XQspiPsu_ClearOptions(), XQspiPsu_FillTxFifo(), XQspiPsu_GenFifoEntryData(), XQspiPsu_GenFifoEntryDataLen(), XQspiPsu_Idle(), XQspiPsu_InterruptTransfer(), XQspiPsu_IntrDataTransfer(), XQspiPsu_IntrDummyDataTransfer(), XQspiPsu_PollDataConfig(), XQspiPsu_PollDataHandler(), XQspiPsu_PolledMessageTransfer(), XQspiPsu_PolledRecvData(), XQspiPsu_SetClkPrescaler(), XQspiPsu_SetDefaultConfig(), XQspiPsu_SetIOMode(), XQspiPsu_SetOptions(), XQspiPsu_SetReadMode(), XQspiPsu_Setup64BRxDma(), XQspiPsu_SetupRxDma(), XQspiPsu_SetWP(), XQspiPsu_StartDmaTransfer(), and XQspiPsu_WriteProtectToggle().

#define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU

Register: XQSPIPSU_XFER_STS.

Typedef Documentation

typedef void(* XQspiPsu_StatusHandler)(const void *CallBackRef, u32 StatusEvent, u32 ByteCount)

The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device.

The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler executes in an interrupt context, so only minimal processing should be performed.

Parameters

CallBackRef	is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer.
StatusEvent	holds one or more status events that have occurred. See the XQspiPsu_SetStatusHandler() for details on the status events that can be passed in the callback.
ByteCount	indicates how many bytes of data were successfully transferred. This may be less than the number of bytes requested if the status event indicates an error.

Function Documentation

void XQspiPsu_Abort ( XQspiPsu * InstancePtr )

Aborts a transfer in progress.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::GenFifoEntries, XQspiPsu::IsBusy, MAX_DELAY_CNT, XQspiPsu::ReadMode, XQspiPsu::RxBytes, XQspiPsu::TxBytes, XQSPIPSU_CFG_OFFSET, XQSPIPSU_FIFO_CTRL_OFFSET, XQSPIPSU_IDR_OFFSET, XQSPIPSU_ISR_OFFSET, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_Reset().

s32 XQspiPsu_CfgInitialize	(	XQspiPsu *	InstancePtr,
		const XQspiPsu_Config *	ConfigPtr,
		UINTPTR	EffectiveAddr
	)

Initializes a specific XQspiPsu instance as such the driver is ready to use.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
ConfigPtr	is a reference to a structure containing information about a specific QSPIPSU device. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
EffectiveAddr	is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->Config.BaseAddress for this device.

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Config::BusWidth, XQspiPsu::Config, XQspiPsu_Config::ConnectionMode, XQspiPsu::GenFifoBufferPtr, XQspiPsu::GenFifoBus, XQspiPsu::GenFifoCS, XQspiPsu::GenFifoEntries, XQspiPsu_Config::InputClockHz, XQspiPsu::IsBusy, XQspiPsu_Config::IsCacheCoherent, XQspiPsu_Config::IsFbClock, XQspiPsu::IsManualstart, XQspiPsu::IsReady, XQspiPsu::IsUnaligned, XQspiPsu::ReadMode, XQspiPsu::RecvBufferPtr, XQspiPsu::RxBytes, XQspiPsu::SendBufferPtr, XQspiPsu::StatusHandler, XQspiPsu::TxBytes, XQspiPsu_Enable, XQSPIPSU_READMODE_DMA, XQspiPsu_Reset(), and XQspiPsu_Select.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

s32 XQspiPsu_CheckDmaDone ( XQspiPsu * InstancePtr )

This function check for DMA transfer complete.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns

XST_SUCCESS if DMA transfer complete.
XST_FAILURE if DMA transfer is not completed.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu_Config::IsCacheCoherent, XQspiPsu::IsManualstart, XQspiPsu::IsReady, MAX_DELAY_CNT, XQspiPsu::Msg, XQspiPsu_Msg::RxAddr64bit, XQspiPsu_Msg::RxBfrPtr, XQspiPsu::RxBytes, XQspiPsu_Msg::Xfer64bit, XQSPIPSU_CFG_OFFSET, XQSPIPSU_ISR_OFFSET, XQspiPsu_ReadReg, XQSPIPSU_RXADDR_OVER_32BIT, and XQspiPsu_WriteReg.

s32 XQspiPsu_ClearOptions	(	XQspiPsu *	InstancePtr,
		u32	Options
	)

This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus.

The device must be idle rather than busy transferring data before setting these device options.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Options	contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned OFF and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

Note: This function is not thread-safe.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsManualstart, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_NUM_OPTIONS, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

u32 XQspiPsu_CreatePollDataConfig	(	const XQspiPsu *	InstancePtr,
		const XQspiPsu_Msg *	FlashMsg
	)

This function creates Poll config register data to write.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
FlashMsg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

References XQspiPsu::GenFifoBus, XQspiPsu::IsReady, XQspiPsu_Msg::PollBusMask, XQspiPsu_Msg::PollData, and XQSPIPSU_SELECT_FLASH_BUS_LOWER.

Referenced by XQspiPsu_PollDataConfig().

void XQspiPsu_FillTxFifo	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	Size
	)

Fills the TX FIFO as long as there is room in the FIFO or the bytes required to be transmitted.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
Size	is the number of bytes to be transmitted.

Returns: None

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu_Msg::TxBfrPtr, XQspiPsu::TxBytes, XQSPIPSU_TXD_OFFSET, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_IntrSendData(), XQspiPsu_PolledSendData(), and XQspiPsu_TXSetup().

void XQspiPsu_GenFifoEntryData	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function writes the GENFIFO entries to transmit the messages requested.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::BusWidth, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::GenFifoBus, XQspiPsu::GenFifoCS, XQspiPsu::IsReady, XQspiPsu::IsUnaligned, XQspiPsu::ReadMode, XQSPIPSU_CFG_OFFSET, XQSPIPSU_GEN_FIFO_OFFSET, XQspiPsu_GenFifoEntryDataLen(), XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_STRIPE, XQSPIPSU_READMODE_DMA, XQSPIPSU_READMODE_IO, XQspiPsu_ReadReg, XQspiPsu_SelectSpiMode(), XQspiPsu_TXRXSetup(), and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptTransfer(), XQspiPsu_IntrDummyDataTransfer(), XQspiPsu_IntrRecvData(), XQspiPsu_PolledMessageTransfer(), and XQspiPsu_StartDmaTransfer().

void XQspiPsu_GenFifoEntryDataLen	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32 *	GenFifoEntry
	)

This function writes the Data length to GENFIFO entries that need to be transmitted or received.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
GenFifoEntry	is index of the current message to be handled.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu::IsReady, XQSPIPSU_GEN_FIFO_OFFSET, XQSPIPSU_GENFIFO_EXP_START, XQSPIPSU_GENFIFO_IMM_DATA_MASK, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_GenFifoEntryData().

u32 XQspiPsu_GetOptions ( const XQspiPsu * InstancePtr )

This function gets the options for the QSPIPSU device.

The options control how the device behaves relative to the QSPIPSU bus.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns

Options contains the specified options currently set. This is a bit value where a 1 means the option is on, and a 0 means the option is off. See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, XQSPIPSU_NUM_OPTIONS, and XQspiPsu_ReadReg.

void XQspiPsu_Idle ( const XQspiPsu * InstancePtr )

Stops the transfer of data to internal DST FIFO from stream interface and also stops the issuing of new write commands to memory.

By calling this API, any ongoing Dma transfers will be paused and DMA will not issue AXI write commands to memory

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQSPIPSU_EN_OFFSET, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

s32 XQspiPsu_InterruptHandler ( XQspiPsu * InstancePtr )

Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.

Note: None.

References XQspiPsu_Msg::Flags, XQspiPsu::IsReady, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu_IntrDataTransfer(), XQspiPsu_IntrDummyDataTransfer(), XQSPIPSU_MSG_FLAG_POLL, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_TX, and XQspiPsu_PollDataHandler().

Referenced by QspiPsuInterruptFlashExample(), and QspiPsuWriteProtectFlashExample().

s32 XQspiPsu_InterruptTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

This function initiates a transfer on the bus and enables interrupts.

The transfer is completed by the interrupt handler. The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
NumMsg	is the number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu::ReadMode, XQSPIPSU_DMA_BYTES_MAX, XQspiPsu_GenFifoEntryData(), XQSPIPSU_IER_OFFSET, XQSPIPSU_MSG_FLAG_POLL, XQSPIPSU_MSG_FLAG_RX, XQspiPsu_PollDataConfig(), XQSPIPSU_READMODE_DMA, and XQspiPsu_WriteReg.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashReadID(), FlashWrite(), and MultiDieRead().

void XQspiPsu_IntrDataTransfer	(	XQspiPsu *	InstancePtr,
		u32 *	QspiPsuStatusReg,
		u8 *	DeltaMsgCnt
	)

This function transfers Tx and Rx data.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
QspiPsuStatusReg	is the status of QSPI status register.
DeltaMsgCnt	is the message count flag.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu::ReadMode, XQspiPsu::StatusHandler, XQspiPsu::StatusRef, XQspiPsu_IntrRecvData(), XQspiPsu_IntrSendData(), XQSPIPSU_ISR_OFFSET, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_TX, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptHandler().

void XQspiPsu_IntrDummyDataTransfer	(	XQspiPsu *	InstancePtr,
		u32	QspiPsuStatusReg,
		u8	DeltaMsgCnt
	)

This function transfers Dummy byte.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
QspiPsuStatusReg	is the status of QSPI status register.
DeltaMsgCnt	is the message count flag.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsUnaligned, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu::ReadMode, XQspiPsu::StatusHandler, XQspiPsu::StatusRef, XQSPIPSU_CFG_OFFSET, XQspiPsu_GenFifoEntryData(), XQSPIPSU_IDR_OFFSET, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptHandler().

void XQspiPsu_IntrRecvData	(	XQspiPsu *	InstancePtr,
		u32	QspiPsuStatusReg,
		u32	DmaIntrStatusReg,
		u8 *	DeltaMsgCnt
	)

This function performs a transfer of Rx data on the busin interrupt mode.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
QspiPsuStatusReg	is the status QSPI status register.
DmaIntrStatusReg	is the status DMA interrupt register.
DeltaMsgCnt	is the message count flag.

Returns: None.

Note: None.

References XQspiPsu::Config, XQspiPsu_Config::IsCacheCoherent, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::ReadMode, XQspiPsu::RxBytes, XQspiPsu_GenFifoEntryData(), XQspiPsu_IORead(), XQSPIPSU_READMODE_DMA, XQSPIPSU_RXADDR_OVER_32BIT, and XQspiPsu_SetIOMode().

Referenced by XQspiPsu_IntrDataTransfer().

void XQspiPsu_IntrSendData	(	XQspiPsu *	InstancePtr,
		u32	QspiPsuStatusReg,
		u8 *	DeltaMsgCnt
	)

This function performs a transfer of Tx data on the bus in interrupt mode.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
QspiPsuStatusReg	is the status QSPI status register.
DeltaMsgCnt	is the message count flag.

Returns: None.

Note: None.

References XQspiPsu_Msg::Flags, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::TxBytes, XQspiPsu_FillTxFifo(), and XQSPIPSU_MSG_FLAG_RX.

Referenced by XQspiPsu_IntrDataTransfer().

void XQspiPsu_IORead	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	StatusReg
	)

This function reads data from RXFifo in IO mode.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
StatusReg	is the Interrupt status Register value.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu::RxBytes, XQspiPsu_ReadReg, and XQspiPsu_ReadRxFifo().

Referenced by XQspiPsu_IntrRecvData(), and XQspiPsu_PolledRecvData().

XQspiPsu_Config * XQspiPsu_LookupConfig ( u16 DeviceId )

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters

DeviceId contains the ID of the device to look up the configuration for.

Returns: A pointer to the configuration found or NULL if the specified device ID was not found. See xqspipsu.h for the definition of XQspiPsu_Config.

Note: None.

References XQspiPsu_ConfigTable.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

void XQspiPsu_PollDataConfig	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	FlashMsg
	)

This function enables the polling functionality of controller.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
FlashMsg	is a pointer to the structure containing transfer data

Returns: None

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::GenFifoBus, XQspiPsu::GenFifoCS, XQspiPsu::IsReady, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu_Msg::PollStatusCmd, XQspiPsu_Msg::PollTimeout, XQSPIPSU_CFG_OFFSET, XQspiPsu_CreatePollDataConfig(), XQSPIPSU_GEN_FIFO_OFFSET, XQSPIPSU_IER_OFFSET, XQSPIPSU_MSG_FLAG_STRIPE, XQSPIPSU_POLL_CFG_OFFSET, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptTransfer().

void XQspiPsu_PollDataHandler	(	XQspiPsu *	InstancePtr,
		u32	StatusReg
	)

This is the handler for polling functionality of controller.

It reads data from RXFIFO, since when data from the flash device (status data) matched with configured value in poll_cfg, then controller writes the matched data into RXFIFO.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
StatusReg	is the Interrupt status Register value.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQspiPsu::ReadMode, XQspiPsu::StatusHandler, XQspiPsu::StatusRef, XQSPIPSU_IDR_OFFSET, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, XQSPIPSU_RXD_OFFSET, XQspiPsu_SetReadMode(), and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptHandler().

s32 XQspiPsu_PolledMessageTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

This function performs a transfer on the bus in polled mode.

The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
NumMsg	is the number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsUnaligned, XQspiPsu::ReadMode, XQspiPsu::RxBytes, XQspiPsu::TxBytes, XQSPIPSU_CFG_OFFSET, XQspiPsu_GenFifoEntryData(), XQSPIPSU_ISR_OFFSET, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_TX, XQspiPsu_PolledRecvData(), XQspiPsu_PolledSendData(), XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_PolledTransfer().

s32 XQspiPsu_PolledRecvData	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		s32	Index,
		u32 *	IOPending
	)

This function transfers Rx data on the bus in polled mode.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
Index	is the Msg index to transfer.
IOPending	is the .

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Config::IsCacheCoherent, MAX_DELAY_CNT, XQspiPsu::ReadMode, XQspiPsu::RxBytes, XQspiPsu_IORead(), XQSPIPSU_ISR_OFFSET, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, XQSPIPSU_RXADDR_OVER_32BIT, XQspiPsu_SetIOMode(), and XQspiPsu_WriteReg.

Referenced by XQspiPsu_PolledMessageTransfer().

s32 XQspiPsu_PolledSendData	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		s32	Index
	)

This function transfers Tx data on the bus in polled mode.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
Index	is the Msg index to transfer.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, MAX_DELAY_CNT, XQspiPsu::TxBytes, XQspiPsu_FillTxFifo(), and XQSPIPSU_ISR_OFFSET.

Referenced by XQspiPsu_PolledMessageTransfer().

s32 XQspiPsu_PolledTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

This function performs a transfer on the bus in polled mode.

The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
NumMsg	is the number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::IsBusy, XQspiPsu::IsReady, MAX_DELAY_CNT, XQSPIPSU_DMA_BYTES_MAX, XQSPIPSU_ISR_OFFSET, XQSPIPSU_MSG_FLAG_RX, and XQspiPsu_PolledMessageTransfer().

Referenced by FlashRegisterRead(), and FlashRegisterWrite().

void XQspiPsu_ReadRxFifo	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		s32	Size
	)

Read the specified number of bytes from RX FIFO.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
Size	is the number of bytes to be read.

Returns: None

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu_Msg::RxBfrPtr, XQspiPsu::RxBytes, XQspiPsu_ReadReg, and XQSPIPSU_RXD_OFFSET.

Referenced by XQspiPsu_IORead().

void XQspiPsu_Reset ( XQspiPsu * InstancePtr )

Resets the QSPIPSU device.

Reset must only be called after the driver has been initialized. Any data transfer that is in progress is aborted.

The upper layer software is responsible for re-configuring (if necessary) and restarting the QSPIPSU device after the reset.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns: None.

Note: None.

References XQspiPsu_Abort(), and XQspiPsu_SetDefaultConfig().

Referenced by XQspiPsu_CfgInitialize().

void XQspiPsu_RXSetup	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function checks the RX buffers in the message and setup the RX DMA as required.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

References XQspiPsu_Msg::ByteCount, XQspiPsu::IsReady, XQspiPsu::ReadMode, XQspiPsu_Msg::RxAddr64bit, XQspiPsu::RxBytes, XQspiPsu_Msg::Xfer64bit, XQSPIPSU_READMODE_DMA, XQSPIPSU_RXADDR_OVER_32BIT, XQspiPsu_Setup64BRxDma(), and XQspiPsu_SetupRxDma().

Referenced by XQspiPsu_TXRXSetup().

void XQspiPsu_SelectFlash	(	XQspiPsu *	InstancePtr,
		u8	FlashCS,
		u8	FlashBus
	)

This function should be used to tell the QSPIPSU driver the HW flash configuration being used.

This API should be called at least once in the application. If desired, it can be called multiple times when switching between communicating to different flahs devices/using different configs.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
FlashCS	- Flash Chip Select.
FlashBus	- Flash Bus (Upper, Lower or Both).

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

Note: If this function is not called at least once in the application, the driver assumes there is a single flash connected to the lower bus and CS line.

References XQspiPsu::GenFifoBus, XQspiPsu::GenFifoCS, XQspiPsu::IsReady, XQSPIPSU_SELECT_FLASH_BUS_BOTH, XQSPIPSU_SELECT_FLASH_BUS_LOWER, XQSPIPSU_SELECT_FLASH_BUS_UPPER, XQSPIPSU_SELECT_FLASH_CS_BOTH, XQSPIPSU_SELECT_FLASH_CS_LOWER, and XQSPIPSU_SELECT_FLASH_CS_UPPER.

Referenced by FlashErase(), GetRealAddr(), QspiPsuConfigurePoll(), QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

u32 XQspiPsu_SelectSpiMode ( u8 SpiMode )

Selects SPI mode - x1 or x2 or x4.

Parameters

SpiMode - spi or dual or quad.

Returns: Mask to set desired SPI mode in GENFIFO entry.

Note: None.

References XQSPIPSU_SELECT_MODE_DUALSPI, XQSPIPSU_SELECT_MODE_QUADSPI, and XQSPIPSU_SELECT_MODE_SPI.

Referenced by XQspiPsu_GenFifoEntryData().

s32 XQspiPsu_SetClkPrescaler	(	const XQspiPsu *	InstancePtr,
		u8	Prescaler
	)

Configures the clock according to the prescaler passed.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Prescaler	- clock prescaler to be set.

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started.
XST_DEVICE_BUSY if the device is currently transferring data. It must be stopped to re-initialize.
XST_FAILURE if Prescaler value is less than FreqDiv when feedback clock is not enabled.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Config::InputClockHz, XQspiPsu::IsBusy, XQspiPsu_Config::IsFbClock, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, XQSPIPSU_CR_PRESC_MAXIMUM, XQSPIPSU_FREQ_37_5MHZ, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

void XQspiPsu_SetDefaultConfig ( XQspiPsu * InstancePtr )

Enable and initialize DMA Mode, set little endain, disable poll timeout, clear prescalar bits and reset thresholds.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQSPIPSU_CFG_OFFSET, XQSPIPSU_GF_THRESHOLD_OFFSET, XQSPIPSU_LPBK_DLY_ADJ_OFFSET, XQspiPsu_ReadReg, XQSPIPSU_TX_THRESHOLD_OFFSET, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_Reset().

u32 XQspiPsu_SetIOMode	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function reads remaining bytes, after the completion of a DMA transfer, using IO mode.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu::IsUnaligned, XQspiPsu::ReadMode, XQspiPsu_Msg::RxBfrPtr, XQspiPsu::RxBytes, XQSPIPSU_CFG_OFFSET, XQSPIPSU_READMODE_IO, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_IntrRecvData(), and XQspiPsu_PolledRecvData().

s32 XQspiPsu_SetOptions	(	XQspiPsu *	InstancePtr,
		u32	Options
	)

This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus.

The device must be idle rather than busy transferring data before setting these device options.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Options	contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned ON and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

Note: This function is not thread-safe.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsManualstart, XQspiPsu::IsReady, XQSPIPS_BASEADDR, XQSPIPS_LQSPI_CFG_RST_STATE, XQSPIPS_LQSPI_CR_4_BYTE_STATE, XQSPIPS_LQSPI_CR_RST_STATE, XQSPIPSU_CFG_OFFSET, XQSPIPSU_EN_OFFSET, XQSPIPSU_LQSPI_CR_LINEAR_MASK, XQSPIPSU_LQSPI_CR_OFFSET, XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB, XQSPIPSU_LQSPI_MODE_OPTION, XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_NUM_OPTIONS, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

s32 XQspiPsu_SetReadMode	(	XQspiPsu *	InstancePtr,
		u32	Mode
	)

This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Mode	contains the specified Mode to be set. See the bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting Mode.

Note: This function is not thread-safe.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQspiPsu::ReadMode, XQSPIPSU_CFG_OFFSET, XQSPIPSU_READMODE_DMA, XQSPIPSU_READMODE_IO, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_PollDataHandler().

void XQspiPsu_SetStatusHandler	(	XQspiPsu *	InstancePtr,
		void *	CallBackRef,
		XQspiPsu_StatusHandler	FuncPointer
	)

Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software.

The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.

XST_SPI_TRANSFER_DONE           The requested data transfer is done

XST_SPI_TRANSMIT_UNDERRUN       As a slave device, the master clocked data
                        but there were none available in the transmit
                        register/FIFO. This typically means the slave
                        application did not issue a transfer request
                        fast enough, or the processor/driver could not
                        fill the transmit register/FIFO fast enough.

XST_SPI_RECEIVE_OVERRUN The QSPIPSU device lost data. Data was received
                        but the receive data register/FIFO was full.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
CallBackRef	is the upper layer callback reference passed back when the callback function is invoked.
FuncPointer	is the pointer to the callback function.

Returns: None.

Note

The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.

References XQspiPsu::IsReady, XQspiPsu::StatusHandler, and XQspiPsu::StatusRef.

Referenced by QspiPsuInterruptFlashExample(), and QspiPsuWriteProtectFlashExample().

void XQspiPsu_Setup64BRxDma	(	const XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function sets up the RX DMA operation on a 32bit Machine For 64bit Dma transfers.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu_Msg::RxAddr64bit, XQspiPsu::RxBytes, XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_RXSetup().

void XQspiPsu_SetupRxDma	(	const XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function sets up the RX DMA operation.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu_Config::IsCacheCoherent, XQspiPsu::IsReady, XQspiPsu_Msg::RxBfrPtr, XQspiPsu::RxBytes, XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_RXSetup().

void XQspiPsu_SetWP	(	const XQspiPsu *	InstancePtr,
		u8	Value
	)

This function sets the Write Protect and Hold options for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Write Protect and Hold options.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Value	of the WP_HOLD bit in configuration register

Returns: None

Note: This function is not thread-safe. This function can only be used with single flash configuration and x1/x2 data mode. This function cannot be used with x4 data mode and dual parallel and stacked flash configuration.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by QspiPsuWriteProtectFlashExample().

s32 XQspiPsu_StartDmaTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

This function start a DMA transfer.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
NumMsg	is the number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if ByteCount is greater than XQSPIPSU_DMA_BYTES_MAX.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::IsBusy, XQspiPsu::IsManualstart, XQspiPsu::IsReady, MAX_DELAY_CNT, XQspiPsu::Msg, XQspiPsu::ReadMode, XQspiPsu::TxBytes, XQSPIPSU_CFG_OFFSET, XQSPIPSU_DMA_BYTES_MAX, XQspiPsu_GenFifoEntryData(), XQSPIPSU_ISR_OFFSET, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_READMODE_DMA, XQSPIPSU_READMODE_IO, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

void XQspiPsu_TXRXSetup	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32 *	GenFifoEntry
	)

This function checks the TX/RX buffers in the message and setups up the GENFIFO entries, TX FIFO or RX DMA as required.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
GenFifoEntry	is pointer to the variable in which GENFIFO mask is returned to calling function

Returns: None

Note: None.

References XQspiPsu_Msg::Flags, XQspiPsu::IsReady, XQspiPsu::RecvBufferPtr, XQspiPsu::RxBytes, XQspiPsu::SendBufferPtr, XQspiPsu::TxBytes, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_TX, XQspiPsu_RXSetup(), and XQspiPsu_TXSetup().

Referenced by XQspiPsu_GenFifoEntryData().

void XQspiPsu_TXSetup	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function checks the TX buffer in the message and setup the TX FIFO as required.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

References XQspiPsu_Msg::ByteCount, XQspiPsu::IsReady, XQspiPsu::SendBufferPtr, XQspiPsu_Msg::TxBfrPtr, XQspiPsu::TxBytes, and XQspiPsu_FillTxFifo().

Referenced by XQspiPsu_TXRXSetup().

void XQspiPsu_WriteProtectToggle	(	const XQspiPsu *	InstancePtr,
		u32	Toggle
	)

This API enables/ disables Write Protect pin on the flash parts.

Parameters

InstancePtr	is a pointer to the QSPIPSU driver component to use.
Toggle	is a value of the GPIO pin

Returns: None

Note: By default WP pin as per the QSPI controller is driven High which means no write protection. Calling this function once will enable the protection.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Config::ConnectionMode, XQspiPsu::IsReady, XQSPIPSU_CONNECTION_MODE_SINGLE, XQSPIPSU_GPIO_OFFSET, and XQspiPsu_WriteReg.

Referenced by QspiPsuWriteProtectFlashExample().

Variable Documentation

XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]

Initial value:

= {
        {
                XPAR_XQSPIPSU_0_DEVICE_ID, 
                XPAR_XQSPIPSU_0_BASEADDR,  
                XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ,
                XPAR_XQSPIPSU_0_QSPI_MODE,
                XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH,
                XPAR_XQSPIPSU_0_IS_CACHE_COHERENT
        },
}

This table contains configuration information for each QSPIPSU device in the system.

Referenced by XQspiPsu_LookupConfig().

XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]

This table contains configuration information for each QSPIPSU device in the system.

Referenced by XQspiPsu_LookupConfig().

Data Structures

Macros

Typedefs

Functions

Variables

Device Base Address

XQSPIPS Enable Register information

XQSPIPSU configuration Register information

XQSPIPSU LQSPI Register information

XQSPIPSU Interrupt Status Register information

XQSPIPSU Interrupt Enable Register information

XQSPIPSU Interrupt Disable Register information

XQSPIPSU Interrupt Mask Register information

XQSPIPSU Enable Register information

XQSPIPSU TX Data Register information

XQSPIPSU RX Data Register information

XQSPIPSU TX/RX Threshold Register information

XQSPIPSU GPIO Register information

XQSPIPSU Loopback Master Clock Delay Adjustment Register information

XQSPIPSU GEN_FIFO Register information

XQSPIPSU Select Register information

XQSPIPSU FIFO Control Register information

XQSPIPSU GENFIFO Threshold Register information

XQSPIPSU Poll configuration Register information

XQSPIPSU Transfer Status Register information

XQSPIPSU GEN_FIFO Snapshot Register information

XQSPIPSU Receive Data Copy Register information

XQSPIPSU Module Identification Register information

XQSPIPSU DMA Transfer Register information

XQSPIPSU Generic FIFO masks information

XQSPIPSU RX Data Delay Register information

TAPDLY Bypass register information

Macro Definition Documentation

Typedef Documentation

Function Documentation

Variable Documentation