Data Structures
struct	XQspiPsu_Msg
	This typedef contains configuration information for a flash message. More...

struct	XQspiPsu_Config
	This typedef contains configuration information for the device. More...

struct	XQspiPsu
	The XQspiPsu driver instance data. More...

Macros
#define	MAX_DELAY_CNT 1000000000U
	Max delay count. More...

#define	XQSPIPSU_H_
	< prevent circular inclusions More...

#define	BYTES256_PER_PAGE 256U
	Definitions for Intel, STM, Winbond and Spansion Serial Flash Device geometry. More...

#define	BYTES512_PER_PAGE 512U
	512 Bytes per Page More...

#define	BYTES1024_PER_PAGE 1024U
	1024 Bytes per Page More...

#define	PAGES16_PER_SECTOR 16U
	16 Pages per Sector More...

#define	PAGES128_PER_SECTOR 128U
	128 Pages per Sector More...

#define	PAGES256_PER_SECTOR 256U
	256 Pages per Sector More...

#define	PAGES512_PER_SECTOR 512U
	512 Pages per Sector More...

#define	PAGES1024_PER_SECTOR 1024U
	1024 Pages per Sector More...

#define	NUM_OF_SECTORS2 2U
	2 Sectors More...

#define	NUM_OF_SECTORS4 4U
	4 Sectors More...

#define	NUM_OF_SECTORS8 8U
	8 Sector More...

#define	NUM_OF_SECTORS16 16U
	16 Sectors More...

#define	NUM_OF_SECTORS32 32U
	32 Sectors More...

#define	NUM_OF_SECTORS64 64U
	64 Sectors More...

#define	NUM_OF_SECTORS128 128U
	128 Sectors More...

#define	NUM_OF_SECTORS256 256U
	256 Sectors More...

#define	NUM_OF_SECTORS512 512U
	512 Sectors More...

#define	NUM_OF_SECTORS1024 1024U
	1024 Sectors More...

#define	NUM_OF_SECTORS2048 2048U
	2048 Sectors More...

#define	NUM_OF_SECTORS4096 4096U
	4096 Sectors More...

#define	NUM_OF_SECTORS8192 8192U
	8192 Sectors More...

#define	SECTOR_SIZE_64K 0X10000U
	64K Sector More...

#define	SECTOR_SIZE_128K 0X20000U
	128K Sector More...

#define	SECTOR_SIZE_256K 0X40000U
	256K Sector More...

#define	SECTOR_SIZE_512K 0X80000U
	512K Sector More...

#define	XQSPIPSU_READMODE_DMA 0x0U
	DMA read mode. More...

#define	XQSPIPSU_READMODE_IO 0x1U
	IO read mode. More...

#define	XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U
	Select lower flash. More...

#define	XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U
	Select upper flash. More...

#define	XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U
	Select both flash. More...

#define	XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U
	Select lower bus flash. More...

#define	XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U
	Select upper bus flash. More...

#define	XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U
	Select both bus flash. More...

#define	XQSPIPSU_SELECT_MODE_SPI 0x1U
	Select SPI mode. More...

#define	XQSPIPSU_SELECT_MODE_DUALSPI 0x2U
	Select dual SPI mode. More...

#define	XQSPIPSU_SELECT_MODE_QUADSPI 0x4U
	Select quad SPI mode. More...

#define	XQSPIPSU_GENFIFO_CS_SETUP 0x05U
	Chip select setup in GENFIO. More...

#define	XQSPIPSU_GENFIFO_CS_HOLD 0x04U
	Chip select hold in GENFIFO. More...

#define	XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U
	Clk Active low option. More...

#define	XQSPIPSU_CLK_PHASE_1_OPTION 0x4U
	Clk phase 1 option. More...

#define	XQSPIPSU_MANUAL_START_OPTION 0x8U
	Manual start option. More...

#define	XQSPIPSU_LQSPI_MODE_OPTION 0x20U
	LQSPI mode option. More...

#define	XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB 1U
	LQSPI less Than 16 MB. More...

#define	XQSPIPSU_GENFIFO_EXP_START 0x100U
	Genfifo start. More...

#define	XQSPIPSU_DMA_BYTES_MAX 0x10000000U
	DMA bytes max. More...

#define	XQSPIPSU_CLK_PRESCALE_2 0x00U
	Clock prescale 2. More...

#define	XQSPIPSU_CLK_PRESCALE_4 0x01U
	Clock prescale 4. More...

#define	XQSPIPSU_CLK_PRESCALE_8 0x02U
	Clock prescale 8. More...

#define	XQSPIPSU_CLK_PRESCALE_16 0x03U
	Clock prescale 16. More...

#define	XQSPIPSU_CLK_PRESCALE_32 0x04U
	Clock prescale 32. More...

#define	XQSPIPSU_CLK_PRESCALE_64 0x05U
	Clock prescale 64. More...

#define	XQSPIPSU_CLK_PRESCALE_128 0x06U
	Clock prescale 128. More...

#define	XQSPIPSU_CLK_PRESCALE_256 0x07U
	Clock prescale 256. More...

#define	XQSPIPSU_CR_PRESC_MAXIMUM 7U
	Prescale max. More...

#define	XQSPIPSU_CONNECTION_MODE_SINGLE 0U
	Single mode connection. More...

#define	XQSPIPSU_CONNECTION_MODE_STACKED 1U
	Stacked mode connection. More...

#define	XQSPIPSU_CONNECTION_MODE_PARALLEL 2U
	Parallel mode connection. More...

#define	XQSPIPSU_FREQ_37_5MHZ 37500000U
	Frequency 375 Mhz. More...

#define	XQSPIPSU_FREQ_40MHZ 40000000U
	Frequency 40 Mhz. More...

#define	XQSPIPSU_FREQ_100MHZ 100000000U
	Frequency 100 Mhz. More...

#define	XQSPIPSU_FREQ_150MHZ 150000000U
	Frequency 150 Mhz. More...

#define	XQSPIPSU_MSG_FLAG_STRIPE 0x1U
	Stripe Msg flag. More...

#define	XQSPIPSU_MSG_FLAG_RX 0x2U
	Rx Msg flag. More...

#define	XQSPIPSU_MSG_FLAG_TX 0x4U
	Tx Msg flag. More...

#define	XQSPIPSU_MSG_FLAG_POLL 0x8U
	POLL Msg flag. More...

#define	XQSPIPSU_RXADDR_OVER_32BIT 0x100000000U
	Rx address over 32 bit. More...

#define	XQSPIPSU_SET_WP 1
	GQSPI configuration to toggle WP of flash. More...

#define	XQspiPsu_Select(InstancePtr, Mask)
	select QSPI controller More...

#define	XQspiPsu_Enable(InstancePtr)
	Enable QSPI Controller. More...

#define	XQspiPsu_Disable(InstancePtr)
	Disable QSPI controller. More...

#define	XQspiPsu_GetLqspiConfigReg(InstancePtr)
	Read Configuration register of LQSPI Controller. More...

#define	XQSPIPSU_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
	Number of options in option table. More...

#define	MAX_DELAY_CNT 1000000000U
	Max delay count. More...

Typedefs
typedef void(*	XQspiPsu_StatusHandler )(const void *CallBackRef, u32 StatusEvent, u32 ByteCount)
	The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device. More...

Functions
s32	XQspiPsu_CfgInitialize (XQspiPsu InstancePtr, const XQspiPsu_Config ConfigPtr, UINTPTR EffectiveAddr)
	Initializes a specific XQspiPsu instance as such the driver is ready to use. More...

void	XQspiPsu_Idle (const XQspiPsu *InstancePtr)
	Stops the transfer of data to internal DST FIFO from stream interface and also stops the issuing of new write commands to memory. More...

void	XQspiPsu_Reset (XQspiPsu *InstancePtr)
	Resets the QSPIPSU device. More...

void	XQspiPsu_Abort (XQspiPsu *InstancePtr)
	Aborts a transfer in progress. More...

void	XQspiPsu_PollDataHandler (XQspiPsu *InstancePtr, u32 StatusReg)
	This is the handler for polling functionality of controller. More...

s32	XQspiPsu_PolledTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)
	Performs a transfer on the bus in polled mode. More...

s32	XQspiPsu_InterruptTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)
	Initiates a transfer on the bus and enables interrupts. More...

s32	XQspiPsu_InterruptHandler (XQspiPsu *InstancePtr)
	Handles interrupt based transfers by acting on GENFIFO and DMA interurpts. More...

void	XQspiPsu_SetStatusHandler (XQspiPsu InstancePtr, void CallBackRef, XQspiPsu_StatusHandler FuncPointer)
	Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. More...

void	XQspiPsu_WriteProtectToggle (const XQspiPsu *InstancePtr, u32 Toggle)
	Enables/disables Write Protect pin on the flash parts. More...

s32	XQspiPsu_StartDmaTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)
	Starts a DMA transfer. More...

s32	XQspiPsu_CheckDmaDone (XQspiPsu *InstancePtr)
	Checks for DMA transfer complete. More...

XQspiPsu_Config *	XQspiPsu_LookupConfig (u16 DeviceId)
	Looks up the device configuration based on the unique device ID. More...

s32	XQspiPsu_SetClkPrescaler (const XQspiPsu *InstancePtr, u8 Prescaler)
	Configures the clock according to the prescaler passed. More...

void	XQspiPsu_SelectFlash (XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
	Used to tell the QSPIPSU driver the hardware flash configuration being used. More...

s32	XQspiPsu_SetOptions (XQspiPsu *InstancePtr, u32 Options)
	Sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. More...

s32	XQspiPsu_ClearOptions (XQspiPsu *InstancePtr, u32 Options)
	Resets the options for the QSPIPSU device driver. More...

u32	XQspiPsu_GetOptions (const XQspiPsu *InstancePtr)
	Gets the options for the QSPIPSU device. More...

s32	XQspiPsu_SetReadMode (XQspiPsu *InstancePtr, u32 Mode)
	Sets the Read mode for the QSPIPSU device driver. More...

void	XQspiPsu_SetWP (const XQspiPsu *InstancePtr, u8 Value)
	Sets the Write Protect and Hold options for the QSPIPSU device driver. More...

void	XQspiPsu_GenFifoEntryData (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	Writes the GENFIFO entries to transmit the messages requested. More...

void	XQspiPsu_PollDataConfig (XQspiPsu InstancePtr, XQspiPsu_Msg FlashMsg)
	Enables the polling functionality of controller. More...

s32	XQspiPsu_PolledMessageTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)
	Performs a transfer on the bus in polled mode. More...

void	XQspiPsu_IntrDataTransfer (XQspiPsu InstancePtr, u32 QspiPsuStatusReg, u8 *DeltaMsgCnt)
	Transfers Tx and Rx data. More...

void	XQspiPsu_IntrDummyDataTransfer (XQspiPsu *InstancePtr, u32 QspiPsuStatusReg, u8 DeltaMsgCnt)
	Transfers Dummy byte. More...

void	XQspiPsu_FillTxFifo (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 Size)
	Fills the TX FIFO as long as there is room in the FIFO or the bytes required to be transmitted. More...

void	XQspiPsu_TXSetup (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	Checks the TX buffer in the message and setup the TX FIFO as required. More...

void	XQspiPsu_SetupRxDma (const XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	Sets up the RX DMA operation. More...

void	XQspiPsu_Setup64BRxDma (const XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	Sets up the RX DMA operation on a 32-bit Machine For 64-bit DMA transfers. More...

u32	XQspiPsu_SetIOMode (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	Reads remaining bytes after the completion of a DMA transfer using I/O mode. More...

void	XQspiPsu_RXSetup (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)
	Checks the RX buffers in the message and setup the RX DMA as required. More...

void	XQspiPsu_TXRXSetup (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 *GenFifoEntry)
	Checks the TX/RX buffers in the message and setups up the GENFIFO entries, TX FIFO, or RX DMA as required. More...

void	XQspiPsu_GenFifoEntryDataLen (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 *GenFifoEntry)
	Writes the data length to GENFIFO entries to be transmitted or received. More...

u32	XQspiPsu_CreatePollDataConfig (const XQspiPsu InstancePtr, const XQspiPsu_Msg FlashMsg)
	Creates Poll configuration register data to write. More...

u32	XQspiPsu_SelectSpiMode (u8 SpiMode)
	Selects SPI mode - x1 or x2 or x4. More...

void	XQspiPsu_SetDefaultConfig (XQspiPsu *InstancePtr)
	Enables and initializes DMA Mode, set little endain, disable poll timeout, clears prescalar bits and reset thresholds. More...

void	XQspiPsu_ReadRxFifo (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, s32 Size)
	Reads the specified number of bytes from RX FIFO. More...

void	XQspiPsu_IORead (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 StatusReg)
	Reads data from RXFifo in I/O mode. More...

s32	XQspiPsu_PolledSendData (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, s32 Index)
	Transfers Tx data on the bus in polled mode. More...

s32	XQspiPsu_PolledRecvData (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, s32 Index, u32 *IOPending)
	Transfers Rx data on the bus in polled mode. More...

void	XQspiPsu_IntrSendData (XQspiPsu InstancePtr, u32 QspiPsuStatusReg, u8 DeltaMsgCnt)
	Performs a transfer of Tx data on the bus in interrupt mode. More...

void	XQspiPsu_IntrRecvData (XQspiPsu InstancePtr, u32 QspiPsuStatusReg, u32 DmaIntrStatusReg, u8 DeltaMsgCnt)
	Performs a transfer of Rx data on the busin interrupt mode. More...

Variables
XQspiPsu_Config	XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES]
	This table contains configuration information for each QSPIPSU device in the system. More...

XQspiPsu_Config	XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES]
	This table contains configuration information for each QSPIPSU device in the system. More...

Macro Definition Documentation

#define BYTES1024_PER_PAGE 1024U

1024 Bytes per Page

#define BYTES256_PER_PAGE 256U

Definitions for Intel, STM, Winbond and Spansion Serial Flash Device geometry.

256 Bytes per Page

#define BYTES512_PER_PAGE 512U

512 Bytes per Page

#define MAX_DELAY_CNT 1000000000U

Max delay count.

Referenced by XQspiPsu_PolledRecvData(), and XQspiPsu_PolledSendData().

#define MAX_DELAY_CNT 1000000000U

Max delay count.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashReadID(), FlashRegisterWrite(), FlashWrite(), MultiDieRead(), XQspiPsu_Abort(), XQspiPsu_CheckDmaDone(), XQspiPsu_PolledTransfer(), and XQspiPsu_StartDmaTransfer().

#define NUM_OF_SECTORS1024 1024U

1024 Sectors

#define NUM_OF_SECTORS128 128U

128 Sectors

#define NUM_OF_SECTORS16 16U

16 Sectors

#define NUM_OF_SECTORS2 2U

2 Sectors

#define NUM_OF_SECTORS2048 2048U

2048 Sectors

#define NUM_OF_SECTORS256 256U

256 Sectors

#define NUM_OF_SECTORS32 32U

32 Sectors

#define NUM_OF_SECTORS4 4U

4 Sectors

#define NUM_OF_SECTORS4096 4096U

4096 Sectors

#define NUM_OF_SECTORS512 512U

512 Sectors

#define NUM_OF_SECTORS64 64U

64 Sectors

#define NUM_OF_SECTORS8 8U

8 Sector

#define NUM_OF_SECTORS8192 8192U

8192 Sectors

#define PAGES1024_PER_SECTOR 1024U

1024 Pages per Sector

#define PAGES128_PER_SECTOR 128U

128 Pages per Sector

#define PAGES16_PER_SECTOR 16U

16 Pages per Sector

#define PAGES256_PER_SECTOR 256U

256 Pages per Sector

#define PAGES512_PER_SECTOR 512U

512 Pages per Sector

#define SECTOR_SIZE_128K 0X20000U

128K Sector

#define SECTOR_SIZE_256K 0X40000U

256K Sector

#define SECTOR_SIZE_512K 0X80000U

512K Sector

#define SECTOR_SIZE_64K 0X10000U

64K Sector

#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U

Clk Active low option.

#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4U

Clk phase 1 option.

#define XQSPIPSU_CLK_PRESCALE_128 0x06U

Clock prescale 128.

#define XQSPIPSU_CLK_PRESCALE_16 0x03U

Clock prescale 16.

#define XQSPIPSU_CLK_PRESCALE_2 0x00U

Clock prescale 2.

#define XQSPIPSU_CLK_PRESCALE_256 0x07U

Clock prescale 256.

#define XQSPIPSU_CLK_PRESCALE_32 0x04U

Clock prescale 32.

#define XQSPIPSU_CLK_PRESCALE_4 0x01U

Clock prescale 4.

#define XQSPIPSU_CLK_PRESCALE_64 0x05U

Clock prescale 64.

#define XQSPIPSU_CLK_PRESCALE_8 0x02U

Clock prescale 8.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2U

Parallel mode connection.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashWrite(), GetRealAddr(), MultiDieRead(), QspiPsuConfigurePoll(), QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

#define XQSPIPSU_CONNECTION_MODE_SINGLE 0U

Single mode connection.

Referenced by GetRealAddr(), MultiDieRead(), and XQspiPsu_WriteProtectToggle().

#define XQSPIPSU_CONNECTION_MODE_STACKED 1U

Stacked mode connection.

Referenced by DieErase(), FlashErase(), and GetRealAddr().

#define XQSPIPSU_CR_PRESC_MAXIMUM 7U

Prescale max.

Referenced by XQspiPsu_SetClkPrescaler().

#define XQspiPsu_Disable ( InstancePtr )

Value:

XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPSU_EN_OFFSET, 0x0U)

XQSPIPSU_EN_OFFSET

#define XQSPIPSU_EN_OFFSET

Register: XQSPIPSU_EN_REG.

Definition: xqspipsu_hw.h:380

XQspiPsu_Out32

#define XQspiPsu_Out32

Write the 32 bit register value.

Definition: xqspipsu_hw.h:965

Disable QSPI controller.

#define XQSPIPSU_DMA_BYTES_MAX 0x10000000U

DMA bytes max.

Referenced by XQspiPsu_InterruptTransfer(), XQspiPsu_PolledTransfer(), and XQspiPsu_StartDmaTransfer().

#define XQspiPsu_Enable ( InstancePtr )

Value:

XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)

XQSPIPSU_EN_OFFSET

#define XQSPIPSU_EN_OFFSET

Register: XQSPIPSU_EN_REG.

Definition: xqspipsu_hw.h:380

XQspiPsu_Out32

#define XQspiPsu_Out32

Write the 32 bit register value.

Definition: xqspipsu_hw.h:965

Enable QSPI Controller.

Referenced by XQspiPsu_CfgInitialize().

#define XQSPIPSU_FREQ_100MHZ 100000000U

Frequency 100 Mhz.

#define XQSPIPSU_FREQ_150MHZ 150000000U

Frequency 150 Mhz.

#define XQSPIPSU_FREQ_37_5MHZ 37500000U

Frequency 375 Mhz.

Referenced by XQspiPsu_SetClkPrescaler().

#define XQSPIPSU_FREQ_40MHZ 40000000U

Frequency 40 Mhz.

#define XQSPIPSU_GENFIFO_CS_HOLD 0x04U

Chip select hold in GENFIFO.

#define XQSPIPSU_GENFIFO_CS_SETUP 0x05U

Chip select setup in GENFIO.

#define XQSPIPSU_GENFIFO_EXP_START 0x100U

Genfifo start.

Referenced by XQspiPsu_GenFifoEntryDataLen().

#define XQspiPsu_GetLqspiConfigReg ( InstancePtr )

Value:

XQspiPsu_In32((XQSPIPS_BASEADDR) + \

XQSPIPSU_LQSPI_CR_OFFSET)

XQSPIPSU_LQSPI_CR_OFFSET

#define XQSPIPSU_LQSPI_CR_OFFSET

Register: XQSPIPSU_LQSPI.

Definition: xqspipsu_hw.h:146

XQspiPsu_In32

#define XQspiPsu_In32

Read the 32 bit register value.

Definition: xqspipsu_hw.h:964

XQSPIPS_BASEADDR

#define XQSPIPS_BASEADDR

QSPI Base Address.

Definition: xqspipsu_hw.h:64

Read Configuration register of LQSPI Controller.

Referenced by XQspiPsu_LqspiRead().

#define XQSPIPSU_H_

< prevent circular inclusions

by using protection macros

#define XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB 1U

LQSPI less Than 16 MB.

Referenced by XQspiPsu_SetOptions().

#define XQSPIPSU_LQSPI_MODE_OPTION 0x20U

LQSPI mode option.

Referenced by XQspiPsu_SetOptions().

#define XQSPIPSU_MANUAL_START_OPTION 0x8U

Manual start option.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), QspiPsuWriteProtectFlashExample(), XQspiPsu_ClearOptions(), and XQspiPsu_SetOptions().

#define XQSPIPSU_MSG_FLAG_POLL 0x8U

POLL Msg flag.

Referenced by QspiPsuConfigurePoll(), XQspiPsu_InterruptHandler(), and XQspiPsu_InterruptTransfer().

#define XQSPIPSU_MSG_FLAG_RX 0x2U

#define XQSPIPSU_MSG_FLAG_STRIPE 0x1U

Stripe Msg flag.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashWrite(), MultiDieRead(), QspiPsuConfigurePoll(), XQspiPsu_GenFifoEntryData(), and XQspiPsu_PollDataConfig().

#define XQSPIPSU_MSG_FLAG_TX 0x4U

Tx Msg flag.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashReadID(), FlashRegisterRead(), FlashRegisterWrite(), FlashWrite(), MultiDieRead(), XQspiPsu_InterruptHandler(), XQspiPsu_IntrDataTransfer(), XQspiPsu_PolledMessageTransfer(), and XQspiPsu_TXRXSetup().

#define XQSPIPSU_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))

Number of options in option table.

Referenced by XQspiPsu_ClearOptions(), XQspiPsu_GetOptions(), and XQspiPsu_SetOptions().

#define XQSPIPSU_READMODE_DMA 0x0U

DMA read mode.

Referenced by XQspiPsu_Abort(), XQspiPsu_CfgInitialize(), XQspiPsu_GenFifoEntryData(), XQspiPsu_InterruptTransfer(), XQspiPsu_IntrDataTransfer(), XQspiPsu_IntrDummyDataTransfer(), XQspiPsu_IntrRecvData(), XQspiPsu_PollDataHandler(), XQspiPsu_PolledMessageTransfer(), XQspiPsu_PolledRecvData(), XQspiPsu_RXSetup(), XQspiPsu_SetReadMode(), and XQspiPsu_StartDmaTransfer().

#define XQSPIPSU_READMODE_IO 0x1U

IO read mode.

Referenced by XQspiPsu_GenFifoEntryData(), XQspiPsu_SetIOMode(), XQspiPsu_SetReadMode(), and XQspiPsu_StartDmaTransfer().

#define XQSPIPSU_RXADDR_OVER_32BIT 0x100000000U

Rx address over 32 bit.

Referenced by XQspiPsu_CheckDmaDone(), XQspiPsu_IntrRecvData(), XQspiPsu_PolledRecvData(), and XQspiPsu_RXSetup().

#define XQspiPsu_Select	(	InstancePtr,
		Mask
	)

Value:

XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPSU_SEL_OFFSET, (Mask))

XQSPIPSU_SEL_OFFSET

#define XQSPIPSU_SEL_OFFSET

Register: XQSPIPSU_SEL.

Definition: xqspipsu_hw.h:504

XQspiPsu_Out32

#define XQspiPsu_Out32

Write the 32 bit register value.

Definition: xqspipsu_hw.h:965

select QSPI controller

Referenced by XQspiPsu_CfgInitialize().

#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U

Select both bus flash.

Referenced by GetRealAddr(), QspiPsuConfigurePoll(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U

Select lower bus flash.

Referenced by FlashErase(), GetRealAddr(), QspiPsuConfigurePoll(), QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), QspiPsuWriteProtectFlashExample(), XQspiPsu_CreatePollDataConfig(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U

Select upper bus flash.

Referenced by XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U

Select both flash.

Referenced by GetRealAddr(), QspiPsuConfigurePoll(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U

Select lower flash.

Referenced by FlashErase(), GetRealAddr(), QspiPsuConfigurePoll(), QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), QspiPsuWriteProtectFlashExample(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U

Select upper flash.

Referenced by FlashErase(), GetRealAddr(), and XQspiPsu_SelectFlash().

#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2U

Select dual SPI mode.

Referenced by FlashRead(), MultiDieRead(), and XQspiPsu_SelectSpiMode().

#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4U

Select quad SPI mode.

Referenced by FlashRead(), MultiDieRead(), and XQspiPsu_SelectSpiMode().

#define XQSPIPSU_SELECT_MODE_SPI 0x1U

Select SPI mode.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashReadID(), FlashRegisterRead(), FlashRegisterWrite(), FlashWrite(), MultiDieRead(), QspiPsuConfigurePoll(), and XQspiPsu_SelectSpiMode().

#define XQSPIPSU_SET_WP 1

GQSPI configuration to toggle WP of flash.

Referenced by QspiPsuWriteProtectFlashExample().

Typedef Documentation

typedef void(* XQspiPsu_StatusHandler)(const void *CallBackRef, u32 StatusEvent, u32 ByteCount)

The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device.

The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler executes in an interrupt context, so only minimal processing should be performed.

Parameters

CallBackRef	Callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer.
StatusEvent	Holds one or more status events that have occurred. See XQspiPsu_SetStatusHandler() for details on the status events that can be passed in the callback.
ByteCount	Indicates how many bytes of data were successfully transferred. This may be less than the number of bytes requested if the status event indicates an error.

Function Documentation

void XQspiPsu_Abort ( XQspiPsu * InstancePtr )

Aborts a transfer in progress.

Parameters

InstancePtr Pointer to the XQspiPsu instance.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::GenFifoEntries, XQspiPsu::IsBusy, MAX_DELAY_CNT, XQspiPsu::ReadMode, XQspiPsu::RxBytes, XQspiPsu::TxBytes, XQSPIPSU_CFG_OFFSET, XQSPIPSU_FIFO_CTRL_OFFSET, XQSPIPSU_IDR_OFFSET, XQSPIPSU_ISR_OFFSET, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_Reset().

s32 XQspiPsu_CfgInitialize	(	XQspiPsu *	InstancePtr,
		const XQspiPsu_Config *	ConfigPtr,
		UINTPTR	EffectiveAddr
	)

Initializes a specific XQspiPsu instance as such the driver is ready to use.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
ConfigPtr	Reference to a structure containing information about a specific QSPIPSU device. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
EffectiveAddr	Device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->Config. BaseAddress for this device.

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Config::BaudRateDiv, XQspiPsu_Config::BusWidth, XQspiPsu::Config, XQspiPsu_Config::ConnectionMode, XQspiPsu::GenFifoBufferPtr, XQspiPsu::GenFifoBus, XQspiPsu::GenFifoCS, XQspiPsu::GenFifoEntries, XQspiPsu_Config::InputClockHz, XQspiPsu::IsBusy, XQspiPsu_Config::IsCacheCoherent, XQspiPsu_Config::IsFbClock, XQspiPsu::IsManualstart, XQspiPsu::IsReady, XQspiPsu::IsUnaligned, XQspiPsu::ReadMode, XQspiPsu::RecvBufferPtr, XQspiPsu::RxBytes, XQspiPsu::SendBufferPtr, XQspiPsu::StatusHandler, XQspiPsu::TxBytes, XQspiPsu_Enable, XQSPIPSU_READMODE_DMA, XQspiPsu_Reset(), and XQspiPsu_Select.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

s32 XQspiPsu_CheckDmaDone ( XQspiPsu * InstancePtr )

Checks for DMA transfer complete.

Parameters

InstancePtr Pointer to the XQspiPsu instance.

Returns

XST_SUCCESS if DMA transfer complete.
XST_FAILURE if DMA transfer is not completed.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu_Config::IsCacheCoherent, XQspiPsu::IsManualstart, XQspiPsu::IsReady, MAX_DELAY_CNT, XQspiPsu::Msg, XQspiPsu_Msg::RxAddr64bit, XQspiPsu_Msg::RxBfrPtr, XQspiPsu::RxBytes, XQspiPsu_Msg::Xfer64bit, XQSPIPSU_CFG_OFFSET, XQSPIPSU_ISR_OFFSET, XQspiPsu_ReadReg, XQSPIPSU_RXADDR_OVER_32BIT, and XQspiPsu_WriteReg.

s32 XQspiPsu_ClearOptions	(	XQspiPsu *	InstancePtr,
		u32	Options
	)

Resets the options for the QSPIPSU device driver.

The options control how the device behaves relative to the QSPIPSU bus. The device must be idle rather than busy transferring data before setting these device options.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Options	Contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned OFF and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

Note: This function is not thread-safe.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsManualstart, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_NUM_OPTIONS, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

u32 XQspiPsu_CreatePollDataConfig	(	const XQspiPsu *	InstancePtr,
		const XQspiPsu_Msg *	FlashMsg
	)

Creates Poll configuration register data to write.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
FlashMsg	Pointer to the structure containing transfer data.

Returns: None

References XQspiPsu::GenFifoBus, XQspiPsu::IsReady, XQspiPsu_Msg::PollBusMask, XQspiPsu_Msg::PollData, and XQSPIPSU_SELECT_FLASH_BUS_LOWER.

Referenced by XQspiPsu_PollDataConfig().

void XQspiPsu_FillTxFifo	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	Size
	)

Fills the TX FIFO as long as there is room in the FIFO or the bytes required to be transmitted.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
Size	Number of bytes to be transmitted.

Returns: None

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu_Msg::TxBfrPtr, XQspiPsu::TxBytes, XQSPIPSU_TXD_OFFSET, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_IntrSendData(), XQspiPsu_PolledSendData(), and XQspiPsu_TXSetup().

void XQspiPsu_GenFifoEntryData	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

Writes the GENFIFO entries to transmit the messages requested.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::BusWidth, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::GenFifoBus, XQspiPsu::GenFifoCS, XQspiPsu::IsReady, XQspiPsu::IsUnaligned, XQspiPsu::ReadMode, XQSPIPSU_CFG_OFFSET, XQSPIPSU_GEN_FIFO_OFFSET, XQspiPsu_GenFifoEntryDataLen(), XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_STRIPE, XQSPIPSU_READMODE_DMA, XQSPIPSU_READMODE_IO, XQspiPsu_ReadReg, XQspiPsu_SelectSpiMode(), XQspiPsu_TXRXSetup(), and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptTransfer(), XQspiPsu_IntrDummyDataTransfer(), XQspiPsu_IntrRecvData(), XQspiPsu_PolledMessageTransfer(), and XQspiPsu_StartDmaTransfer().

void XQspiPsu_GenFifoEntryDataLen	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32 *	GenFifoEntry
	)

Writes the data length to GENFIFO entries to be transmitted or received.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
GenFifoEntry	Pointer to the variable in which GENFIFO mask is returned to the calling function.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu::IsReady, XQSPIPSU_GEN_FIFO_OFFSET, XQSPIPSU_GENFIFO_EXP_START, XQSPIPSU_GENFIFO_IMM_DATA_MASK, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_GenFifoEntryData().

u32 XQspiPsu_GetOptions ( const XQspiPsu * InstancePtr )

Gets the options for the QSPIPSU device.

The options control how the device behaves relative to the QSPIPSU bus.

Parameters

InstancePtr Pointer to the XQspiPsu instance.

Returns

Options contains the specified options currently set. This is a bit value where a 1 means the option is on, and a 0 means the option is off. See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, XQSPIPSU_NUM_OPTIONS, and XQspiPsu_ReadReg.

void XQspiPsu_Idle ( const XQspiPsu * InstancePtr )

Stops the transfer of data to internal DST FIFO from stream interface and also stops the issuing of new write commands to memory.

By calling this API, any ongoing Dma transfers will be paused and DMA will not issue AXI write commands to memory

Parameters

InstancePtr Pointer to the XQspiPsu instance.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQSPIPSU_EN_OFFSET, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

s32 XQspiPsu_InterruptHandler ( XQspiPsu * InstancePtr )

Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.

Parameters

InstancePtr Pointer to the XQspiPsu instance.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.

Note: None.

References XQspiPsu_Msg::Flags, XQspiPsu::IsReady, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu_IntrDataTransfer(), XQspiPsu_IntrDummyDataTransfer(), XQSPIPSU_MSG_FLAG_POLL, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_TX, and XQspiPsu_PollDataHandler().

Referenced by QspiPsuInterruptFlashExample(), and QspiPsuWriteProtectFlashExample().

s32 XQspiPsu_InterruptTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

Initiates a transfer on the bus and enables interrupts.

The transfer is completed by the interrupt handler. The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
NumMsg	Number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu::ReadMode, XQSPIPSU_DMA_BYTES_MAX, XQspiPsu_GenFifoEntryData(), XQSPIPSU_IER_OFFSET, XQSPIPSU_MSG_FLAG_POLL, XQSPIPSU_MSG_FLAG_RX, XQspiPsu_PollDataConfig(), XQSPIPSU_READMODE_DMA, and XQspiPsu_WriteReg.

Referenced by BulkErase(), DieErase(), FlashEnableQuadMode(), FlashEnterExit4BAddMode(), FlashErase(), FlashRead(), FlashReadID(), FlashWrite(), and MultiDieRead().

void XQspiPsu_IntrDataTransfer	(	XQspiPsu *	InstancePtr,
		u32 *	QspiPsuStatusReg,
		u8 *	DeltaMsgCnt
	)

Transfers Tx and Rx data.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
QspiPsuStatusReg	Status of QSPI status register.
DeltaMsgCnt	Message count flag.

Returns: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu::ReadMode, XQspiPsu::StatusHandler, XQspiPsu::StatusRef, XQspiPsu_IntrRecvData(), XQspiPsu_IntrSendData(), XQSPIPSU_ISR_OFFSET, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_TX, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptHandler().

void XQspiPsu_IntrDummyDataTransfer	(	XQspiPsu *	InstancePtr,
		u32	QspiPsuStatusReg,
		u8	DeltaMsgCnt
	)

Transfers Dummy byte.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
QspiPsuStatusReg	Status of QSPI status register.
DeltaMsgCnt	Message count flag.

Returns: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsUnaligned, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu::ReadMode, XQspiPsu::StatusHandler, XQspiPsu::StatusRef, XQSPIPSU_CFG_OFFSET, XQspiPsu_GenFifoEntryData(), XQSPIPSU_IDR_OFFSET, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptHandler().

void XQspiPsu_IntrRecvData	(	XQspiPsu *	InstancePtr,
		u32	QspiPsuStatusReg,
		u32	DmaIntrStatusReg,
		u8 *	DeltaMsgCnt
	)

Performs a transfer of Rx data on the busin interrupt mode.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
QspiPsuStatusReg	Status QSPI status register.
DmaIntrStatusReg	Status DMA interrupt register.
DeltaMsgCnt	Message count flag.

Returns: None.

References XQspiPsu::Config, XQspiPsu_Config::IsCacheCoherent, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::ReadMode, XQspiPsu::RxBytes, XQspiPsu_GenFifoEntryData(), XQspiPsu_IORead(), XQSPIPSU_READMODE_DMA, XQSPIPSU_RXADDR_OVER_32BIT, and XQspiPsu_SetIOMode().

Referenced by XQspiPsu_IntrDataTransfer().

void XQspiPsu_IntrSendData	(	XQspiPsu *	InstancePtr,
		u32	QspiPsuStatusReg,
		u8 *	DeltaMsgCnt
	)

Performs a transfer of Tx data on the bus in interrupt mode.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
QspiPsuStatusReg	Status QSPI status register.
DeltaMsgCnt	Message count flag.

Returns: None.

References XQspiPsu_Msg::Flags, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::TxBytes, XQspiPsu_FillTxFifo(), and XQSPIPSU_MSG_FLAG_RX.

Referenced by XQspiPsu_IntrDataTransfer().

void XQspiPsu_IORead	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	StatusReg
	)

Reads data from RXFifo in I/O mode.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
StatusReg	Interrupt status Register value.

Returns: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu::RxBytes, XQspiPsu_ReadReg, and XQspiPsu_ReadRxFifo().

Referenced by XQspiPsu_IntrRecvData(), and XQspiPsu_PolledRecvData().

XQspiPsu_Config * XQspiPsu_LookupConfig ( u16 DeviceId )

Looks up the device configuration based on the unique device ID.

A table contains the configuration info for each device in the system.

Parameters

DeviceId Contains the ID of the device to look up the configuration for.

Returns: A pointer to the configuration found or NULL if the specified device ID was not found. See xqspipsu.h for the definition of XQspiPsu_Config.

Note: None.

References XQspiPsu_ConfigTable.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

void XQspiPsu_PollDataConfig	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	FlashMsg
	)

Enables the polling functionality of controller.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
FlashMsg	Pointer to the structure containing transfer data.

Returns: None

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::GenFifoBus, XQspiPsu::GenFifoCS, XQspiPsu::IsReady, XQspiPsu::Msg, XQspiPsu::MsgCnt, XQspiPsu::NumMsg, XQspiPsu_Msg::PollStatusCmd, XQspiPsu_Msg::PollTimeout, XQSPIPSU_CFG_OFFSET, XQspiPsu_CreatePollDataConfig(), XQSPIPSU_GEN_FIFO_OFFSET, XQSPIPSU_IER_OFFSET, XQSPIPSU_MSG_FLAG_STRIPE, XQSPIPSU_POLL_CFG_OFFSET, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptTransfer().

void XQspiPsu_PollDataHandler	(	XQspiPsu *	InstancePtr,
		u32	StatusReg
	)

This is the handler for polling functionality of controller.

It reads data from RXFIFO, since when data from the flash device (status data) matched with configured value in poll_cfg, then controller writes the matched data into RXFIFO.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
StatusReg	Interrupt status Register value.

Returns: None.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQspiPsu::ReadMode, XQspiPsu::StatusHandler, XQspiPsu::StatusRef, XQSPIPSU_IDR_OFFSET, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, XQSPIPSU_RXD_OFFSET, XQspiPsu_SetReadMode(), and XQspiPsu_WriteReg.

Referenced by XQspiPsu_InterruptHandler().

s32 XQspiPsu_PolledMessageTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

Performs a transfer on the bus in polled mode.

The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
NumMsg	Number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsUnaligned, XQspiPsu::ReadMode, XQspiPsu::RxBytes, XQspiPsu::TxBytes, XQSPIPSU_CFG_OFFSET, XQspiPsu_GenFifoEntryData(), XQSPIPSU_ISR_OFFSET, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_TX, XQspiPsu_PolledRecvData(), XQspiPsu_PolledSendData(), XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_PolledTransfer().

s32 XQspiPsu_PolledRecvData	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		s32	Index,
		u32 *	IOPending
	)

Transfers Rx data on the bus in polled mode.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
Index	Msg index to transfer.
IOPending	I/O mode transfer status.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Config::IsCacheCoherent, MAX_DELAY_CNT, XQspiPsu::ReadMode, XQspiPsu::RxBytes, XQspiPsu_IORead(), XQSPIPSU_ISR_OFFSET, XQSPIPSU_READMODE_DMA, XQspiPsu_ReadReg, XQSPIPSU_RXADDR_OVER_32BIT, XQspiPsu_SetIOMode(), and XQspiPsu_WriteReg.

Referenced by XQspiPsu_PolledMessageTransfer().

s32 XQspiPsu_PolledSendData	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		s32	Index
	)

Transfers Tx data on the bus in polled mode.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
Index	Msg index to transfer.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, MAX_DELAY_CNT, XQspiPsu::TxBytes, XQspiPsu_FillTxFifo(), and XQSPIPSU_ISR_OFFSET.

Referenced by XQspiPsu_PolledMessageTransfer().

s32 XQspiPsu_PolledTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

Performs a transfer on the bus in polled mode.

The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
NumMsg	Number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::IsBusy, XQspiPsu::IsReady, MAX_DELAY_CNT, XQSPIPSU_DMA_BYTES_MAX, XQSPIPSU_ISR_OFFSET, XQSPIPSU_MSG_FLAG_RX, and XQspiPsu_PolledMessageTransfer().

Referenced by FlashRegisterRead(), and FlashRegisterWrite().

void XQspiPsu_ReadRxFifo	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		s32	Size
	)

Reads the specified number of bytes from RX FIFO.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
Size	Number of bytes to be read.

Returns: None

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu_Msg::RxBfrPtr, XQspiPsu::RxBytes, XQspiPsu_ReadReg, and XQSPIPSU_RXD_OFFSET.

Referenced by XQspiPsu_IORead().

void XQspiPsu_Reset ( XQspiPsu * InstancePtr )

Resets the QSPIPSU device.

Reset must only be called after the driver has been initialized. Any data transfer that is in progress is aborted.

The upper layer software is responsible for re-configuring (if necessary) and restarting the QSPIPSU device after the reset.

Parameters

InstancePtr Pointer to the XQspiPsu instance.

Returns: None.

Note: None.

References XQspiPsu_Abort(), and XQspiPsu_SetDefaultConfig().

Referenced by XQspiPsu_CfgInitialize().

void XQspiPsu_RXSetup	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

Checks the RX buffers in the message and setup the RX DMA as required.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.

Returns: None

References XQspiPsu_Msg::ByteCount, XQspiPsu::IsReady, XQspiPsu::ReadMode, XQspiPsu_Msg::RxAddr64bit, XQspiPsu::RxBytes, XQspiPsu_Msg::Xfer64bit, XQSPIPSU_READMODE_DMA, XQSPIPSU_RXADDR_OVER_32BIT, XQspiPsu_Setup64BRxDma(), and XQspiPsu_SetupRxDma().

Referenced by XQspiPsu_TXRXSetup().

void XQspiPsu_SelectFlash	(	XQspiPsu *	InstancePtr,
		u8	FlashCS,
		u8	FlashBus
	)

Used to tell the QSPIPSU driver the hardware flash configuration being used.

This API should be called at least once in the application. If desired, it can be called multiple times when switching between communicating to different flahs devices/using different configs.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
FlashCS	Flash Chip Select.
FlashBus	Flash Bus (Upper, Lower or Both).

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

Note: If this function is not called at least once in the application, the driver assumes there is a single flash connected to the lower bus and CS line.

References XQspiPsu::GenFifoBus, XQspiPsu::GenFifoCS, XQspiPsu::IsReady, XQSPIPSU_SELECT_FLASH_BUS_BOTH, XQSPIPSU_SELECT_FLASH_BUS_LOWER, XQSPIPSU_SELECT_FLASH_BUS_UPPER, XQSPIPSU_SELECT_FLASH_CS_BOTH, XQSPIPSU_SELECT_FLASH_CS_LOWER, and XQSPIPSU_SELECT_FLASH_CS_UPPER.

Referenced by FlashErase(), GetRealAddr(), QspiPsuConfigurePoll(), QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

u32 XQspiPsu_SelectSpiMode ( u8 SpiMode )

Selects SPI mode - x1 or x2 or x4.

Parameters

SpiMode spi or dual or quad.

Returns: Mask to set desired SPI mode in GENFIFO entry.

References XQSPIPSU_SELECT_MODE_DUALSPI, XQSPIPSU_SELECT_MODE_QUADSPI, and XQSPIPSU_SELECT_MODE_SPI.

Referenced by XQspiPsu_GenFifoEntryData().

s32 XQspiPsu_SetClkPrescaler	(	const XQspiPsu *	InstancePtr,
		u8	Prescaler
	)

Configures the clock according to the prescaler passed.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Prescaler	Clock prescaler to be set.

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started.
XST_DEVICE_BUSY if the device is currently transferring data. It must be stopped to re-initialize.
XST_FAILURE if Prescaler value is less than FreqDiv when feedback clock is not enabled.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Config::InputClockHz, XQspiPsu::IsBusy, XQspiPsu_Config::IsFbClock, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, XQSPIPSU_CR_PRESC_MAXIMUM, XQSPIPSU_FREQ_37_5MHZ, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

void XQspiPsu_SetDefaultConfig ( XQspiPsu * InstancePtr )

Enables and initializes DMA Mode, set little endain, disable poll timeout, clears prescalar bits and reset thresholds.

Parameters

InstancePtr Pointer to the XQspiPsu instance.

Returns: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQSPIPSU_CFG_OFFSET, XQSPIPSU_GF_THRESHOLD_OFFSET, XQSPIPSU_LPBK_DLY_ADJ_OFFSET, XQspiPsu_ReadReg, XQSPIPSU_TX_THRESHOLD_OFFSET, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_Reset().

u32 XQspiPsu_SetIOMode	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

Reads remaining bytes after the completion of a DMA transfer using I/O mode.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu::IsUnaligned, XQspiPsu::ReadMode, XQspiPsu_Msg::RxBfrPtr, XQspiPsu::RxBytes, XQSPIPSU_CFG_OFFSET, XQSPIPSU_READMODE_IO, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_IntrRecvData(), and XQspiPsu_PolledRecvData().

s32 XQspiPsu_SetOptions	(	XQspiPsu *	InstancePtr,
		u32	Options
	)

Sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus.

The device must be idle rather than busy transferring data before setting these device options.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Options	Contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned ON and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

Note: This function is not thread-safe.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsManualstart, XQspiPsu::IsReady, XQSPIPS_BASEADDR, XQSPIPS_LQSPI_CFG_RST_STATE, XQSPIPS_LQSPI_CR_4_BYTE_STATE, XQSPIPS_LQSPI_CR_RST_STATE, XQSPIPSU_CFG_OFFSET, XQSPIPSU_EN_OFFSET, XQSPIPSU_LQSPI_CR_LINEAR_MASK, XQSPIPSU_LQSPI_CR_OFFSET, XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB, XQSPIPSU_LQSPI_MODE_OPTION, XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_NUM_OPTIONS, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by QspiPsuFlashNonBlockingReadExample(), QspiPsuInterruptFlashExample(), QspiPsuPolledFlashExample(), and QspiPsuWriteProtectFlashExample().

s32 XQspiPsu_SetReadMode	(	XQspiPsu *	InstancePtr,
		u32	Mode
	)

Sets the Read mode for the QSPIPSU device driver.

The device must be idle rather than busy transferring data before setting Read mode options.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Mode	Contains the specified Mode to be set. See the bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting Mode.

Note: This function is not thread-safe.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQspiPsu::ReadMode, XQSPIPSU_CFG_OFFSET, XQSPIPSU_READMODE_DMA, XQSPIPSU_READMODE_IO, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_PollDataHandler().

void XQspiPsu_SetStatusHandler	(	XQspiPsu *	InstancePtr,
		void *	CallBackRef,
		XQspiPsu_StatusHandler	FuncPointer
	)

Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software.

The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.

XST_SPI_TRANSFER_DONE           The requested data transfer is done

XST_SPI_TRANSMIT_UNDERRUN       As a slave device, the master clocked data
                        but there were none available in the transmit
                        register/FIFO. This typically means the slave
                        application did not issue a transfer request
                        fast enough, or the processor/driver could not
                        fill the transmit register/FIFO fast enough.

XST_SPI_RECEIVE_OVERRUN The QSPIPSU device lost data. Data was received
                        but the receive data register/FIFO was full.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
CallBackRef	Upper layer callback reference passed back when the callback function is invoked.
FuncPointer	Pointer to the callback function.

Returns: None.

Note

The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.

References XQspiPsu::IsReady, XQspiPsu::StatusHandler, and XQspiPsu::StatusRef.

Referenced by QspiPsuInterruptFlashExample(), and QspiPsuWriteProtectFlashExample().

void XQspiPsu_Setup64BRxDma	(	const XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

Sets up the RX DMA operation on a 32-bit Machine For 64-bit DMA transfers.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.

Returns: None

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu::IsReady, XQspiPsu_Msg::RxAddr64bit, XQspiPsu::RxBytes, XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_RXSetup().

void XQspiPsu_SetupRxDma	(	const XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

Sets up the RX DMA operation.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.

Returns: None

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu_Msg::ByteCount, XQspiPsu::Config, XQspiPsu_Config::IsCacheCoherent, XQspiPsu::IsReady, XQspiPsu_Msg::RxBfrPtr, XQspiPsu::RxBytes, XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, and XQspiPsu_WriteReg.

Referenced by XQspiPsu_RXSetup().

void XQspiPsu_SetWP	(	const XQspiPsu *	InstancePtr,
		u8	Value
	)

Sets the Write Protect and Hold options for the QSPIPSU device driver.

The device must be idle rather than busy transferring data before setting Write Protect and Hold options.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Value	Value of the WP_HOLD bit in configuration register

Returns: None

Note: This function is not thread-safe. This function can only be used with single flash configuration and x1/x2 data mode. This function cannot be used with x4 data mode and dual parallel and stacked flash configuration.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu::IsBusy, XQspiPsu::IsReady, XQSPIPSU_CFG_OFFSET, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

Referenced by QspiPsuWriteProtectFlashExample().

s32 XQspiPsu_StartDmaTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

Starts a DMA transfer.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
NumMsg	Number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if ByteCount is greater than XQSPIPSU_DMA_BYTES_MAX.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Msg::Flags, XQspiPsu::IsBusy, XQspiPsu::IsManualstart, XQspiPsu::IsReady, MAX_DELAY_CNT, XQspiPsu::Msg, XQspiPsu::ReadMode, XQspiPsu::TxBytes, XQSPIPSU_CFG_OFFSET, XQSPIPSU_DMA_BYTES_MAX, XQspiPsu_GenFifoEntryData(), XQSPIPSU_ISR_OFFSET, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_READMODE_DMA, XQSPIPSU_READMODE_IO, XQspiPsu_ReadReg, and XQspiPsu_WriteReg.

void XQspiPsu_TXRXSetup	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32 *	GenFifoEntry
	)

Checks the TX/RX buffers in the message and setups up the GENFIFO entries, TX FIFO, or RX DMA as required.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.
GenFifoEntry	Pointer to the variable in which GENFIFO mask is returned to calling function

Returns: None

References XQspiPsu_Msg::Flags, XQspiPsu::IsReady, XQspiPsu::RecvBufferPtr, XQspiPsu::RxBytes, XQspiPsu::SendBufferPtr, XQspiPsu::TxBytes, XQSPIPSU_MSG_FLAG_RX, XQSPIPSU_MSG_FLAG_TX, XQspiPsu_RXSetup(), and XQspiPsu_TXSetup().

Referenced by XQspiPsu_GenFifoEntryData().

void XQspiPsu_TXSetup	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

Checks the TX buffer in the message and setup the TX FIFO as required.

Parameters

InstancePtr	Pointer to the XQspiPsu instance.
Msg	Pointer to the structure containing transfer data.

Returns: None

Note: None.

References XQspiPsu_Msg::ByteCount, XQspiPsu::IsReady, XQspiPsu::SendBufferPtr, XQspiPsu_Msg::TxBfrPtr, XQspiPsu::TxBytes, and XQspiPsu_FillTxFifo().

Referenced by XQspiPsu_TXRXSetup().

void XQspiPsu_WriteProtectToggle	(	const XQspiPsu *	InstancePtr,
		u32	Toggle
	)

Enables/disables Write Protect pin on the flash parts.

Parameters

InstancePtr	Pointer to the QSPIPSU driver component to use.
Toggle	Value of the GPIO pin

Returns: None

Note: By default, the Write Protect pin as per the QSPI controller is driven High which means no write protection. Calling this function once will enable the protection.

References XQspiPsu_Config::BaseAddress, XQspiPsu::Config, XQspiPsu_Config::ConnectionMode, XQspiPsu::IsReady, XQSPIPSU_CONNECTION_MODE_SINGLE, XQSPIPSU_GPIO_OFFSET, and XQspiPsu_WriteReg.

Referenced by QspiPsuWriteProtectFlashExample().

Variable Documentation

XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]

Initial value:

= {
        {
                XPAR_XQSPIPSU_0_DEVICE_ID, 
                XPAR_XQSPIPSU_0_BASEADDR,  
                XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ,
                XPAR_XQSPIPSU_0_QSPI_MODE,
                XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH,
                XPAR_XQSPIPSU_0_IS_CACHE_COHERENT
        },
}

This table contains configuration information for each QSPIPSU device in the system.

Referenced by XQspiPsu_LookupConfig().

XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]

This table contains configuration information for each QSPIPSU device in the system.

Referenced by XQspiPsu_LookupConfig().

Data Structures

Macros

Typedefs

Functions

Variables

Macro Definition Documentation

Typedef Documentation

Function Documentation

Variable Documentation