Xilinx Vitis Drivers API Documentation
qspipsu Documentation

This section explains the implementation the functions required to use the QSPIPSU hardware to perform a transfer. These are accessible to the user via xqspipsu.h.

Generic QSPI interface allows for communication to any QSPI slave device. GQSPI contains a GENFIFO into which the bus transfers required are to be pushed with appropriate configuration. The controller provides TX and RX FIFO's and a DMA to be used for RX transfers. The controller executes each GENFIFO entry noting the configuration and places data on the bus as required

The different options in GENFIFO are as follows:

  • IMM_DATA : Can be one byte of data to be transmitted, number of clocks or number of bytes in transfer.
  • DATA_XFER : Indicates that data/clocks need to be transmitted or received.
  • EXPONENT : e when 2^e bytes are involved in transfer.
  • SPI_MODE : SPI/Dual SPI/Quad SPI
  • CS : Lower or Upper CS or Both
  • Bus : Lower or Upper Bus or Both
  • TX : When selected, controller transmits data in IMM or fetches number of bytes mentioned form TX FIFO. If not selected, dummies are pumped.
  • RX : When selected, controller receives and fills the RX FIFO/allows RX DMA of requested number of bytes. If not selected, RX data is discarded.
  • Stripe : Byte stripe over lower and upper bus or not.
  • Poll : Polls response to match for to a set value (used along with POLL_CFG registers) and then proceeds to next GENFIFO entry. This feature is not currently used in the driver.

GENFIFO has manual and auto start options. All DMA requests need a 4-byte aligned destination address buffer and size of transfer should also be a multiple of 4. This driver supports DMA RX and IO RX.

Initialization & Configuration

This driver uses the GQSPI controller with RX DMA. It supports both interrupt and polled transfers. Manual start of GENFIFO is used. XQspiPsu_CfgInitialize() initializes the instance variables. Additional setting can be done using SetOptions/ClearOptions functions and SelectSlave function.


Polled or Interrupt transfers can be done. The transfer function needs the message(s) to be transmitted in the form of an array of type XQspiPsu_Msg. This is supposed to contain the byte count and any TX/RX buffers as required. Flags can be used indicate further information such as whether the message should be striped. The transfer functions form and write GENFIFO entries, check the status of the transfer and report back to the application when done.

Ver   Who Date     Changes
--— — -----— --------------------------------------------—.
1.0   hk  08/21/14 First release
      sk  03/13/15 Added IO mode support.
      hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
                   Clear and disable DMA interrupts/status in abort.
                   Use DMA DONE bit instead of BUSY as recommended.
      sk  04/24/15 Modified the code according to MISRAC-2012.
      sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
                   writing/reading from 0x0 location is permitted.
1.1   sk  04/12/16 Added debug message prints.
1.2 nsk 07/01/16 Added LQSPI support
                 Modified XQspiPsu_Select() macro in xqspipsu.h
                 Added XQspiPsu_GetLqspiConfigReg() in xqspipsu.h
                 Added required macros in xqspipsu_hw.h
                 Modified XQspiPsu_SetOptions() to support
                 LQSPI options and updated OptionsTable in
      rk  07/15/16 Added support for TapDelays at different frequencies.
    nsk 08/05/16 Added example support PollData and PollTimeout
                 Added  XQSPIPSU_MSG_FLAG_POLL macro in xqspipsu.h
                 Added XQspiPsu_Create_PollConfigData and
                 XQspiPsu_PollData() functions in xqspipsu.c
1.3 nsk 09/16/16 Update PollData and Polltimeout support for dual parallel
                 configuration. Updated XQspiPsu_PollData() and
                 XQspiPsu_Create_PollConfigData() functions in xqspipsu.c
                   and also modified the polldata example
      ms  03/17/17 Added readme.txt file in examples folder for doxygen
      ms  04/05/17 Modified Comment lines in functions of qspipsu
                   examples to recognize it as documentation block
                   and modified filename tag to include them in
                   doxygen examples.
1.4 tjs 05/26/17 Added support for accessing upper DDR (0x800000000)
                 while booting images from QSPI
1.5 tjs 08/08/17 Added index.html file for importing examples
                 from system.mss
1.5 nsk 08/14/17 Added CCI support
1.5 tjs 09/14/17 Modified the checks for 4 byte addressing and commands.
1.6 tjs 10/16/17 Flow for accessing flash is made similar to u-boot
                 and linux For CR-984966
1.6   tjs 11/02/17 Resolved the compilation errors for ICCARM. CR-988625
1.7   tjs 11/16/17 Removed the unsupported 4 Byte write and sector erase
1.7 tjs 12/01/17 Added support for MT25QL02G Flash from Micron. CR-990642
1.7 tjs 12/19/17 Added support for S25FL064L from Spansion. CR-990724
1.7 tjs 01/11/18 Added support for MX66L1G45G flash from Macronix CR-992367
1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560)
1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448)
                   Added XQspiPsu_SetWP() in xqspipsu_options.c
                   Added XQspiPsu_WriteProtectToggle() in xqspipsu.c and
                   also added write protect example.
1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882)
1.7 tjs 26/03/18 In dual parallel mode enable both CS when issuing Write
                    enable command. CR-998478
1.8 tjs 05/02/18 Added support for IS25LP064 and IS25WP064.
1.8 tjs 06/26/18 Added an example for accessing 64bit dma within
                 32 bit application. CR#1004701
1.8 tjs 06/26/18 Removed checkpatch warnings
1.8 tjs 07/09/19 Fixed cppcheck, doxygen and gcc warnings.
1.8 tjs 07/18/18 Setup64BRxDma() should be called only if the RxAddress is
                 greater than 32 bit address space. (CR#1006862)
1.8 tjs 07/18/18 Added support for the low density ISSI flash parts.
1.8 tjs 09/06/18 Fixed the code in XQspiPsu_GenFifoEntryData() for data
                 transfer length up to 255 for reducing the extra loop.
1.9 tjs 11/22/17 Added the check for A72 and R5 processors (CR-987075)
1.9 tjs 04/17/18 Updated register addresses as per the latest revision
            of versal (CR#999610)
1.9  aru 01/17/19 Fixed the violations for  MISRAC-2012
                 in safety mode .Done changes such as added U suffix,
                 Declared pointer param as const.
1.9  nsk 02/01/19 Clear DMA_DST_ADDR_MSB register on 32bit machine, if the
             address is of only 32bit (CR#1020031)
1.9  nsk 02/01/19 Added QSPI idling support
1.9 akm 03/08/19 Set recommended clock and data tap delay values for 40MHZ,
                 100MHZ and 150MHZ frequencies(CR#1023187)
1.9  nsk 03/27/19 Update 64bit dma support
1.9  akm 04/03/19 Fixed data alignment warnings on IAR compiler.
1.9  akm 04/03/19 Fixed compilation error in XQspiPsu_LqspiRead()
                    function on IAR compiler.
1.10 sk  08/20/19 Fixed issues in poll timeout feature.
1.10 akm 08/22/19 Set recommended tap delay values for 37.5MHZ, 100MHZ and
             150MHZ frequencies in Versal.
1.10 akm 09/05/19 Added Multi Die Erase and Muti Die Read support.
1.11 akm 11/07/19 Removed LQSPI register access in Versal.
1.11    akm 11/15/19 Fixed Coverity deadcode warning in
1.11 akm 02/19/20 Added XQspiPsu_StartDmaTransfer() and XQspiPsu_CheckDmaDone()
                     APIs for non-blocking transfer.
1.11 sd  01/02/20 Added clocking support
1.11 akm 03/09/20 Reorganize the source code, enable qspi controller and
             interrupts in XQspiPsu_CfgInitialize() API.
1.11 akm 03/26/20 Fixed issue by updating XQspiPsu_CfgInitialize to return
             XST_DEVICE_IS_STARTED instead of asserting, when the
             instance is already configured(CR#1058525).
1.12    akm 09/02/20 Updated the Makefile to support parallel make execution.
1.13 akm 01/04/21 Fix MISRA-C violations.
1.13 sne 04/23/21 Fixed doxygen warnings.
1.14 akm 06/24/21 Allow enough time for the controller to reset the FIFOs.
1.14 akm 08/12/21 Perform Dcache invalidate at the end of the DMA transfer.