rfdc
Xilinx Vitis Drivers API Documentation
xrfdc_hw.h File Reference

Macros

#define XRFdc_ReadReg64(InstancePtr, BaseAddress, RegOffset)   XRFdc_In64(InstancePtr->io, ((u32)RegOffset + (u32)BaseAddress))
 Read a register. More...
 
#define XRFdc_WriteReg64(InstancePtr, BaseAddress, RegOffset, RegisterValue)   XRFdc_Out64((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))
 Write to a register. More...
 
#define XRFdc_ReadReg(InstancePtr, BaseAddress, RegOffset)   XRFdc_In32((InstancePtr->io), ((u32)BaseAddress + (u32)RegOffset))
 Read a register. More...
 
#define XRFdc_WriteReg(InstancePtr, BaseAddress, RegOffset, RegisterValue)   XRFdc_Out32((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))
 Write to a register. More...
 
#define XRFdc_ReadReg16(InstancePtr, BaseAddress, RegOffset)   XRFdc_In16((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress))
 Read a register. More...
 
#define XRFdc_WriteReg16(InstancePtr, BaseAddress, RegOffset, RegisterValue)   XRFdc_Out16((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))
 Write to a register. More...
 
#define XRFdc_ReadReg8(InstancePtr, BaseAddress, RegOffset)   XRFdc_In8((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress))
 Read a register. More...
 
#define XRFdc_WriteReg8(InstancePtr, BaseAddress, RegOffset, RegisterValue)   XRFdc_Out8((InstancePtr->io), ((u32)RegOffset + (u32)BaseAddress), (u32)(RegisterValue))
 Write to a register. More...
 
Register Map

Register offsets from the base address of an RFDC ADC and DAC device.

#define XRFDC_CLK_EN_OFFSET   0x000U
 ADC Clock Enable Register. More...
 
#define XRFDC_ADC_DEBUG_RST_OFFSET   0x004U
 ADC Debug Reset Register. More...
 
#define XRFDC_ADC_FABRIC_RATE_OFFSET   0x008U
 ADC Fabric Rate Register. More...
 
#define XRFDC_ADC_FABRIC_RATE_OBS_OFFSET   0x050U
 ADC Obs Fabric Rate Register. More...
 
#define XRFDC_ADC_FABRIC_RATE_TDD_OFFSET(X)
 ADC Fabric Rate (or OBS) Register TDD Selected. More...
 
#define XRFDC_DAC_FABRIC_RATE_OFFSET   0x008U
 DAC Fabric Rate Register. More...
 
#define XRFDC_ADC_FABRIC_OFFSET   0x00CU
 ADC Fabric Register. More...
 
#define XRFDC_ADC_FABRIC_OBS_OFFSET   0x054U
 ADC Obs Fabric Register. More...
 
#define XRFDC_ADC_FABRIC_TDD_OFFSET(X)
 ADC Fabric Register (or OBS) TDD Selected. More...
 
#define XRFDC_ADC_FABRIC_ISR_OFFSET   0x010U
 ADC Fabric ISR Register. More...
 
#define XRFDC_DAC_FIFO_START_OFFSET   0x010U
 DAC FIFO Start Register. More...
 
#define XRFDC_DAC_FABRIC_ISR_OFFSET   0x014U
 DAC Fabric ISR Register. More...
 
#define XRFDC_ADC_FABRIC_IMR_OFFSET   0x014U
 ADC Fabric IMR Register. More...
 
#define XRFDC_DAC_FABRIC_IMR_OFFSET   0x018U
 DAC Fabric IMR Register. More...
 
#define XRFDC_ADC_FABRIC_DBG_OFFSET   0x018U
 ADC Fabric Debug Register. More...
 
#define XRFDC_ADC_FABRIC_DBG_OBS_OFFSET   0x058U
 ADC Obs Fabric Debug Register. More...
 
#define XRFDC_ADC_FABRIC_DBG_TDD_OFFSET(X)
 ADC Fabric Debug (or OBS) Register TDD Selected. More...
 
#define XRFDC_ADC_UPDATE_DYN_OFFSET   0x01CU
 ADC Update Dynamic Register. More...
 
#define XRFDC_DAC_UPDATE_DYN_OFFSET   0x020U
 DAC Update Dynamic Register. More...
 
#define XRFDC_ADC_FIFO_LTNC_CRL_OFFSET   0x020U
 ADC FIFO Latency Control Register. More...
 
#define XRFDC_ADC_FIFO_LTNC_CRL_OBS_OFFSET   0x064U
 ADC Obs FIFO Latency Control Register. More...
 
#define XRFDC_ADC_FIFO_LTNC_CRL_TDD_OFFSET(X)
 ADC FIFO Latency Control (or OBS) Register TDD Selected. More...
 
#define XRFDC_ADC_DEC_ISR_OFFSET   0x030U
 ADC Decoder interface ISR Register. More...
 
#define XRFDC_DAC_DATAPATH_OFFSET   0x034U
 ADC Decoder interface IMR Register. More...
 
#define XRFDC_ADC_DEC_IMR_OFFSET   0x034U
 ADC Decoder interface IMR Register. More...
 
#define XRFDC_DATPATH_ISR_OFFSET   0x038U
 ADC Data Path ISR Register. More...
 
#define XRFDC_DATPATH_IMR_OFFSET   0x03CU
 ADC Data Path IMR Register. More...
 
#define XRFDC_ADC_DECI_CONFIG_OFFSET   0x040U
 ADC Decimation Config Register. More...
 
#define XRFDC_ADC_DECI_CONFIG_OBS_OFFSET   0x048U
 ADC Decimation Config Register. More...
 
#define XRFDC_ADC_DECI_CONFIG_TDD_OFFSET(X)
 ADC Decimation Config (or OBS) Register TDD Selected. More...
 
#define XRFDC_DAC_INTERP_CTRL_OFFSET   0x040U
 DAC Interpolation Control Register. More...
 
#define XRFDC_ADC_DECI_MODE_OFFSET   0x044U
 ADC Decimation mode Register. More...
 
#define XRFDC_ADC_DECI_MODE_OBS_OFFSET   0x04CU
 ADC Obs Decimation mode Register. More...
 
#define XRFDC_ADC_DECI_MODE_TDD_OFFSET(X)
 ADC Decimation mode (or OBS) Register TDD Selected. More...
 
#define XRFDC_DAC_ITERP_DATA_OFFSET   0x044U
 DAC interpolation data. More...
 
#define XRFDC_ADC_FABRIC_ISR_OBS_OFFSET   0x05CU
 ADC Fabric ISR Observation Register. More...
 
#define XRFDC_ADC_FABRIC_IMR_OBS_OFFSET   0x060U
 ADC Fabric ISR Observation Register. More...
 
#define XRFDC_DAC_TDD_MODE0_OFFSET   0x060U
 DAC TDD Mode 0 Configuration. More...
 
#define XRFDC_ADC_TDD_MODE0_OFFSET   0x068U
 ADC TDD Mode 0 Configuration. More...
 
#define XRFDC_TDD_MODE0_OFFSET(X)   ((X == 0) ? XRFDC_ADC_TDD_MODE0_OFFSET : XRFDC_DAC_TDD_MODE0_OFFSET)
 ADC TDD Mode 0 Configuration. More...
 
#define XRFDC_ADC_MXR_CFG0_OFFSET   0x080U
 ADC I channel mixer config Register. More...
 
#define XRFDC_ADC_MXR_CFG1_OFFSET   0x084U
 ADC Q channel mixer config Register. More...
 
#define XRFDC_MXR_MODE_OFFSET   0x088U
 ADC/DAC mixer mode Register. More...
 
#define XRFDC_NCO_UPDT_OFFSET   0x08CU
 ADC/DAC NCO Update mode Register. More...
 
#define XRFDC_NCO_RST_OFFSET   0x090U
 ADC/DAC NCO Phase Reset Register. More...
 
#define XRFDC_ADC_NCO_FQWD_UPP_OFFSET   0x094U
 ADC NCO Frequency Word[47:32] Register. More...
 
#define XRFDC_ADC_NCO_FQWD_MID_OFFSET   0x098U
 ADC NCO Frequency Word[31:16] Register. More...
 
#define XRFDC_ADC_NCO_FQWD_LOW_OFFSET   0x09CU
 ADC NCO Frequency Word[15:0] Register. More...
 
#define XRFDC_NCO_PHASE_UPP_OFFSET   0x0A0U
 ADC/DAC NCO Phase[17:16] Register. More...
 
#define XRFDC_NCO_PHASE_LOW_OFFSET   0x0A4U
 ADC/DAC NCO Phase[15:0] Register. More...
 
#define XRFDC_ADC_NCO_PHASE_MOD_OFFSET   0x0A8U
 ADC NCO Phase Mode Register. More...
 
#define XRFDC_QMC_UPDT_OFFSET   0x0C8U
 ADC/DAC QMC Update Mode Register. More...
 
#define XRFDC_QMC_CFG_OFFSET   0x0CCU
 ADC/DAC QMC Config Register. More...
 
#define XRFDC_QMC_OFF_OFFSET   0x0D0U
 ADC/DAC QMC Offset Correction Register. More...
 
#define XRFDC_QMC_GAIN_OFFSET   0x0D4U
 ADC/DAC QMC Gain Correction Register. More...
 
#define XRFDC_QMC_PHASE_OFFSET   0x0D8U
 ADC/DAC QMC Phase Correction Register. More...
 
#define XRFDC_ADC_CRSE_DLY_UPDT_OFFSET   0x0DCU
 ADC Coarse Delay Update Register. More...
 
#define XRFDC_DAC_CRSE_DLY_UPDT_OFFSET   0x0E0U
 DAC Coarse Delay Update Register. More...
 
#define XRFDC_ADC_CRSE_DLY_CFG_OFFSET   0x0E0U
 ADC Coarse delay Config Register. More...
 
#define XRFDC_DAC_CRSE_DLY_CFG_OFFSET   0x0DCU
 DAC Coarse delay Config Register. More...
 
#define XRFDC_ADC_DAT_SCAL_CFG_OFFSET   0x0E4U
 ADC Data Scaling Config Register. More...
 
#define XRFDC_ADC_SWITCH_MATRX_OFFSET   0x0E8U
 ADC Switch Matrix Config Register. More...
 
#define XRFDC_ADC_TRSHD0_CFG_OFFSET   0x0ECU
 ADC Threshold0 Config Register. More...
 
#define XRFDC_ADC_TRSHD0_AVG_UP_OFFSET   0x0F0U
 ADC Threshold0 Average[31:16] Register. More...
 
#define XRFDC_ADC_TRSHD0_AVG_LO_OFFSET   0x0F4U
 ADC Threshold0 Average[15:0] Register. More...
 
#define XRFDC_ADC_TRSHD0_UNDER_OFFSET   0x0F8U
 ADC Threshold0 Under Threshold Register. More...
 
#define XRFDC_ADC_TRSHD0_OVER_OFFSET   0x0FCU
 ADC Threshold0 Over Threshold Register. More...
 
#define XRFDC_ADC_TRSHD1_CFG_OFFSET   0x100U
 ADC Threshold1 Config Register. More...
 
#define XRFDC_ADC_TRSHD1_AVG_UP_OFFSET   0x104U
 ADC Threshold1 Average[31:16] Register. More...
 
#define XRFDC_ADC_TRSHD1_AVG_LO_OFFSET   0x108U
 ADC Threshold1 Average[15:0] Register. More...
 
#define XRFDC_ADC_TRSHD1_UNDER_OFFSET   0x10CU
 ADC Threshold1 Under Threshold Register. More...
 
#define XRFDC_ADC_TRSHD1_OVER_OFFSET   0x110U
 ADC Threshold1 Over Threshold Register. More...
 
#define XRFDC_ADC_FEND_DAT_CRL_OFFSET   0x140U
 ADC Front end Data Control Register. More...
 
#define XRFDC_ADC_TI_DCB_CRL0_OFFSET   0x144U
 ADC Time Interleaved digital correction block gain control0 Register. More...
 
#define XRFDC_ADC_TI_DCB_CRL1_OFFSET   0x148U
 ADC Time Interleaved digital correction block gain control1 Register. More...
 
#define XRFDC_ADC_TI_DCB_CRL2_OFFSET   0x14CU
 ADC Time Interleaved digital correction block gain control2 Register. More...
 
#define XRFDC_ADC_TI_DCB_CRL3_OFFSET   0x150U
 ADC Time Interleaved digital correction block gain control3 Register. More...
 
#define XRFDC_ADC_TI_TISK_CRL0_OFFSET   0x154U
 ADC Time skew correction control bits0 Register. More...
 
#define XRFDC_DAC_MC_CFG0_OFFSET   0x1C4U
 Static Configuration data for DAC Analog. More...
 
#define XRFDC_ADC_TI_TISK_CRL1_OFFSET   0x158U
 ADC Time skew correction control bits1 Register. More...
 
#define XRFDC_ADC_TI_TISK_CRL2_OFFSET   0x15CU
 ADC Time skew correction control bits2 Register. More...
 
#define XRFDC_ADC_TI_TISK_CRL3_OFFSET   0x160U
 ADC Time skew correction control bits3 Register. More...
 
#define XRFDC_ADC_TI_TISK_CRL4_OFFSET   0x164U
 ADC Time skew correction control bits4 Register. More...
 
#define XRFDC_ADC_TI_TISK_CRL5_OFFSET   0x168U
 ADC Time skew correction control bits5 Register (Gen 3 only) More...
 
#define XRFDC_ADC_TI_TISK_DAC0_OFFSET   0x168U
 ADC Time skew DAC cal code of subadc ch0 Register(Below Gen 3) More...
 
#define XRFDC_ADC_TI_TISK_DAC1_OFFSET   0x16CU
 ADC Time skew DAC cal code of subadc ch1 Register. More...
 
#define XRFDC_ADC_TI_TISK_DAC2_OFFSET   0x170U
 ADC Time skew DAC cal code of subadc ch2 Register. More...
 
#define XRFDC_ADC_TI_TISK_DAC3_OFFSET   0x174U
 ADC Time skew DAC cal code of subadc ch3 Register. More...
 
#define XRFDC_ADC_TI_TISK_DACP0_OFFSET   0x178U
 ADC Time skew DAC cal code of subadc ch0 Register. More...
 
#define XRFDC_ADC_TI_TISK_DACP1_OFFSET   0x17CU
 ADC Time skew DAC cal code of subadc ch1 Register. More...
 
#define XRFDC_ADC_TI_TISK_DACP2_OFFSET   0x180U
 ADC Time skew DAC cal code of subadc ch2 Register. More...
 
#define XRFDC_ADC_TI_TISK_DACP3_OFFSET   0x184U
 ADC Time skew DAC cal code of subadc ch3 Register. More...
 
#define XRFDC_DATA_SCALER_OFFSET   0x190U
 DAC Data Scaler Register. More...
 
#define XRFDC_DAC_VOP_CTRL_OFFSET   0x198U
 DAC variable output power control Register. More...
 
#define XRFDC_ADC0_SUBDRP_ADDR_OFFSET   0x198U
 subadc0, sub-drp address of target Register More...
 
#define XRFDC_ADC0_SUBDRP_DAT_OFFSET   0x19CU
 subadc0, sub-drp data of target Register More...
 
#define XRFDC_ADC1_SUBDRP_ADDR_OFFSET   0x1A0U
 subadc1, sub-drp address of target Register More...
 
#define XRFDC_ADC1_SUBDRP_DAT_OFFSET   0x1A4U
 subadc1, sub-drp data of target Register More...
 
#define XRFDC_ADC2_SUBDRP_ADDR_OFFSET   0x1A8U
 subadc2, sub-drp address of target Register More...
 
#define XRFDC_ADC2_SUBDRP_DAT_OFFSET   0x1ACU
 subadc2, sub-drp data of target Register More...
 
#define XRFDC_ADC3_SUBDRP_ADDR_OFFSET   0x1B0U
 subadc3, sub-drp address of target Register More...
 
#define XRFDC_ADC3_SUBDRP_DAT_OFFSET   0x1B4U
 subadc3, sub-drp data of target Register More...
 
#define XRFDC_ADC_RX_MC_PWRDWN_OFFSET   0x1C0U
 ADC Static configuration bits for ADC(RX) analog Register. More...
 
#define XRFDC_ADC_DAC_MC_CFG0_OFFSET   0x1C4U
 ADC/DAC Static configuration bits for ADC/DAC analog Register. More...
 
#define XRFDC_ADC_DAC_MC_CFG1_OFFSET   0x1C8U
 ADC/DAC Static configuration bits for ADC/DAC analog Register. More...
 
#define XRFDC_ADC_DAC_MC_CFG2_OFFSET   0x1CCU
 ADC/DAC Static configuration bits for ADC/DAC analog Register. More...
 
#define XRFDC_DAC_MC_CFG3_OFFSET   0x1D0U
 DAC Static configuration bits for DAC analog Register. More...
 
#define XRFDC_ADC_RXPR_MC_CFG0_OFFSET   0x1D0U
 ADC RX Pair static Configuration Register. More...
 
#define XRFDC_ADC_RXPR_MC_CFG1_OFFSET   0x1D4U
 ADC RX Pair static Configuration Register. More...
 
#define XRFDC_ADC_TI_DCBSTS0_BG_OFFSET   0x200U
 ADC DCB Status0 BG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS0_FG_OFFSET   0x204U
 ADC DCB Status0 FG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS1_BG_OFFSET   0x208U
 ADC DCB Status1 BG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS1_FG_OFFSET   0x20CU
 ADC DCB Status1 FG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS2_BG_OFFSET   0x210U
 ADC DCB Status2 BG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS2_FG_OFFSET   0x214U
 ADC DCB Status2 FG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS3_BG_OFFSET   0x218U
 ADC DCB Status3 BG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS3_FG_OFFSET   0x21CU
 ADC DCB Status3 FG Register. More...
 
#define XRFDC_ADC_TI_DCBSTS4_MB_OFFSET   0x220U
 ADC DCB Status4 MSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS4_LB_OFFSET   0x224U
 ADC DCB Status4 LSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS5_MB_OFFSET   0x228U
 ADC DCB Status5 MSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS5_LB_OFFSET   0x22CU
 ADC DCB Status5 LSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS6_MB_OFFSET   0x230U
 ADC DCB Status6 MSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS6_LB_OFFSET   0x234U
 ADC DCB Status6 LSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS7_MB_OFFSET   0x238U
 ADC DCB Status7 MSB Register. More...
 
#define XRFDC_ADC_TI_DCBSTS7_LB_OFFSET   0x23CU
 ADC DCB Status7 LSB Register. More...
 
#define XRFDC_DSA_UPDT_OFFSET   0x254U
 ADC DSA Update Trigger REgister. More...
 
#define XRFDC_ADC_FIFO_LTNCY_LB_OFFSET   0x280U
 ADC FIFO Latency measurement LSB Register. More...
 
#define XRFDC_ADC_FIFO_LTNCY_MB_OFFSET   0x284U
 ADC FIFO Latency measurement MSB Register. More...
 
#define XRFDC_DAC_DECODER_CTRL_OFFSET   0x180U
 DAC Unary Decoder/ Randomizer settings. More...
 
#define XRFDC_DAC_DECODER_CLK_OFFSET   0x184U
 Decoder Clock enable. More...
 
#define XRFDC_MB_CONFIG_OFFSET   0x308U
 Multiband Config status. More...
 
#define XRFDC_ADC_SIG_DETECT_CTRL_OFFSET   0x114
 ADC Signal Detector Control. More...
 
#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_LEVEL_OFFSET   0x118
 ADC Signal Detector Threshold 0. More...
 
#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_OFF_OFFSET   0x11C
 ADC Signal Detector Threshold 0 on Counter. More...
 
#define XRFDC_ADC_SIG_DETECT_THRESHOLD0_CNT_ON_OFFSET   0x120
 ADC Signal Detector Threshold 0 off Counter. More...
 
#define XRFDC_ADC_SIG_DETECT_MAGN_OFFSET   0x130
 ADC Signal Detector Magintude. More...
 
#define XRFDC_HSCOM_CLK_DSTR_OFFSET   0x088U
 Clock Distribution Register. More...
 
#define XRFDC_HSCOM_CLK_DSTR_MASK   0xC788U
 Clock Distribution Register. More...
 
#define XRFDC_HSCOM_CLK_DSTR_MASK_ALT   0x1870U
 Clock Distribution Register for Intratile. More...
 
#define XRFDC_HSCOM_PWR_OFFSET   0x094
 Control register during power-up sequence. More...
 
#define XRFDC_HSCOM_CLK_DIV_OFFSET   0xB0
 Fabric clk out divider. More...
 
#define XRFDC_HSCOM_PWR_STATE_OFFSET   0xB4
 Check powerup state. More...
 
#define XRFDC_HSCOM_UPDT_DYN_OFFSET   0x0B8
 Trigger the update dynamic event. More...
 
#define XRFDC_HSCOM_EFUSE_2_OFFSET   0x144
 
#define XRFDC_DAC_INVSINC_OFFSET   0x0C0U
 Invsinc control. More...
 
#define XRFDC_DAC_MB_CFG_OFFSET   0x0C4U
 Multiband config. More...
 
#define XRFDC_MTS_SRDIST   0x1CA0U
 
#define XRFDC_MTS_SRCAP_T1   (0x24U << 2U)
 
#define XRFDC_MTS_SRCAP_PLL   (0x0CU << 2U)
 
#define XRFDC_MTS_SRCAP_DIG   (0x2CU << 2U)
 
#define XRFDC_MTS_SRDTC_T1   (0x27U << 2U)
 
#define XRFDC_MTS_SRDTC_PLL   (0x26U << 2U)
 
#define XRFDC_MTS_SRFLAG   (0x49U << 2U)
 
#define XRFDC_MTS_CLKSTAT   (0x24U << 2U)
 
#define XRFDC_MTS_SRCOUNT_CTRL   0x004CU
 
#define XRFDC_MTS_SRCOUNT_VAL   0x0050U
 
#define XRFDC_MTS_SRFREQ_VAL   0x0054U
 
#define XRFDC_MTS_FIFO_CTRL_ADC   0x0010U
 
#define XRFDC_MTS_FIFO_CTRL_DAC   0x0014U
 
#define XRFDC_MTS_DELAY_CTRL   0x0028U
 
#define XRFDC_MTS_ADC_MARKER   0x0018U
 
#define XRFDC_MTS_ADC_MARKER_CNT   0x0010U
 
#define XRFDC_MTS_DAC_MARKER_CTRL   0x0048U
 
#define XRFDC_MTS_DAC_MARKER_CNT   (0x92U << 2U)
 
#define XRFDC_MTS_DAC_MARKER_LOC   (0x93U << 2U)
 
#define XRFDC_MTS_DAC_FIFO_MARKER_CTRL   (0x94U << 2U)
 
#define XRFDC_MTS_DAC_FABRIC_OFFSET   0x0C
 
#define XRFDC_RESET_OFFSET   0x00U
 Tile reset register. More...
 
#define XRFDC_RESTART_OFFSET   0x04U
 Tile restart register. More...
 
#define XRFDC_RESTART_STATE_OFFSET   0x08U
 Tile restart state register. More...
 
#define XRFDC_CURRENT_STATE_OFFSET   0x0CU
 Current state register. More...
 
#define XRFDC_CLOCK_DETECT_OFFSET   0x80U
 Clock detect register. More...
 
#define XRFDC_STATUS_OFFSET   0x228U
 Common status register. More...
 
#define XRFDC_CAL_DIV_BYP_OFFSET   0x100U
 Calibration divider bypass register. More...
 
#define XRFDC_COMMON_INTR_STS   0x100U
 Common Intr Status register. More...
 
#define XRFDC_COMMON_INTR_ENABLE   0x104U
 Common Intr enable register. More...
 
#define XRFDC_INTR_STS   0x200U
 Intr status register. More...
 
#define XRFDC_INTR_ENABLE   0x204U
 Intr enable register. More...
 
#define XRFDC_CONV_INTR_STS(X)   (0x208U + (X * 0x08U))
 
#define XRFDC_CONV_INTR_EN(X)   (0x20CU + (X * 0x08U))
 
#define XRFDC_CONV_CAL_STGS(X)   (0x234U + (X * 0x04U))
 
#define XRFDC_CONV_DSA_STGS(X)   (0x244U + (X * 0x04U))
 
#define XRFDC_CAL_GCB_COEFF0_FAB(X)   (0x280U + (X * 0x10U))
 
#define XRFDC_CAL_GCB_COEFF1_FAB(X)   (0x284U + (X * 0x10U))
 
#define XRFDC_CAL_GCB_COEFF2_FAB(X)   (0x288U + (X * 0x10U))
 
#define XRFDC_CAL_GCB_COEFF3_FAB(X)   (0x28CU + (X * 0x10U))
 
#define XRFDC_TDD_CTRL_SLICE_OFFSET(X)   (0x260 + (X * 0x04U))
 TDD control registers. More...
 
#define XRFDC_PLL_FREQ   0x300U
 PLL output frequency (before divider) register. More...
 
#define XRFDC_PLL_FS   0x304U
 Sampling rate register. More...
 
#define XRFDC_CAL_TMR_MULT_OFFSET   0x30CU
 Calibration timer register. More...
 
#define XRFDC_CAL_DLY_OFFSET   0x310U
 Calibration delay register. More...
 
#define XRFDC_FIFO_ENABLE   0x230U
 FIFO Enable and Disable. More...
 
#define XRFDC_PLL_SDM_CFG0   0x00U
 PLL Configuration bits for sdm. More...
 
#define XRFDC_PLL_SDM_SEED0   0x18U
 PLL Bits for sdm LSB. More...
 
#define XRFDC_PLL_SDM_SEED1   0x1CU
 PLL Bits for sdm MSB. More...
 
#define XRFDC_PLL_VREG   0x44U
 PLL bits for voltage regulator. More...
 
#define XRFDC_PLL_VCO0   0x54U
 PLL bits for coltage controlled oscillator LSB. More...
 
#define XRFDC_PLL_VCO1   0x58U
 PLL bits for coltage controlled oscillator MSB. More...
 
#define XRFDC_PLL_CRS1   0x28U
 PLL bits for coarse frequency control LSB. More...
 
#define XRFDC_PLL_CRS2   0x2CU
 PLL bits for coarse frequency control MSB. More...
 
#define XRFDC_PLL_DIVIDER0   0x30U
 PLL Output Divider LSB register. More...
 
#define XRFDC_PLL_DIVIDER1   0x34U
 PLL Output Divider MSB register. More...
 
#define XRFDC_PLL_SPARE0   0x38U
 PLL spare inputs LSB. More...
 
#define XRFDC_PLL_SPARE1   0x3CU
 PLL spare inputs MSB. More...
 
#define XRFDC_PLL_REFDIV   0x40U
 PLL Reference Divider register. More...
 
#define XRFDC_PLL_VREG   0x44U
 PLL bits for voltage regulator. More...
 
#define XRFDC_PLL_CHARGEPUMP   0x48U
 PLL bits for charge pumps. More...
 
#define XRFDC_PLL_LPF0   0x4CU
 PLL bits for loop filters LSB. More...
 
#define XRFDC_PLL_LPF1   0x50U
 PLL bits for loop filters MSB. More...
 
#define XRFDC_PLL_FPDIV   0x5CU
 PLL Feedback Divider register. More...
 
#define XRFDC_CLK_NETWORK_CTRL0   0x8CU
 Clock network control and trim register. More...
 
#define XRFDC_CLK_NETWORK_CTRL1   0x90U
 Multi-tile sync and clock source control register. More...
 
#define XRFDC_HSCOM_NETWORK_CTRL1_MASK   0x02FU
 Clock Network Register Mask for IntraTile. More...
 
#define XRFDC_PLL_REFDIV_MASK   0x0E0U
 PLL Reference Divider Register Mask for IntraTile. More...
 
#define XRFDC_PLL_DIVIDER0_ALT_MASK   0xC00U
 PLL Output Divider Register Mask for IntraTile. More...
 
#define XRFDC_PLL_DIVIDER0_BYPPLL_MASK   0x800U
 PLL Output Divider Register Mask for IntraTile. More...
 
#define XRFDC_PLL_DIVIDER0_BYPDIV_MASK   0x400U
 PLL Output Divider Register Mask for IntraTile. More...
 
#define XRFDC_CAL_OCB1_OFFSET_COEFF0   0x200
 Foreground offset correction block. More...
 
#define XRFDC_CAL_OCB1_OFFSET_COEFF1   0x208
 Foreground offset correction block. More...
 
#define XRFDC_CAL_OCB1_OFFSET_COEFF2   0x210
 Foreground offset correction block. More...
 
#define XRFDC_CAL_OCB1_OFFSET_COEFF3   0x218
 Foreground offset correction block. More...
 
#define XRFDC_CAL_OCB2_OFFSET_COEFF0   0x204
 Background offset correction block. More...
 
#define XRFDC_CAL_OCB2_OFFSET_COEFF1   0x20C
 Background offset correction block. More...
 
#define XRFDC_CAL_OCB2_OFFSET_COEFF2   0x214
 Background offset correction block. More...
 
#define XRFDC_CAL_OCB2_OFFSET_COEFF3   0x21C
 Background offset correction block. More...
 
#define XRFDC_CAL_GCB_OFFSET_COEFF0   0x220
 Background gain correction block. More...
 
#define XRFDC_CAL_GCB_OFFSET_COEFF1   0x224
 Background gain correction block. More...
 
#define XRFDC_CAL_GCB_OFFSET_COEFF2   0x228
 Background gain correction block. More...
 
#define XRFDC_CAL_GCB_OFFSET_COEFF3   0x22C
 Background gain correction block. More...
 
#define XRFDC_CAL_GCB_OFFSET_COEFF0_ALT   0x220
 Background gain correction block (below Gen 3) More...
 
#define XRFDC_CAL_GCB_OFFSET_COEFF1_ALT   0x228
 Background gain correction block (below Gen 3) More...
 
#define XRFDC_CAL_GCB_OFFSET_COEFF2_ALT   0x230
 Background gain correction block (below Gen 3) More...
 
#define XRFDC_CAL_GCB_OFFSET_COEFF3_ALT   0x238
 Background gain correction block (below Gen 3) More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF0   0x170
 Background time skew correction block. More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF1   0x174
 Background time skew correction block. More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF2   0x178
 Background time skew correction block. More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF3   0x17C
 Background time skew correction block. More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF4   0x180
 Background time skew correction block. More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF5   0x184
 Background time skew correction block. More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF6   0x188
 Background time skew correction block. More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF7   0x18C
 Background time skew correction block. More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF0_ALT   0x168
 Background time skew correction block (below Gen 3) More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF1_ALT   0x16C
 Background time skew correction block (below Gen 3) More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF2_ALT   0x170
 Background time skew correction block (below Gen 3) More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF3_ALT   0x174
 Background time skew correction block (below Gen 3) More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF4_ALT   0x178
 Background time skew correction block (below Gen 3) More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF5_ALT   0x17C
 Background time skew correction block (below Gen 3) More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF6_ALT   0x180
 Background time skew correction block (below Gen 3) More...
 
#define XRFDC_CAL_TSCB_OFFSET_COEFF7_ALT   0x184
 Background time skew correction block (below Gen 3) More...
 
#define XRFDC_HSCOM_FIFO_START_OFFSET   0x0C0U
 FIFO Start register tommon along tile. More...
 
#define XRFDC_HSCOM_FIFO_START_OBS_OFFSET   0x0BCU
 FIFO Obs Start register common along tile. More...
 
#define XRFDC_HSCOM_FIFO_START_TDD_OFFSET(X)
 FIFO Start (or OBS) register common along tile TDD Selected. More...
 
IP Register Map

Register offsets from the base address of the IP.

#define XRFDC_TILES_ENABLED_OFFSET   0x00A0U
 The tiles enabled in the design. More...
 
#define XRFDC_ADC_PATHS_ENABLED_OFFSET   0x00A4U
 The ADC analogue/digital paths enabled in the design. More...
 
#define XRFDC_DAC_PATHS_ENABLED_OFFSET   0x00A8U
 The DAC analogue/digital paths enabled in the design. More...
 
#define XRFDC_PATH_ENABLED_TILE_SHIFT   4U
 A shift to get to the correct tile for the path. More...
 
Tile State - Tile state register

This register contains bits for the current tile State.

#define XRFDC_CURRENT_STATE_MASK   0x0000000FU
 Current tile state mask. More...
 
Calibration Mode - Calibration mode registers

This register contains bits for calibration modes for ADC.

#define XRFDC_CAL_MODES_MASK   0x0003U
 Calibration modes for Gen 3 mask. More...
 
Calibration Coefficients - Calibration coefficients and disable registers

This register contains bits for calibration coefficients for ADC.

#define XRFDC_CAL_OCB_MASK   0xFFFFU
 offsets coeff mask More...
 
#define XRFDC_CAL_GCB_MASK   0x0FFFU
 gain coeff mask More...
 
#define XRFDC_CAL_GCB_FAB_MASK   0xFFF0U
 gain coeff mask for IP Gen 2 or below More...
 
#define XRFDC_CAL_TSCB_MASK   0x01FFU
 time skew coeff mask More...
 
#define XRFDC_CAL_GCB_FLSH_MASK   0x1000U
 GCB accumulator flush mask. More...
 
#define XRFDC_CAL_GCB_ACEN_MASK   0x0800U
 GCB accumulator enable mask. More...
 
#define XRFDC_CAL_GCB_ENFL_MASK   0x1800U
 GCB accumulator enable mask. More...
 
#define XRFDC_CAL_OCB_EN_MASK   0x0001U
 offsets coeff override enable mask More...
 
#define XRFDC_CAL_GCB_EN_MASK   0x2000U
 gain coeff override enable mask More...
 
#define XRFDC_CAL_TSCB_EN_MASK   0x8000U
 time skew coeff override enable mask More...
 
#define XRFDC_CAL_OCB_EN_SHIFT   0U
 offsets coeff shift More...
 
#define XRFDC_CAL_GCB_EN_SHIFT   13U
 gain coeff shift More...
 
#define XRFDC_CAL_TSCB_EN_SHIFT   15U
 time skew coeff shift More...
 
#define XRFDC_CAL_GCB_FLSH_SHIFT   12U
 GCB accumulator flush shift. More...
 
#define XRFDC_CAL_GCB_ACEN_SHIFT   11U
 GCB accumulator enable shift. More...
 
#define XRFDC_CAL_TSCB_TUNE_MASK   0x0FF0U
 time skew tuning mask More...
 
#define XRFDC_CAL_SLICE_SHIFT   16U
 Coefficient shift for HSADCs. More...
 
#define XRFDC_CAL_FREEZE_CAL_MASK   0x1U
 Calibration freeze enable mask. More...
 
#define XRFDC_CAL_FREEZE_STS_MASK   0x2U
 Calibration freeze status mask. More...
 
#define XRFDC_CAL_FREEZE_PIN_MASK   0x4U
 Calibration freeze pin disable mask. More...
 
#define XRFDC_CAL_FREEZE_CAL_SHIFT   0U
 Calibration freeze enable shift. More...
 
#define XRFDC_CAL_FREEZE_STS_SHIFT   1U
 Calibration freeze status shift. More...
 
#define XRFDC_CAL_FREEZE_PIN_SHIFT   2U
 Calibration freeze pin disable shift. More...
 
FIFO Enable - FIFO enable and disable register

This register contains bits for FIFO enable and disable for ADC and DAC.

#define XRFDC_FIFO_EN_MASK   0x00000001U
 FIFO enable/disable mask. More...
 
#define XRFDC_FIFO_EN_OBS_MASK   0x00000002U
 FIFO OBS enable/disable mask. More...
 
#define XRFDC_FIFO_EN_OBS_SHIFT   1U
 FIFO OBS enable/disable shift. More...
 
#define XRFDC_RESTART_MASK   0x00000001U
 Restart bit mask. More...
 
Clock Enable - FIFO Latency, fabric, DataPath,

full-rate, output register

This register contains bits for various clock enable options of the ADC. Read/Write apart from the reserved bits.

#define XRFDC_CLK_EN_CAL_MASK   0x00000001U
 Enable Output Register clock. More...
 
#define XRFDC_CLK_EN_DIG_MASK   0x00000002U
 Enable full-rate clock. More...
 
#define XRFDC_CLK_EN_DP_MASK   0x00000004U
 Enable Data Path clock. More...
 
#define XRFDC_CLK_EN_FAB_MASK   0x00000008U
 Enable fabric clock. More...
 
#define XRFDC_DAT_CLK_EN_MASK   0x0000000FU
 Data Path Clk enable. More...
 
#define XRFDC_CLK_EN_LM_MASK   0x00000010U
 Enable for FIFO Latency measurement clock. More...
 
Debug reset - FIFO Latency, fabric, DataPath,

full-rate, output register

This register contains bits for various Debug reset options of the ADC. Read/Write apart from the reserved bits.

#define XRFDC_DBG_RST_CAL_MASK   0x00000001U
 Reset clk_cal clock domain. More...
 
#define XRFDC_DBG_RST_DP_MASK   0x00000002U
 Reset data path clock domain. More...
 
#define XRFDC_DBG_RST_FAB_MASK   0x00000004U
 Reset clock fabric clock domain. More...
 
#define XRFDC_DBG_RST_DIG_MASK   0x00000008U
 Reset clk_dig clock domain. More...
 
#define XRFDC_DBG_RST_DRP_CAL_MASK   0x00000010U
 Reset subadc-drp register on clock cal. More...
 
#define XRFDC_DBG_RST_LM_MASK   0x00000020U
 Reset FIFO Latency measurement clock domain. More...
 
Fabric rate - Fabric data rate for read and write

This register contains bits for read and write fabric data rate for ADC.

Read/Write apart from the reserved bits.

#define XRFDC_ADC_FAB_RATE_WR_MASK   0x0000000FU
 ADC FIFO Write Number of Words per clock. More...
 
#define XRFDC_DAC_FAB_RATE_WR_MASK   0x0000001FU
 DAC FIFO Write Number of Words per clock. More...
 
#define XRFDC_ADC_FAB_RATE_RD_MASK   0x00000F00U
 ADC FIFO Read Number of Words per clock. More...
 
#define XRFDC_DAC_FAB_RATE_RD_MASK   0x00001F00U
 DAC FIFO Read Number of Words per clock. More...
 
#define XRFDC_FAB_RATE_RD_SHIFT   8U
 Fabric Read shift. More...
 
Fabric Offset - FIFO de-skew

This register contains bits of Fabric Offset.

Read/Write apart from the reserved bits.

#define XRFDC_FAB_RD_PTR_OFFST_MASK   0x0000003FU
 FIFO read pointer offset for interface de-skew. More...
 
Fabric ISR - Interrupt status register for FIFO interface

This register contains bits of margin-indicator and user-data overlap (overflow/underflow).

Read/Write apart from the reserved bits.

#define XRFDC_FAB_ISR_USRDAT_OVR_MASK   0x00000001U
 User-data overlap- data written faster than read (overflow) More...
 
#define XRFDC_FAB_ISR_USRDAT_UND_MASK   0x00000002U
 User-data overlap- data read faster than written (underflow) More...
 
#define XRFDC_FAB_ISR_USRDAT_MASK   0x00000003U
 User-data overlap Mask. More...
 
#define XRFDC_FAB_ISR_MARGIND_OVR_MASK   0x00000004U
 Marginal-indicator overlap (overflow) More...
 
#define XRFDC_FAB_ISR_MARGIND_UND_MASK   0x00000008U
 Marginal-indicator overlap (underflow) More...
 
Fabric IMR - Interrupt mask register for FIFO interface

This register contains bits of margin-indicator and user-data overlap (overflow/underflow).

Read/Write apart from the reserved bits.

#define XRFDC_FAB_IMR_USRDAT_OVR_MASK   0x00000001U
 User-data overlap- data written faster than read (overflow) More...
 
#define XRFDC_FAB_IMR_USRDAT_UND_MASK   0x00000002U
 User-data overlap- data read faster than written (underflow) More...
 
#define XRFDC_FAB_IMR_USRDAT_MASK   0x00000003U
 User-data overlap Mask. More...
 
#define XRFDC_FAB_IMR_MARGIND_OVR_MASK   0x00000004U
 Marginal-indicator overlap (overflow) More...
 
#define XRFDC_FAB_IMR_MARGIND_UND_MASK   0x00000008U
 Marginal-indicator overlap (underflow) More...
 
Update Dynamic - Trigger a dynamic update event

This register contains bits of update event for slice, nco, qmc and coarse delay.

Read/Write apart from the reserved bits.

#define XRFDC_UPDT_EVNT_MASK   0x0000000FU
 Update event mask. More...
 
#define XRFDC_UPDT_EVNT_SLICE_MASK   0x00000001U
 Trigger a slice update event apply to _DCONFIG reg. More...
 
#define XRFDC_UPDT_EVNT_NCO_MASK   0x00000002U
 Trigger a update event apply to NCO_DCONFIG reg. More...
 
#define XRFDC_UPDT_EVNT_QMC_MASK   0x00000004U
 Trigger a update event apply to QMC_DCONFIG reg. More...
 
#define XRFDC_ADC_UPDT_CRSE_DLY_MASK   0x00000008U
 ADC Trigger a update event apply to Coarse delay_DCONFIG reg. More...
 
#define XRFDC_DAC_UPDT_CRSE_DLY_MASK   0x00000020U
 DAC Trigger a update event apply to Coarse delay_DCONFIG reg. More...
 
FIFO Latency control - Config registers for FIFO Latency measurement

This register contains bits of FIFO Latency ctrl for disable, restart and set fifo latency measurement.

Read/Write apart from the reserved bits.

#define XRFDC_FIFO_LTNCY_PRD_MASK   0x00000007U
 Set FIFO Latency measurement period. More...
 
#define XRFDC_FIFO_LTNCY_RESTRT_MASK   0x00000008U
 Restart FIFO Latency measurement. More...
 
#define XRFDC_FIFO_LTNCY_DIS_MASK   0x000000010U
 Disable FIFO Latency measurement. More...
 
Decode ISR - ISR for Decoder Interface

This register contains bits of subadc 0,1,2 and 3 decoder overflow and underflow range.

Read/Write apart from the reserved bits.

#define XRFDC_DEC_ISR_SUBADC_MASK   0x000000FFU
 subadc decoder Mask More...
 
#define XRFDC_DEC_ISR_SUBADC0_UND_MASK   0x00000001U
 subadc0 decoder underflow range More...
 
#define XRFDC_DEC_ISR_SUBADC0_OVR_MASK   0x00000002U
 subadc0 decoder overflow range More...
 
#define XRFDC_DEC_ISR_SUBADC1_UND_MASK   0x00000004U
 subadc1 decoder underflow range More...
 
#define XRFDC_DEC_ISR_SUBADC1_OVR_MASK   0x00000008U
 subadc1 decoder overflow range More...
 
#define XRFDC_DEC_ISR_SUBADC2_UND_MASK   0x00000010U
 subadc2 decoder underflow range More...
 
#define XRFDC_DEC_ISR_SUBADC2_OVR_MASK   0x00000020U
 subadc2 decoder overflow range More...
 
#define XRFDC_DEC_ISR_SUBADC3_UND_MASK   0x00000040U
 subadc3 decoder underflow range More...
 
#define XRFDC_DEC_ISR_SUBADC3_OVR_MASK   0x00000080U
 subadc3 decoder overflow range More...
 
Decode IMR - IMR for Decoder Interface

This register contains bits of subadc 0,1,2 and 3 decoder overflow and underflow range.

Read/Write apart from the reserved bits.

#define XRFDC_DEC_IMR_SUBADC0_UND_MASK   0x00000001U
 subadc0 decoder underflow range More...
 
#define XRFDC_DEC_IMR_SUBADC0_OVR_MASK   0x00000002U
 subadc0 decoder overflow range More...
 
#define XRFDC_DEC_IMR_SUBADC1_UND_MASK   0x00000004U
 subadc1 decoder underflow range More...
 
#define XRFDC_DEC_IMR_SUBADC1_OVR_MASK   0x00000008U
 subadc1 decoder overflow range More...
 
#define XRFDC_DEC_IMR_SUBADC2_UND_MASK   0x00000010U
 subadc2 decoder underflow range More...
 
#define XRFDC_DEC_IMR_SUBADC2_OVR_MASK   0x00000020U
 subadc2 decoder overflow range More...
 
#define XRFDC_DEC_IMR_SUBADC3_UND_MASK   0x00000040U
 subadc3 decoder underflow range More...
 
#define XRFDC_DEC_IMR_SUBADC3_OVR_MASK   0x00000080U
 subadc3 decoder overflow range More...
 
#define XRFDC_DEC_IMR_MASK   0x000000FFU
 
DataPath (DAC)- FIFO Latency, Image Reject Filter, Mode,

This register contains bits for DataPath latency, Image Reject Filter and the Mode for the DAC.

Read/Write apart from the reserved bits.

#define XRFDC_DATAPATH_MODE_MASK   0x00000003U
 DataPath Mode. More...
 
#define XRFDC_DATAPATH_IMR_MASK   0x00000004U
 IMR Mode. More...
 
#define XRFDC_DATAPATH_LATENCY_MASK   0x00000008U
 DataPath Latency. More...
 
#define XRFDC_DATAPATH_IMR_SHIFT   2U
 IMR Mode shift. More...
 
DataPath ISR - ISR for Data Path interface

This register contains bits of QMC Gain/Phase overflow, offset overflow, Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.

Read/Write apart from the reserved bits.

#define XRFDC_ADC_DAT_PATH_ISR_MASK   0x000000FFU
 ADC Data Path Overflow. More...
 
#define XRFDC_DAC_DAT_PATH_ISR_MASK   0x0000FFFFU
 DAC Data Path Overflow. More...
 
#define XRFDC_DAT_ISR_DECI_IPATH_MASK   0x00000007U
 Decimation I-Path overflow for stages 0,1,2. More...
 
#define XRFDC_DAT_ISR_INTR_QPATH_MASK   0x00000038U
 Interpolation Q-Path overflow for stages 0,1,2. More...
 
#define XRFDC_DAT_ISR_QMC_GAIN_MASK   0x00000040U
 QMC Gain/Phase overflow. More...
 
#define XRFDC_DAT_ISR_QMC_OFFST_MASK   0x00000080U
 QMC offset overflow. More...
 
#define XRFDC_DAC_DAT_ISR_INVSINC_MASK   0x00000100U
 Inverse-Sinc offset overflow. More...
 
DataPath IMR - IMR for Data Path interface

This register contains bits of QMC Gain/Phase overflow, offset overflow, Decimation I-Path and Interpolation Q-Path overflow for stages 0,1,2.

Inverse sinc overflow, Datapath Scaling, Interpolation I and Q, IMR, and Even Nyquist Zone overflow Mixer I and Q over/underflow. Read/Write apart from the reserved bits.

#define XRFDC_DAT_IMR_DECI_IPATH_MASK   0x00000007U
 Decimation I-Path overflow for stages 0,1,2. More...
 
#define XRFDC_DAT_IMR_INTR_QPATH_MASK   0x00000038U
 Interpolation Q-Path overflow for stages 0,1,2. More...
 
#define XRFDC_DAT_IMR_QMC_GAIN_MASK   0x00000040U
 QMC Gain/Phase overflow. More...
 
#define XRFDC_DAT_IMR_QMC_OFFST_MASK   0x00000080U
 QMC offset overflow. More...
 
#define XRFDC_DAC_DAT_IMR_INV_SINC_MASK   0x00000100U
 Inverse Sinc overflow. More...
 
#define XRFDC_DAC_DAT_IMR_MXR_HLF_I_MASK   0x00000200U
 Over or under flow mixer (Mixer half I) More...
 
#define XRFDC_DAC_DAT_IMR_MXR_HLF_Q_MASK   0x00000400U
 Over or under flow mixer (Mixer half Q) More...
 
#define XRFDC_DAC_DAT_IMR_DP_SCALE_MASK   0x00000800U
 DataPath Scaling overflow. More...
 
#define XRFDC_DAC_DAT_IMR_INTR_IPATH3_MASK   0x00001000U
 Interpolation I-Path overflow for stage 3. More...
 
#define XRFDC_DAC_DAT_IMR_INTR_QPATH3_MASK   0x00002000U
 Interpolation Q-Path overflow for stage 3. More...
 
#define XRFDC_DAC_DAT_IMR_IMR_OV_MASK   0x00004000U
 IMR overflow. More...
 
#define XRFDC_DAC_DAT_IMR_INV_SINC_EVEN_NYQ_MASK   0x00008000U
 2nd Nyquist Zone Inverse SINC overflow More...
 
#define XRFDC_ADC_DAT_IMR_MASK   0x000000FFU
 ADC DataPath mask. More...
 
#define XRFDC_DAC_DAT_IMR_MASK   0x0000FFFFU
 DAC DataPath mask. More...
 
FIFO IMR - FIFO for Data Path interface

This register contains bits of FIFO over/underflows Read/Write apart from the reserved bits.

#define XRFDC_FIFO_USRD_OF_MASK   0x00000001U
 User data overflow. More...
 
#define XRFDC_FIFO_USRD_UF_MASK   0x00000002U
 User data underflow. More...
 
#define XRFDC_FIFO_MRGN_OF_MASK   0x00000004U
 Marginal overflow. More...
 
#define XRFDC_FIFO_MRGN_UF_MASK   0x00000008U
 Marginal underflow. More...
 
#define XRFDC_FIFO_ACTL_OF_MASK   0x00000010U
 DAC Actual overflow. More...
 
#define XRFDC_FIFO_ACTL_UF_MASK   0x00000020U
 DAC Actual underflow. More...
 
#define XRFDC_DAC_FIFO_IMR_SUPP_MASK   0x00000030U
 DAC FIFO Mask. More...
 
#define XRFDC_DAC_FIFO_IMR_MASK   0x0000003FU
 DAC FIFO Mask. More...
 
Decimation Config - Decimation control

This register contains bits to configure the decimation in terms of the type of data.

Read/Write apart from the reserved bits.

#define XRFDC_DEC_CFG_MASK   0x00000003U
 ChannelA (2GSPS real data from Mixer I output) More...
 
#define XRFDC_DEC_CFG_CHA_MASK   0x00000000U
 ChannelA(I) More...
 
#define XRFDC_DEC_CFG_CHB_MASK   0x00000001U
 ChannelB (2GSPS real data from Mixer Q output) More...
 
#define XRFDC_DEC_CFG_IQ_MASK   0x00000002U
 IQ-2GSPS. More...
 
#define XRFDC_DEC_CFG_4GSPS_MASK   0x00000003U
 4GSPS may be I or Q or Real depending on high level block config More...
 
Decimation Mode - Decimation Rate

This register contains bits to configures the decimation rate.

Read/Write apart from the reserved bits.

#define XRFDC_DEC_MOD_MASK   0x00000007U
 Decimation mode Mask. More...
 
#define XRFDC_DEC_MOD_MASK_EXT   0x0000003FU
 Decimation mode Mask. More...
 
Mixer config0 - Configure I channel coarse mixer mode of operation

This register contains bits to set the output data sequence of I channel.

Read/Write apart from the reserved bits.

#define XRFDC_MIX_CFG0_MASK   0x00000FFFU
 Mixer Config0 Mask. More...
 
#define XRFDC_MIX_I_DAT_WRD0_MASK   0x00000007U
 Output data word[0] of I channel. More...
 
#define XRFDC_MIX_I_DAT_WRD1_MASK   0x00000038U
 Output data word[1] of I channel. More...
 
#define XRFDC_MIX_I_DAT_WRD2_MASK   0x000001C0U
 Output data word[2] of I channel. More...
 
#define XRFDC_MIX_I_DAT_WRD3_MASK   0x00000E00U
 Output data word[3] of I channel. More...
 
Mixer config1 - Configure Q channel coarse mixer mode of operation

This register contains bits to set the output data sequence of Q channel.

Read/Write apart from the reserved bits.

#define XRFDC_MIX_CFG1_MASK   0x00000FFFU
 Mixer Config0 Mask. More...
 
#define XRFDC_MIX_Q_DAT_WRD0_MASK   0x00000007U
 Output data word[0] of Q channel. More...
 
#define XRFDC_MIX_Q_DAT_WRD1_MASK   0x00000038U
 Output data word[1] of Q channel. More...
 
#define XRFDC_MIX_Q_DAT_WRD2_MASK   0x000001C0U
 Output data word[2] of Q channel. More...
 
#define XRFDC_MIX_Q_DAT_WRD3_MASK   0x00000E00U
 Output data word[3] of Q channel. More...
 
Mixer mode - Configure mixer mode of operation

This register contains bits to set NCO phases, NCO output scale and fine mixer multipliers.

Read/Write apart from the reserved bits.

#define XRFDC_EN_I_IQ_MASK   0x00000003U
 Enable fine mixer multipliers on IQ i/p for I output. More...
 
#define XRFDC_EN_Q_IQ_MASK   0x0000000CU
 Enable fine mixer multipliers on IQ i/p for Q output. More...
 
#define XRFDC_FINE_MIX_SCALE_MASK   0x00000010U
 NCO output scale. More...
 
#define XRFDC_SEL_I_IQ_MASK   0x00000F00U
 Select NCO phases for I output. More...
 
#define XRFDC_SEL_Q_IQ_MASK   0x0000F000U
 Select NCO phases for Q output. More...
 
#define XRFDC_I_IQ_COS_MINSIN   0x00000C00U
 Select NCO phases for I output. More...
 
#define XRFDC_Q_IQ_SIN_COS   0x00001000U
 Select NCO phases for Q output. More...
 
#define XRFDC_MIXER_MODE_C2C_MASK   0x0000000FU
 Mixer mode C2C Mask. More...
 
#define XRFDC_MIXER_MODE_R2C_MASK   0x00000005U
 Mixer mode R2C Mask. More...
 
#define XRFDC_MIXER_MODE_C2R_MASK   0x00000003U
 Mixer mode C2R Mask. More...
 
#define XRFDC_MIXER_MODE_OFF_MASK   0x00000000U
 Mixer mode OFF Mask. More...
 
NCO update - NCO update mode

This register contains bits to Select event source, delay and reset delay.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_UPDT_MODE_MASK   0x00000007U
 NCO event source selection mask. More...
 
#define XRFDC_NCO_UPDT_MODE_GRP   0x00000000U
 NCO event source selection is Group. More...
 
#define XRFDC_NCO_UPDT_MODE_SLICE   0x00000001U
 NCO event source selection is slice. More...
 
#define XRFDC_NCO_UPDT_MODE_TILE   0x00000002U
 NCO event source selection is tile. More...
 
#define XRFDC_NCO_UPDT_MODE_SYSREF   0x00000003U
 NCO event source selection is Sysref. More...
 
#define XRFDC_NCO_UPDT_MODE_MARKER   0x00000004U
 NCO event source selection is Marker. More...
 
#define XRFDC_NCO_UPDT_MODE_FABRIC   0x00000005U
 NCO event source selection is fabric. More...
 
#define XRFDC_NCO_UPDT_DLY_MASK   0x00001FF8U
 delay in clk_dp cycles in application of event after arrival More...
 
#define XRFDC_NCO_UPDT_RST_DLY_MASK   0x0000D000U
 optional delay on the NCO phase reset delay More...
 
NCO Phase Reset - NCO Slice Phase Reset

This register contains bits to reset the nco phase of the current slice phase accumulator.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_PHASE_RST_MASK   0x00000001U
 Reset NCO Phase of current slice. More...
 
DAC interpolation data

This register contains bits for DAC interpolation data type

#define XRFDC_DAC_INTERP_DATA_MASK   0x00000001U
 Data type mask. More...
 
NCO Freq Word[47:32] - NCO Phase increment(nco freq 48-bit)

This register contains bits for frequency control word of the NCO.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_FQWD_UPP_MASK   0x0000FFFFU
 NCO Phase increment[47:32]. More...
 
#define XRFDC_NCO_FQWD_UPP_SHIFT   32U
 Freq Word upper shift. More...
 
NCO Freq Word[31:16] - NCO Phase increment(nco freq 48-bit)

This register contains bits for frequency control word of the NCO.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_FQWD_MID_MASK   0x0000FFFFU
 NCO Phase increment[31:16]. More...
 
#define XRFDC_NCO_FQWD_MID_SHIFT   16U
 Freq Word Mid shift. More...
 
NCO Freq Word[15:0] - NCO Phase increment(nco freq 48-bit)

This register contains bits for frequency control word of the NCO.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_FQWD_LOW_MASK   0x0000FFFFU
 NCO Phase increment[15:0]. More...
 
#define XRFDC_NCO_FQWD_MASK   0x0000FFFFFFFFFFFFU
 NCO Freq offset[48:0]. More...
 
NCO Phase Offset[17:16] - NCO Phase offset

This register contains bits to set NCO Phase offset(18-bit offset added to the phase accumulator).

Read/Write apart from the reserved bits.

#define XRFDC_NCO_PHASE_UPP_MASK   0x00000003U
 NCO Phase offset[17:16]. More...
 
#define XRFDC_NCO_PHASE_UPP_SHIFT   16U
 NCO phase upper shift. More...
 
NCO Phase Offset[15:0] - NCO Phase offset

This register contains bits to set NCO Phase offset(18-bit offset added to the phase accumulator).

Read/Write apart from the reserved bits.

#define XRFDC_NCO_PHASE_LOW_MASK   0x0000FFFFU
 NCO Phase offset[15:0]. More...
 
#define XRFDC_NCO_PHASE_MASK   0x0003FFFFU
 NCO Phase offset[17:0]. More...
 
NCO Phase mode - NCO Control setting mode

This register contains bits to set NCO mode of operation.

Read/Write apart from the reserved bits.

#define XRFDC_NCO_PHASE_MOD_MASK   0x00000003U
 NCO mode of operation mask. More...
 
#define XRFDC_NCO_PHASE_MOD_4PHASE   0x00000003U
 NCO output 4 successive phase. More...
 
#define XRFDC_NCO_PHASE_MOD_EVEN   0x00000001U
 NCO output even phase. More...
 
#define XRFDC_NCO_PHASE_MODE_ODD   0x00000002U
 NCO output odd phase. More...
 
QMC update - QMC update mode

This register contains bits to Select event source and delay.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_UPDT_MODE_MASK   0x00000007U
 QMC event source selection mask. More...
 
#define XRFDC_QMC_UPDT_MODE_GRP   0x00000000U
 QMC event source selection is group. More...
 
#define XRFDC_QMC_UPDT_MODE_SLICE   0x00000001U
 QMC event source selection is slice. More...
 
#define XRFDC_QMC_UPDT_MODE_TILE   0x00000002U
 QMC event source selection is tile. More...
 
#define XRFDC_QMC_UPDT_MODE_SYSREF   0x00000003U
 QMC event source selection is Sysref. More...
 
#define XRFDC_QMC_UPDT_MODE_MARKER   0x00000004U
 QMC event source selection is Marker. More...
 
#define XRFDC_QMC_UPDT_MODE_FABRIC   0x00000005U
 QMC event source selection is fabric. More...
 
#define XRFDC_QMC_UPDT_DLY_MASK   0x00001FF8U
 delay in clk_dp cycles in application of event after arrival More...
 
QMC Config - QMC Config register

This register contains bits to enable QMC gain and QMC Phase correction.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_CFG_EN_GAIN_MASK   0x00000001U
 enable QMC gain correction mask More...
 
#define XRFDC_QMC_CFG_EN_PHASE_MASK   0x00000002U
 enable QMC Phase correction mask More...
 
#define XRFDC_QMC_CFG_PHASE_SHIFT   1U
 QMC config phase shift. More...
 
QMC Offset - QMC offset correction

This register contains bits to set QMC offset correction factor.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_OFFST_CRCTN_MASK   0x00000FFFU
 QMC offset correction factor. More...
 
#define XRFDC_QMC_OFFST_CRCTN_SIGN_MASK   0x00000800
 QMC offset correction factor sign bit. More...
 
QMC Gain - QMC Gain correction

This register contains bits to set QMC gain correction factor.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_GAIN_CRCTN_MASK   0x00003FFFU
 QMC gain correction factor. More...
 
QMC Phase - QMC Phase correction

This register contains bits to set QMC phase correction factor.

Read/Write apart from the reserved bits.

#define XRFDC_QMC_PHASE_CRCTN_MASK   0x00000FFFU
 QMC phase correction factor. More...
 
#define XRFDC_QMC_PHASE_CRCTN_SIGN_MASK   0x00000800
 QMC phase correction factor sign bit. More...
 
Coarse Delay Update - Coarse delay update mode.

This register contains bits to Select event source and delay.

Read/Write apart from the reserved bits.

#define XRFDC_CRSEDLY_UPDT_MODE_MASK   0x00000007U
 Coarse delay event source selection mask. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_GRP   0x00000000U
 Coarse delay event source selection is group. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_SLICE   0x00000001U
 Coarse delay event source selection is slice. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_TILE   0x00000002U
 Coarse delay event source selection is tile. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_SYSREF   0x00000003U
 Coarse delay event source selection is sysref. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_MARKER   0x00000004U
 Coarse delay event source selection is Marker. More...
 
#define XRFDC_CRSEDLY_UPDT_MODE_FABRIC   0x00000005U
 Coarse delay event source selection is fabric. More...
 
#define XRFDC_CRSEDLY_UPDT_DLY_MASK   0x00001FF8U
 delay in clk_dp cycles in application of event after arrival More...
 
Coarse delay Config - Coarse delay select

This register contains bits to select coarse delay.

Read/Write apart from the reserved bits.

#define XRFDC_CRSE_DLY_CFG_MASK   0x00000007U
 Coarse delay select. More...
 
#define XRFDC_CRSE_DLY_CFG_MASK_EXT   0x0000003FU
 Extended coarse delay select. More...
 
Data Scaling Config - Data Scaling enable

This register contains bits to enable data scaling.

Read/Write apart from the reserved bits.

#define XRFDC_DAT_SCALE_CFG_MASK   0x00000001U
 Enable data scaling. More...
 
#define XRFDC_DAT_SCALE_CFG_MASK   0x00000001U
 Enable data scaling. More...
 
Switch Matrix Config

This register contains bits to control crossbar switch that select data to mixer block.

Read/Write apart from the reserved bits.

#define XRFDC_SWITCH_MTRX_MASK   0x0000003FU
 Switch matrix mask. More...
 
#define XRFDC_SEL_CB_TO_MIX1_MASK   0x00000003U
 Control crossbar switch that select the data to mixer block mux1. More...
 
#define XRFDC_SEL_CB_TO_MIX0_MASK   0x0000000CU
 Control crossbar switch that select the data to mixer block mux0. More...
 
#define XRFDC_SEL_CB_TO_QMC_MASK   0x00000010U
 Control crossbar switch that select the data to QMC. More...
 
#define XRFDC_SEL_CB_TO_DECI_MASK   0x00000020U
 Control crossbar switch that select the data to decimation filter. More...
 
#define XRFDC_SEL_CB_TO_MIX0_SHIFT   2U
 Crossbar Mixer0 shift. More...
 
Threshold0 Config

This register contains bits to select mode, clear mode and to clear sticky bit.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_EN_MOD_MASK   0x00000003U
 Enable Threshold0 block. More...
 
#define XRFDC_TRSHD0_CLR_MOD_MASK   0x00000004U
 Clear mode. More...
 
#define XRFDC_TRSHD0_STIKY_CLR_MASK   0x00000008U
 Clear sticky bit. More...
 
Threshold0 Average[31:16]

This register contains bits to select Threshold0 under averaging.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_AVG_UPP_MASK   0x0000FFFFU
 Threshold0 under Averaging[31:16]. More...
 
#define XRFDC_TRSHD0_AVG_UPP_SHIFT   16U
 Threshold0 Avg upper shift. More...
 
Threshold0 Average[15:0]

This register contains bits to select Threshold0 under averaging.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_AVG_LOW_MASK   0x0000FFFFU
 Threshold0 under Averaging[15:0]. More...
 
Threshold0 Under threshold

This register contains bits to select Threshold0 under threshold.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_UNDER_MASK   0x00003FFFU
 Threshold0 under Threshold[13:0]. More...
 
Threshold0 Over threshold

This register contains bits to select Threshold0 over threshold.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD0_OVER_MASK   0x00003FFFU
 Threshold0 under Threshold[13:0]. More...
 
Threshold1 Config

This register contains bits to select mode, clear mode and to clear sticky bit.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_EN_MOD_MASK   0x00000003U
 Enable Threshold1 block. More...
 
#define XRFDC_TRSHD1_CLR_MOD_MASK   0x00000004U
 Clear mode. More...
 
#define XRFDC_TRSHD1_STIKY_CLR_MASK   0x00000008U
 Clear sticky bit. More...
 
Threshold1 Average[31:16]

This register contains bits to select Threshold1 under averaging.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_AVG_UPP_MASK   0x0000FFFFU
 Threshold1 under Averaging[31:16]. More...
 
#define XRFDC_TRSHD1_AVG_UPP_SHIFT   16U
 Threshold1 Avg upper shift. More...
 
Threshold1 Average[15:0]

This register contains bits to select Threshold1 under averaging.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_AVG_LOW_MASK   0x0000FFFFU
 Threshold1 under Averaging[15:0]. More...
 
Threshold1 Under threshold

This register contains bits to select Threshold1 under threshold.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_UNDER_MASK   0x00003FFFU
 Threshold1 under Threshold[13:0]. More...
 
Threshold1 Over threshold

This register contains bits to select Threshold1 over threshold.

Read/Write apart from the reserved bits.

#define XRFDC_TRSHD1_OVER_MASK   0x00003FFFU
 Threshold1 under Threshold[13:0]. More...
 
TDD Control

This register contains bits to manage the TDD Control

#define XRFDC_TDD_CTRL_MASK   0x0000001FU
 All TDD control bits. More...
 
#define XRFDC_TDD_CTRL_MODE01_MASK   0x00000003U
 The TDD mode control bits. More...
 
#define XRFDC_TDD_CTRL_MODE0_MASK   0x00000001U
 The TDD control bit for Mode 0 config. More...
 
#define XRFDC_TDD_CTRL_MODE1_MASK   0x00000002U
 The TDD control bit for Mode 1 config (unused) More...
 
#define XRFDC_TDD_CTRL_OBS_EN_MASK   0x00000008U
 The observation port enable. More...
 
#define XRFDC_TDD_CTRL_RTP_MASK   0x00000004U
 The IP RTS disable bit. More...
 
#define XRFDC_TDD_CTRL_RTP_OBS_MASK   0x00000010U
 The IP RTS disable bit for the observation channel. More...
 
#define XRFDC_TDD_CTRL_MODE1_SHIFT   1U
 The TDD control bit for Mode 1 config (unused) More...
 
#define XRFDC_TDD_CTRL_OBS_EN_SHIFT   3U
 The observation port enable. More...
 
#define XRFDC_TDD_CTRL_RTP_SHIFT   2U
 The IP RTS disable bit. More...
 
#define XRFDC_TDD_CTRL_RTP_OBS_SHIFT   4U
 The IP RTS disable bit for the observation channel. More...
 
FrontEnd Data Control

This register contains bits to select raw data and cal coefficient to be streamed to memory.

Read/Write apart from the reserved bits.

#define XRFDC_FEND_DAT_CTRL_MASK   0x000000FFU
 raw data and cal coefficient to be streamed to memory More...
 
TI Digital Correction Block control0

This register contains bits for Time Interleaved digital correction block gain and offset correction.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_CTRL0_MASK   0x0000FFFFU
 TI DCB gain and offset correction. More...
 
#define XRFDC_TI_DCB_MODE_MASK   0x00007800U
 TI DCB Mode mask. More...
 
TI Digital Correction Block control1

This register contains bits for Time Interleaved digital correction block gain and offset correction.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_CTRL1_MASK   0x00001FFFU
 TI DCB gain and offset correction. More...
 
TI Digital Correction Block control2

This register contains bits for Time Interleaved digital correction block gain and offset correction.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_CTRL2_MASK   0x00001FFFU
 TI DCB gain and offset correction. More...
 
TI Time Skew control0

This register contains bits for Time skew correction control bits0(enables, mode, multiplier factors, debug).

Read/Write apart from the reserved bits.

#define XRFDC_TI_TISK_EN_MASK   0x00000001U
 Block Enable. More...
 
#define XRFDC_TI_TISK_MODE_MASK   0x00000002U
 Mode (2G/4G) More...
 
#define XRFDC_TI_TISK_ZONE_MASK   0x00000004U
 Specifies Nyquist zone. More...
 
#define XRFDC_TI_TISK_CHOP_EN_MASK   0x00000008U
 enable chopping mode More...
 
#define XRFDC_TI_TISK_MU_CM_MASK   0x000000F0U
 Constant mu_cm multiplying common mode path. More...
 
#define XRFDC_TI_TISK_MU_DF_MASK   0x00000F00U
 Constant mu_df multiplying differential path. More...
 
#define XRFDC_TI_TISK_DBG_CTRL_MASK   0x0000F000U
 Debug control. More...
 
#define XRFDC_TI_TISK_DBG_UPDT_RT_MASK   0x00001000U
 Debug update rate. More...
 
#define XRFDC_TI_TISK_DITH_DLY_MASK   0x0000E000U
 Programmable delay on dither path to match data path. More...
 
#define XRFDC_TISK_ZONE_SHIFT   2U
 Nyquist zone shift. More...
 
#define XRFDC_TISK_EN_MASK   0x00000001U
 Block Enable. More...
 
#define XRFDC_TISK_MODE_MASK   0x00000002U
 Mode (2G/4G) More...
 
#define XRFDC_TISK_ZONE_MASK   0x00000004U
 Specifies Nyquist zone. More...
 
#define XRFDC_TISK_CHOP_EN_MASK   0x00000008U
 enable chopping mode More...
 
#define XRFDC_TISK_MU_CM_MASK   0x000000F0U
 Constant mu_cm multiplying common mode path. More...
 
#define XRFDC_TISK_MU_DF_MASK   0x00000F00U
 Constant mu_df multiplying differential path. More...
 
#define XRFDC_TISK_DBG_CTRL_MASK   0x0000F000U
 Debug control. More...
 
#define XRFDC_TISK_DBG_UPDT_RT_MASK   0x00001000U
 Debug update rate. More...
 
#define XRFDC_TISK_DITH_DLY_MASK   0x0000E000U
 Programmable delay on dither path to match data path. More...
 
DAC MC Config0

This register contains bits for enable/disable shadow logic , Nyquist zone selection, enable full speed clock, Programmable delay.

#define XRFDC_MC_CFG0_MIX_MODE_MASK   0x00000002U
 Enable Mixing mode. More...
 
#define XRFDC_MC_CFG0_MIX_MODE_SHIFT   1U
 Mix mode shift. More...
 
TI Time Skew control1

This register contains bits for Time skew correction control bits1 (Deadzone Parameters).

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DZ_MIN_VAL_MASK   0x000000FFU
 Deadzone min. More...
 
#define XRFDC_TISK_DZ_MAX_VAL_MASK   0x0000FF00U
 Deadzone max. More...
 
TI Time Skew control2

This register contains bits for Time skew correction control bits2 (Filter parameters).

Read/Write apart from the reserved bits.

#define XRFDC_TISK_MU0_MASK   0x0000000FU
 Filter0 multiplying factor. More...
 
#define XRFDC_TISK_BYPASS0_MASK   0x00000080U
 ByPass filter0. More...
 
#define XRFDC_TISK_MU1_MASK   0x00000F00U
 Filter1 multiplying factor. More...
 
#define XRFDC_TISK_BYPASS1_MASK   0x00008000U
 Filter1 multiplying factor. More...
 
TI Time Skew control3

This register contains bits for Time skew control settling time following code update.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_SETTLE_MASK   0x000000FFU
 Settling time following code update. More...
 
TI Time Skew control4

This register contains bits for Time skew control setting time following code update.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_CAL_PRI_MASK   0x00000001U
 
#define XRFDC_TISK_DITH_INV_MASK   0x00000FF0U
 
TI Time Skew DAC0

This register contains bits for Time skew DAC cal code of subadc ch0.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DAC0_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch0 front end switch0. More...
 
#define XRFDC_TISK_DAC0_OVRID_EN_MASK   0x00008000U
 override enable More...
 
TI Time Skew DAC1

This register contains bits for Time skew DAC cal code of subadc ch1.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DAC1_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch1 front end switch0. More...
 
#define XRFDC_TISK_DAC1_OVRID_EN_MASK   0x00008000U
 override enable More...
 
TI Time Skew DAC2

This register contains bits for Time skew DAC cal code of subadc ch2.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DAC2_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch2 front end switch0. More...
 
#define XRFDC_TISK_DAC2_OVRID_EN_MASK   0x00008000U
 override enable More...
 
TI Time Skew DAC3

This register contains bits for Time skew DAC cal code of subadc ch3.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DAC3_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch3 front end switch0. More...
 
#define XRFDC_TISK_DAC3_OVRID_EN_MASK   0x00008000U
 override enable More...
 
TI Time Skew DACP0

This register contains bits for Time skew DAC cal code of subadc ch0.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DACP0_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch0 front end switch1. More...
 
#define XRFDC_TISK_DACP0_OVRID_EN_MASK   0x00008000U
 override enable More...
 
TI Time Skew DACP1

This register contains bits for Time skew DAC cal code of subadc ch1.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DACP1_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch1 front end switch1. More...
 
#define XRFDC_TISK_DACP1_OVRID_EN_MASK   0x00008000U
 override enable More...
 
TI Time Skew DACP2

This register contains bits for Time skew DAC cal code of subadc ch2.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DACP2_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch2 front end switch1. More...
 
#define XRFDC_TISK_DACP2_OVRID_EN_MASK   0x00008000U
 override enable More...
 
TI Time Skew DACP3

This register contains bits for Time skew DAC cal code of subadc ch3.

Read/Write apart from the reserved bits.

#define XRFDC_TISK_DACP3_CODE_MASK   0x000000FFU
 Code to correction DAC of subadc ch3 front end switch1. More...
 
#define XRFDC_TISK_DACP3_OVRID_EN_MASK   0x00008000U
 override enable More...
 
SubDRP ADC0 address

This register contains the sub-drp address of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC0_ADDR_MASK   0x000000FFU
 sub-drp0 address More...
 
SubDRP ADC0 Data

This register contains the sub-drp data of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC0_DAT_MASK   0x0000FFFFU
 sub-drp0 data for read or write transaction More...
 
SubDRP ADC1 address

This register contains the sub-drp address of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC1_ADDR_MASK   0x000000FFU
 sub-drp1 address More...
 
SubDRP ADC1 Data

This register contains the sub-drp data of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC1_DAT_MASK   0x0000FFFFU
 sub-drp1 data for read or write transaction More...
 
SubDRP ADC2 address

This register contains the sub-drp address of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC2_ADDR_MASK   0x000000FFU
 sub-drp2 address More...
 
SubDRP ADC2 Data

This register contains the sub-drp data of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC2_DAT_MASK   0x0000FFFFU
 sub-drp2 data for read or write transaction More...
 
SubDRP ADC3 address

This register contains the sub-drp address of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC3_ADDR_MASK   0x000000FFU
 sub-drp3 address More...
 
SubDRP ADC3 Data

This register contains the sub-drp data of the target register.

Read/Write apart from the reserved bits.

#define XRFDC_SUBDRP_ADC3_DAT_MASK   0x0000FFFFU
 sub-drp3 data for read or write transaction More...
 
RX MC PWRDWN

This register contains the static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_MC_PWRDWN_MASK   0x0000FFFFU
 RX MC power down. More...
 
RX MC Config0

This register contains the static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_MC_CFG0_MASK   0x0000FFFFU
 RX MC config0. More...
 
#define XRFDC_RX_MC_CFG0_CM_MASK   0x00000040U
 Coupling mode mask. More...
 
#define XRFDC_RX_MC_CFG0_IM3_DITH_MASK   0x00000020U
 IM3 Dither Enable mode mask. More...
 
#define XRFDC_RX_MC_CFG0_IM3_DITH_SHIFT   5U
 IM3 Dither Enable mode shift. More...
 
RX MC Config1

This register contains the static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_MC_CFG1_MASK   0x0000FFFFU
 RX MC Config1. More...
 
RX MC Config2

This register contains the static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_MC_CFG2_MASK   0x0000FFFFU
 RX MC Config2. More...
 
RX Pair MC Config0

This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_PR_MC_CFG0_MASK   0x0000FFFFU
 RX Pair MC Config0. More...
 
#define XRFDC_RX_PR_MC_CFG0_PSNK_MASK   0x00002000U
 RX Pair MC Config0. More...
 
#define XRFDC_RX_PR_MC_CFG0_IDIV_MASK   0x00000010U
 RX Pair MC Config0. More...
 
RX Pair MC Config1

This register contains the RX Pair (RX0 and RX1 or RX2 and RX3)static configuration bits of ADC(RX) analog.

Read/Write apart from the reserved bits.

#define XRFDC_RX_PR_MC_CFG1_MASK   0x0000FFFFU
 RX Pair MC Config1. More...
 
TI DCB Status0 BG

This register contains the subadc ch0 ocb1 BG offset correction factor value.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS0_BG_MASK   0x0000FFFFU
 DCB Status0 BG. More...
 
TI DCB Status0 FG

This register contains the subadc ch0 ocb2 FG offset correction factor value(read and write).

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS0_FG_MASK   0x0000FFFFU
 DCB Status0 FG. More...
 
TI DCB Status1 BG

This register contains the subadc ch1 ocb1 BG offset correction factor value.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS1_BG_MASK   0x0000FFFFU
 DCB Status1 BG. More...
 
TI DCB Status1 FG

This register contains the subadc ch1 ocb2 FG offset correction factor value(read and write).

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS1_FG_MASK   0x0000FFFFU
 DCB Status1 FG. More...
 
TI DCB Status2 BG

This register contains the subadc ch2 ocb1 BG offset correction factor value.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS2_BG_MASK   0x0000FFFFU
 DCB Status2 BG. More...
 
TI DCB Status2 FG

This register contains the subadc ch2 ocb2 FG offset correction factor value(read and write).

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS2_FG_MASK   0x0000FFFFU
 DCB Status2 FG. More...
 
TI DCB Status3 BG

This register contains the subadc ch3 ocb1 BG offset correction factor value.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS3_BG_MASK   0x0000FFFFU
 DCB Status3 BG. More...
 
TI DCB Status3 FG

This register contains the subadc ch3 ocb2 FG offset correction factor value(read and write).

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS3_FG_MASK   0x0000FFFFU
 DCB Status3 FG. More...
 
TI DCB Status4 MSB

This register contains the DCB status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS4_MSB_MASK   0x0000FFFFU
 read the status of gcb acc0 msb bits(subadc chan0) More...
 
TI DCB Status4 LSB

This register contains the DCB Status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS4_LSB_MASK   0x0000FFFFU
 read the status of gcb acc0 lsb bits(subadc chan0) More...
 
TI DCB Status5 MSB

This register contains the DCB status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS5_MSB_MASK   0x0000FFFFU
 read the status of gcb acc1 msb bits(subadc chan1) More...
 
TI DCB Status5 LSB

This register contains the DCB Status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS5_LSB_MASK   0x0000FFFFU
 read the status of gcb acc1 lsb bits(subadc chan1) More...
 
TI DCB Status6 MSB

This register contains the DCB status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS6_MSB_MASK   0x0000FFFFU
 read the status of gcb acc2 msb bits(subadc chan2) More...
 
TI DCB Status6 LSB

This register contains the DCB Status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS6_LSB_MASK   0x0000FFFFU
 read the status of gcb acc2 lsb bits(subadc chan2) More...
 
TI DCB Status7 MSB

This register contains the DCB status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS7_MSB_MASK   0x0000FFFFU
 read the status of gcb acc3 msb bits(subadc chan3) More...
 
TI DCB Status7 LSB

This register contains the DCB Status.

Read/Write apart from the reserved bits.

#define XRFDC_TI_DCB_STS7_LSB_MASK   0x0000FFFFU
 read the status of gcb acc3 lsb bits(subadc chan3) More...
 
PLL_REFDIV

This register contains the bits for Reference Clock Divider

#define XRFDC_REFCLK_DIV_MASK   0x1FU
 
#define XRFDC_REFCLK_DIV_1_MASK   0x10U
 Mask for Div1. More...
 
#define XRFDC_REFCLK_DIV_2_MASK   0x0U
 Mask for Div2. More...
 
#define XRFDC_REFCLK_DIV_3_MASK   0x1U
 Mask for Div3. More...
 
#define XRFDC_REFCLK_DIV_4_MASK   0x2U
 Mask for Div4. More...
 
FIFO Latency

This register contains bits for result, key and done flag.

Read/Write apart from the reserved bits.

#define XRFDC_FIFO_LTNCY_RES_MASK   0x00000FFFU
 Latency measurement result. More...
 
#define XRFDC_FIFO_LTNCY_KEY_MASK   0x00004000U
 Latency measurement result identification key. More...
 
#define XRFDC_FIFO_LTNCY_DONE_MASK   0x00008000U
 Latency measurement done flag. More...
 
Decoder Control

This register contains Unary Decoder/Randomizer settings to use.

#define XRFDC_DEC_CTRL_MODE_MASK   0x00000007U
 Decoder mode. More...
 
HSCOM Power state mask

This register contains HSCOM_PWR to check powerup_state.

#define XRFDC_HSCOM_PWR_STATE_MASK   0x0000FFFFU
 powerup state mask More...
 
Interpolation Control

This register contains Interpolation filter modes.

#define XRFDC_INTERP_MODE_MASK   0x00000077U
 Interp filter mask. More...
 
#define XRFDC_INTERP_MODE_I_MASK   0x00000007U
 Interp filter I. More...
 
#define XRFDC_INTERP_MODE_Q_SHIFT   4U
 Interp mode Q shift. More...
 
#define XRFDC_INTERP_MODE_MASK_EXT   0x00003F3FU
 Interp filter mask. More...
 
#define XRFDC_INTERP_MODE_I_MASK_EXT   0x0000003FU
 Interp filter I. More...
 
#define XRFDC_INTERP_MODE_Q_SHIFT_EXT   8U
 Interp mode Q shift. More...
 
Tile enables register

This register contains the bits that indicate whether or not a tile is enabled (Read Only).

#define XRFDC_DAC_TILES_ENABLED_SHIFT   4U
 Shift to the DAC tile bits. More...
 
Path enables register

This register contains the bits that indicate whether or not an analogue/digital is enabled (Read Only).

#define XRFDC_DIGITAL_PATH_ENABLED_SHIFT   16U
 Shift to the digital path bits. More...
 
Tile Reset

This register contains Tile reset bit.

#define XRFDC_TILE_RESET_MASK   0x00000001U
 Tile reset mask. More...
 
Status register

This register contains common status bits.

#define XRFDC_PWR_UP_STAT_MASK   0x00000004U
 Power Up state mask. More...
 
#define XRFDC_PWR_UP_STAT_SHIFT   2U
 PowerUp status shift. More...
 
#define XRFDC_PLL_LOCKED_MASK   0x00000008U
 PLL Locked mask. More...
 
#define XRFDC_PLL_LOCKED_SHIFT   3U
 PLL locked shift. More...
 
Restart State register

This register contains Start and End state bits.

#define XRFDC_PWR_STATE_MASK   0x0000FFFFU
 State mask. More...
 
#define XRFDC_RSR_START_SHIFT   8U
 Start state shift. More...
 
Clock Detect register

This register contains Start and End state bits.

#define XRFDC_CLOCK_DETECT_MASK   0x0000FFFFU
 Clock detect mask. More...
 
#define XRFDC_CLOCK_DETECT_SRC_MASK   0x00005555U
 Clock detect mask. More...
 
#define XRFDC_CLOCK_DETECT_DST_SHIFT   1U
 Clock detect mask. More...
 
Common interrupt enable register

This register contains bits to enable interrupt for ADC and DAC tiles.

#define XRFDC_EN_INTR_DAC_TILE0_MASK   0x00000001U
 DAC Tile0 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_DAC_TILE1_MASK   0x00000002U
 DAC Tile1 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_DAC_TILE2_MASK   0x00000004U
 DAC Tile2 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_DAC_TILE3_MASK   0x00000008U
 DAC Tile3 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_ADC_TILE0_MASK   0x00000010U
 ADC Tile0 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_ADC_TILE1_MASK   0x00000020U
 ADC Tile1 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_ADC_TILE2_MASK   0x00000040U
 ADC Tile2 interrupt enable mask. More...
 
#define XRFDC_EN_INTR_ADC_TILE3_MASK   0x00000080U
 ADC Tile3 interrupt enable mask. More...
 
interrupt enable register

This register contains bits to enable interrupt for blocks.

#define XRFDC_EN_INTR_SLICE_MASK   0x0000000FU
 Slice intr mask. More...
 
#define XRFDC_EN_INTR_SLICE0_MASK   0x00000001U
 slice0 interrupt enable mask More...
 
#define XRFDC_EN_INTR_SLICE1_MASK   0x00000002U
 slice1 interrupt enable mask More...
 
#define XRFDC_EN_INTR_SLICE2_MASK   0x00000004U
 slice2 interrupt enable mask More...
 
#define XRFDC_EN_INTR_SLICE3_MASK   0x00000008U
 slice3 interrupt enable mask More...
 
#define XRFDC_INTR_COMMON_MASK   0x00000010U
 Common interrupt enable mask. More...
 
Converter(X) interrupt register

This register contains bits to enable different interrupts for block X.

#define XRFDC_INTR_OVR_RANGE_MASK   0x00000008U
 Over Range interrupt mask. More...
 
#define XRFDC_INTR_OVR_VOLTAGE_MASK   0x00000004U
 Over Voltage interrupt mask. More...
 
#define XRFDC_INTR_FIFO_OVR_MASK   0x00008000U
 FIFO OF mask. More...
 
#define XRFDC_INTR_DAT_OVR_MASK   0x00004000U
 Data OF mask. More...
 
#define XRFDC_INTR_CMODE_OVR_MASK   0x00040000U
 Common mode OV mask. More...
 
#define XRFDC_INTR_CMODE_UNDR_MASK   0x00080000U
 Common mode UV mask. More...
 
Multiband config register

This register contains bits to configure multiband.

#define XRFDC_EN_MB_MASK   0x00000008U
 multi-band adder mask More...
 
#define XRFDC_EN_MB_SHIFT   3U /** <Enable Multiband shift */
 
#define XRFDC_DAC_MB_SEL_MASK   0x0003U /** <Local and remote select mask */
 
#define XRFDC_ALT_BOND_MASK   0x0200U /** <Alt bondout mask */
 
#define XRFDC_ALT_BOND_SHIFT   9U /** <Alt bondout shift */
 
#define XRFDC_ALT_BOND_CLKDP_MASK   0x4U /** <Alt bondout shift */
 
#define XRFDC_ALT_BOND_CLKDP_SHIFT   2U /** <Alt bondout shift */
 
#define XRFDC_MB_CONFIG_MASK   0x00000007U /** <Multiband Config mask */
 
Invsinc control register

This register contains bits to configure Invsinc.

#define XRFDC_EN_INVSINC_MASK   0x00000001U
 invsinc enable mask More...
 
#define XRFDC_MODE_INVSINC_MASK   0x00000003U
 invsinc mode mask More...
 
OBS FIFO start register

This register contains bits to configure Invsinc.

#define XRFDC_HSCOM_FIFO_START_OBS_EN_MASK   0x00000200U
 invsinc enable mask More...
 
#define XRFDC_HSCOM_FIFO_START_OBS_EN_SHIFT   9U
 invsinc mode mask More...
 
Signal Detector control register

This register contains bits to configure Signal Detector.

#define XRFDC_ADC_SIG_DETECT_MASK   0xFF
 signal detector mask More...
 
#define XRFDC_ADC_SIG_DETECT_THRESH_MASK   0xFFFF
 signal detector thresholds mask More...
 
#define XRFDC_ADC_SIG_DETECT_THRESH_CNT_MASK   0xFFFF
 signal detector thresholds counter mask More...
 
#define XRFDC_ADC_SIG_DETECT_INTG_MASK   0x01
 leaky integrator enable mask More...
 
#define XRFDC_ADC_SIG_DETECT_FLUSH_MASK   0x02
 leaky integrator flush mask More...
 
#define XRFDC_ADC_SIG_DETECT_TCONST_MASK   0x1C
 time constant mask More...
 
#define XRFDC_ADC_SIG_DETECT_MODE_MASK   0x60
 mode mask More...
 
#define XRFDC_ADC_SIG_DETECT_HYST_MASK   0x80
 hysteresis enable mask More...
 
#define XRFDC_ADC_SIG_DETECT_INTG_SHIFT   0
 leaky integrator enable shift More...
 
#define XRFDC_ADC_SIG_DETECT_FLUSH_SHIFT   1
 leaky integrator flush shift More...
 
#define XRFDC_ADC_SIG_DETECT_TCONST_SHIFT   2
 time constant shift More...
 
#define XRFDC_ADC_SIG_DETECT_MODE_WRITE_SHIFT   5
 mode shift fror writing More...
 
#define XRFDC_ADC_SIG_DETECT_MODE_READ_SHIFT   6
 mode shift fror reading More...
 
#define XRFDC_ADC_SIG_DETECT_HYST_SHIFT   7
 hysteresis enable shift More...
 
CLK_DIV register

This register contains the bits to control the clock divider providing the clock fabric out.

#define XRFDC_FAB_CLK_DIV_MASK   0x0000000FU
 clk div mask More...
 
#define XRFDC_FAB_CLK_DIV_CAL_MASK   0x000000F0U
 clk div cal mask More...
 
Multiband Config

This register contains bits to configure multiband for DAC.

#define XRFDC_MB_CFG_MASK   0x000001FFU
 MB config mask. More...
 
#define XRFDC_MB_EN_4X_MASK   0x00000100U
 Enable 4X MB mask. More...
 
Multi Tile Sync

Multi-Tile Sync bit masks.

#define XRFDC_MTS_SRCAP_PLL_M   0x0100U
 
#define XRFDC_MTS_SRCAP_DIG_M   0x0100U
 
#define XRFDC_MTS_SRCAP_EN_TRX_M   0x0400U
 
#define XRFDC_MTS_SRCAP_INIT_M   0x8200U
 
#define XRFDC_MTS_SRCLR_T1_M   0x2000U
 
#define XRFDC_MTS_SRCLR_PLL_M   0x0200U
 
#define XRFDC_MTS_PLLEN_M   0x0001U
 
#define XRFDC_MTS_SRCOUNT_M   0x00FFU
 
#define XRFDC_MTS_DELAY_VAL_M   0x041FU
 
#define XRFDC_MTS_AMARK_CNT_M   0x00FFU
 
#define XRFDC_MTS_AMARK_LOC_M   0x0F0000U
 
#define XRFDC_MTS_AMARK_DONE_M   0x100000U
 
Output divider LSB register

This register contains bits to configure output divisor

#define XRFDC_PLL_DIVIDER0_MASK   0x0CFFU
 
#define XRFDC_PLL_DIVIDER0_MODE_MASK   0x00C0U
 
#define XRFDC_PLL_DIVIDER0_BYP_OPDIV_MASK   0x0400U
 
#define XRFDC_PLL_DIVIDER0_BYP_PLL_MASK   0x0800U
 
#define XRFDC_PLL_DIVIDER0_VALUE_MASK   0x003FU
 
#define XRFDC_PLL_DIVIDER0_SHIFT   6U
 
Multi-tile sync and clock source control register

This register contains bits to Multi-tile sync and clock source control

#define XRFDC_CLK_NETWORK_CTRL1_USE_PLL_MASK   0x1U
 PLL clock mask. More...
 
#define XRFDC_CLK_NETWORK_CTRL1_USE_RX_MASK   0x2U
 PLL clock mask. More...
 
#define XRFDC_CLK_NETWORK_CTRL1_REGS_MASK   0x3U
 PLL clock mask. More...
 
PLL_CRS1 - PLL CRS1 register

This register contains bits for VCO sel_auto, VCO band selection etc.,

#define XRFDC_PLL_CRS1_VCO_SEL_MASK   0x00008001U
 VCO SEL Mask. More...
 
#define XRFDC_PLL_VCO_SEL_AUTO_MASK   0x00008000U
 VCO Auto SEL Mask. More...
 
#define XRFDC_DIGI_ANALOG_SHIFT4   4U
 Register bits Shift, Width Masks. More...
 
FIFO Delays

This register contains bits for delaying the FIFOs.,

#define XRFDC_DAC_FIFO_DELAY_MASK   0x000000FFFU
 DAC FIFO ReadPtr Delay. More...
 
#define XRFDC_ADC_FIFO_DELAY_MASK   0x0000001C0U
 ADC FIFO ReadPtr Delay. More...
 
#define XRFDC_ADC_FIFO_DELAY_SHIFT   6U
 ADC FIFO ReadPtr Shift. More...
 
Data Scaler register

This register contains the data scaler ebable bit.

#define XRFDC_DATA_SCALER_MASK   0x00000001U
 Clock detect mask. More...
 
Calibration divider bypass register

This register contains the calibration divider bypass enable bit.

#define XRFDC_CAL_DIV_BYP_MASK   0x00000004U
 Calibration divider bypass mask. More...