Overview

This file demonstrates how to use the xtrafgen driver on the Xilinx AXI Traffic Generator core.

The AXI Traffic Generator IP is designed to generate AXI4 traffic which can be used to stress different modules/ interconnect connected in the system. It has three internal RAMS: MASTER RAM, COMMAND RAM, PARAMETER RAM. MASTER RAM is used to load/store data from this memory for write/read transactions. And the commands to be issued are loaded into COMMAND and PARAMETER RAMs.

This example demonstrates by programming known data to Master RAM and commands to Command and Param RAM. Initiating the master logic will take the data from Master RAM (from a location) and generate data for slave transactions which will be stored in Master RAM at a different location specified by commands. The test passes when the master logic interrupt asserts and verifies for data to be same.

MODIFICATION HISTORY:

Ver   Who  Date     Changes
----- ---- -------- -------------------------------------------------------
1.00a srt  01/25/13 First release
4.1   ms   01/23/17 Modified xil_printf statement in main function to
                    ensure that "Successfully ran" and "Failed" strings
                    are available in all examples. This is a fix for
                    CR-965028.
      ms   04/05/17 Added tabspace for return statements in functions for
                    proper documentation while generating doxygen.
4.5   sd   07/18/23 Fix the disable interrupt
4.7   ar   03/07/24 Fix the interrupt ID sequence in the SDT flow.

Functions
int	XTrafGenInterruptExample (XTrafGen *InstancePtr, u16 DeviceId)
	This function demonstrates the usage Traffic Generator It does the following: More...

int	main ()
	Main function. More...

Function Documentation

int main ( )

Main function.

This function is the main entry of the traffic generator test.

Parameters

None

Returns

XST_SUCCESS if tests pass
- XST_FAILURE if fails.

Note: None

References XTrafGenInterruptExample().

int XTrafGenInterruptExample	(	XTrafGen *	InstancePtr,
		u16	DeviceId
	)

This function demonstrates the usage Traffic Generator It does the following:

  - Set up the output terminal if UART16550 is in the hardware build
  - Initialize the AXI Traffic Generator device
  - Initialize Master RAM
  - Initialize commands and add them to list
  - Program internal command and parameter RAMs
  - Start Master Logic
  - Wait for the master logic to finish
  - Check for errors
  - Read Master RAM and verify data
  - Return test status and exit

Parameters

InstancePtr	is a pointer to the instance of the XTrafGen component.
DeviceId	is Device ID of the Axi Traffic Generator Device, typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from xparameters.h.

Returns: -XST_SUCCESS to indicate success -XST_FAILURE to indicate failure

References XTrafGen_CRamCmd::Address, XTrafGen_Config::BaseAddress, XTrafGen::Config, XTrafGen_Cmd::CRamCmd, ERROR_INTRID, XTrafGen_Config::IntId, XTrafGen_CRamCmd::Length, MASTER_INTRID, XTrafGen_CRamCmd::MasterRamIndex, XTrafGen_CRamCmd::MyDepend, XTrafGen_CRamCmd::OtherDepend, XTrafGen_Cmd::RdWrFlag, XTrafGen_CRamCmd::Size, XTrafGen_CRamCmd::ValidCmd, XTG_READ, XTG_WRITE, XTrafGen_AccessMasterRam(), XTrafGen_AddCommand(), XTrafGen_CfgInitialize(), XTrafGen_EnableMasterCmpInterrupt, XTrafGen_GetLastValidIndex(), XTrafGen_LookupConfig(), XTrafGen_PrintCmds(), XTrafGen_StartMasterLogic, and XTrafGen_WriteCmdsToHw().

Referenced by main().

Overview

Functions

Function Documentation