 |
v_hdmiphy1
Vitis Drivers API Documentation
|
|
v_hdmiphy1
Vitis Drivers API Documentation
|
This header file contains the identifiers and low-level driver functions (or macros) that can be used to access the device.
High-level driver functions are defined in xhdmiphy1.h.
MODIFICATION HISTORY:
Ver Who Date Changes
dd/mm/yy
1.0 gm 10/12/18 Initial release.
Macros | |
| #define | XHDMIPHY1_RX_CONTROL_RXLPMEN_ALL_MASK |
| RX LPM enable mask for all channels. More... | |
| #define | XHDMIPHY1_INTR_TXRESETDONE_MASK 0x00000001 |
| TX reset done interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_RXRESETDONE_MASK 0x00000002 |
| RX reset done interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_CPLL_LOCK_MASK 0x00000004 |
| CPLL lock interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_QPLL0_LOCK_MASK 0x00000008 |
| QPLL0 lock interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_LCPLL_LOCK_MASK 0x00000008 |
| LCPLL lock interrupt mask (alias for QPLL0) More... | |
| #define | XHDMIPHY1_INTR_TXALIGNDONE_MASK 0x00000010 |
| TX alignment done interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_QPLL1_LOCK_MASK 0x00000020 |
| QPLL1 lock interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_RPLL_LOCK_MASK 0x00000020 |
| RPLL lock interrupt mask (alias for QPLL1) More... | |
| #define | XHDMIPHY1_INTR_TXCLKDETFREQCHANGE_MASK 0x00000040 |
| TX clock detector frequency change interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_RXCLKDETFREQCHANGE_MASK 0x00000080 |
| RX clock detector frequency change interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_TXMMCMUSRCLK_LOCK_MASK 0x00000200 |
| TX MMCM user clock lock interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_RXMMCMUSRCLK_LOCK_MASK 0x00000400 |
| RX MMCM user clock lock interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_TXGPO_RE_MASK 0x00000800 |
| TX GPO rising edge interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_RXGPO_RE_MASK 0x00001000 |
| RX GPO rising edge interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_TXTMRTIMEOUT_MASK 0x40000000 |
| TX timer timeout interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_RXTMRTIMEOUT_MASK 0x80000000 |
| RX timer timeout interrupt mask. More... | |
| #define | XHDMIPHY1_INTR_QPLL_LOCK_MASK XHDMIPHY1_INTR_QPLL0_LOCK_MASK |
| QPLL lock interrupt mask (alias for QPLL0) More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_CTRL_CFG_NEW_MASK 0x01 |
| MMCM user clock control configuration new mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_CTRL_RST_MASK 0x02 |
| MMCM user clock control reset mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_CTRL_CFG_SUCCESS_MASK 0x10 |
| MMCM user clock control configuration success mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_CTRL_LOCKED_MASK 0x200 |
| MMCM user clock control locked mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_CTRL_PWRDWN_MASK 0x400 |
| MMCM user clock control power down mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK 0x800 |
| MMCM user clock control locked mask mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_CTRL_CLKINSEL_MASK 0x1000 |
| MMCM user clock control clock input select mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_REG1_DIVCLK_MASK 0x00000FF |
| MMCM user clock register 1 divider clock mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_MULT_MASK 0x000FF00 |
| MMCM user clock register 1 clock feedback output multiplier mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_MULT_SHIFT 8 |
| MMCM user clock register 1 clock feedback output multiplier shift. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_FRAC_MASK 0x3FF0000 |
| MMCM user clock register 1 clock feedback output fractional mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_REG1_CLKFBOUT_FRAC_SHIFT 16 |
| MMCM user clock register 1 clock feedback output fractional shift. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_REG2_DIVCLK_MASK 0x00000FF |
| MMCM user clock register 2 divider clock mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_REG2_CLKOUT0_FRAC_MASK 0x3FF0000 |
| MMCM user clock register 2 clock output 0 fractional mask. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_REG2_CLKOUT0_FRAC_SHIFT 16 |
| MMCM user clock register 2 clock output 0 fractional shift. More... | |
| #define | XHDMIPHY1_MMCM_USRCLK_REG34_DIVCLK_MASK 0x00000FF |
| MMCM user clock register 3/4 divider clock mask. More... | |
| #define | XHDMIPHY1_BUFGGT_XXUSRCLK_CLR_MASK 0x1 |
| BUFGGT user clock clear mask. More... | |
| #define | XHDMIPHY1_BUFGGT_XXUSRCLK_DIV_MASK 0xE |
| BUFGGT user clock divider mask. More... | |
| #define | XHDMIPHY1_BUFGGT_XXUSRCLK_DIV_SHIFT 1 |
| BUFGGT user clock divider shift. More... | |
| #define | XHDMIPHY1_MISC_XXUSRCLK_CKOUT1_OEN_MASK 0x1 |
| Miscellaneous user clock output 1 output enable mask. More... | |
| #define | XHDMIPHY1_MISC_XXUSRCLK_REFCLK_CEB_MASK 0x2 |
| Miscellaneous user clock reference clock CEB (Clock Enable Bar) mask. More... | |
| #define | XHDMIPHY1_CLKDET_CTRL_RUN_MASK 0x1 |
| Clock detector control run mask. More... | |
| #define | XHDMIPHY1_CLKDET_CTRL_TX_TMR_CLR_MASK 0x2 |
| Clock detector control TX timer clear mask. More... | |
| #define | XHDMIPHY1_CLKDET_CTRL_RX_TMR_CLR_MASK 0x4 |
| Clock detector control RX timer clear mask. More... | |
| #define | XHDMIPHY1_CLKDET_CTRL_TX_FREQ_RST_MASK 0x8 |
| Clock detector control TX frequency reset mask. More... | |
| #define | XHDMIPHY1_CLKDET_CTRL_RX_FREQ_RST_MASK 0x10 |
| Clock detector control RX frequency reset mask. More... | |
| #define | XHDMIPHY1_CLKDET_CTRL_FREQ_LOCK_THRESH_MASK 0x1FE0 |
| Clock detector control frequency lock threshold mask. More... | |
| #define | XHDMIPHY1_CLKDET_CTRL_FREQ_LOCK_THRESH_SHIFT 5 |
| Clock detector control frequency lock threshold shift. More... | |
| #define | XHDMIPHY1_CLKDET_CTRL_ACCURACY_RANGE_MASK 0x1E000 |
| Clock detector control accuracy range mask. More... | |
| #define | XHDMIPHY1_CLKDET_CTRL_ACCURACY_RANGE_SHIFT 13 |
| Clock detector control accuracy range shift. More... | |
| #define | XHDMIPHY1_CLKDET_STAT_TX_FREQ_ZERO_MASK 0x1 |
| Clock detector status TX frequency zero mask. More... | |
| #define | XHDMIPHY1_CLKDET_STAT_RX_FREQ_ZERO_MASK 0x2 |
| Clock detector status RX frequency zero mask. More... | |
| #define | XHDMIPHY1_CLKDET_STAT_TX_REFCLK_LOCK_MASK 0x3 |
| Clock detector status TX reference clock lock mask. More... | |
| #define | XHDMIPHY1_CLKDET_STAT_TX_REFCLK_LOCK_CAP_MASK 0x4 |
| Clock detector status TX reference clock lock capture mask. More... | |
| #define | XHDMIPHY1_DRU_CTRL_RST_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| DRU control reset mask for specific channel. More... | |
| #define | XHDMIPHY1_DRU_CTRL_EN_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| DRU control enable mask for specific channel. More... | |
| #define | XHDMIPHY1_DRU_STAT_ACTIVE_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| DRU status active mask for specific channel. More... | |
| #define | XHDMIPHY1_DRU_STAT_VERSION_MASK 0xFF000000 |
| DRU status version mask. More... | |
| #define | XHDMIPHY1_DRU_STAT_VERSION_SHIFT 24 |
| DRU status version shift. More... | |
| #define | XHDMIPHY1_DRU_CFREQ_H_MASK 0x1F |
| DRU center frequency high mask. More... | |
| #define | XHDMIPHY1_DRU_GAIN_G1_MASK 0x00001F |
| DRU gain G1 mask. More... | |
| #define | XHDMIPHY1_DRU_GAIN_G1_SHIFT 0 |
| DRU gain G1 shift. More... | |
| #define | XHDMIPHY1_DRU_GAIN_G1_P_MASK 0x001F00 |
| DRU gain G1 P mask. More... | |
| #define | XHDMIPHY1_DRU_GAIN_G1_P_SHIFT 8 |
| DRU gain G1 P shift. More... | |
| #define | XHDMIPHY1_DRU_GAIN_G2_MASK 0x1F0000 |
| DRU gain G2 mask. More... | |
| #define | XHDMIPHY1_DRU_GAIN_G2_SHIFT 16 |
| DRU gain G2 shift. More... | |
| #define | XHDMIPHY1_PATGEN_CTRL_ENABLE_MASK 0x80000000 |
| PATGEN control enable mask. More... | |
| #define | XHDMIPHY1_PATGEN_CTRL_ENABLE_SHIFT 31 |
| PATGEN control enable shift. More... | |
| #define | XHDMIPHY1_PATGEN_CTRL_RATIO_MASK 0x7 |
| PATGEN control ratio mask. More... | |
| #define | XHDMIPHY1_PATGEN_CTRL_RATIO_SHIFT 0 |
| PATGEN control ratio shift. More... | |
| #define | XHdmiphy1_ReadReg(BaseAddress, RegOffset) XHdmiphy1_In32((BaseAddress) + (RegOffset)) |
| This is a low-level function that reads from the specified register. More... | |
| #define | XHdmiphy1_WriteReg(BaseAddress, RegOffset, Data) XHdmiphy1_Out32((BaseAddress) + (RegOffset), (Data)) |
| This is a low-level function that writes to the specified register. More... | |
HDMIPHY core registers: General registers. | |
Address mapping for the Video PHY core. | |
| #define | XHDMIPHY1_VERSION_REG 0x000 |
| Version register. More... | |
| #define | XHDMIPHY1_BANK_SELECT_REG 0x00C |
| Bank select register. More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_REG 0x010 |
| Reference clock select register. More... | |
| #define | XHDMIPHY1_PLL_RESET_REG 0x014 |
| PLL reset register. More... | |
| #define | XHDMIPHY1_COMMON_INIT_REG 0x014 |
| Common initialization register. More... | |
| #define | XHDMIPHY1_PLL_LOCK_STATUS_REG 0x018 |
| PLL lock status register. More... | |
| #define | XHDMIPHY1_TX_INIT_REG 0x01C |
| Transmitter initialization register. More... | |
| #define | XHDMIPHY1_TX_INIT_STATUS_REG 0x020 |
| Transmitter initialization status register. More... | |
| #define | XHDMIPHY1_RX_INIT_REG 0x024 |
| Receiver initialization register. More... | |
| #define | XHDMIPHY1_RX_INIT_STATUS_REG 0x028 |
| Receiver initialization status register. More... | |
| #define | XHDMIPHY1_IBUFDS_GTXX_CTRL_REG 0x02C |
| IBUFDS GT control register. More... | |
| #define | XHDMIPHY1_POWERDOWN_CONTROL_REG 0x030 |
| Power down control register. More... | |
| #define | XHDMIPHY1_LOOPBACK_CONTROL_REG 0x038 |
| Loopback control register. More... | |
HDMIPHY core registers: Dynamic reconfiguration port (DRP) registers. | |
| #define | XHDMIPHY1_DRP_CONTROL_CH1_REG 0x040 |
| DRP control register for channel 1 (0x040) More... | |
| #define | XHDMIPHY1_DRP_CONTROL_CH2_REG 0x044 |
| DRP control register for channel 2 (0x044) More... | |
| #define | XHDMIPHY1_DRP_CONTROL_CH3_REG 0x048 |
| DRP control register for channel 3 (0x048) More... | |
| #define | XHDMIPHY1_DRP_CONTROL_CH4_REG 0x04C |
| DRP control register for channel 4 (0x04C) More... | |
| #define | XHDMIPHY1_DRP_STATUS_CH1_REG 0x050 |
| DRP status register for channel 1 (0x050) More... | |
| #define | XHDMIPHY1_DRP_STATUS_CH2_REG 0x054 |
| DRP status register for channel 2 (0x054) More... | |
| #define | XHDMIPHY1_DRP_STATUS_CH3_REG 0x058 |
| DRP status register for channel 3 (0x058) More... | |
| #define | XHDMIPHY1_DRP_STATUS_CH4_REG 0x05C |
| DRP status register for channel 4 (0x05C) More... | |
| #define | XHDMIPHY1_DRP_CONTROL_COMMON_REG 0x060 |
| DRP control register for common (0x060) More... | |
| #define | XHDMIPHY1_DRP_STATUS_COMMON_REG 0x064 |
| DRP status register for common (0x064) More... | |
| #define | XHDMIPHY1_DRP_CONTROL_TXMMCM_REG 0x124 |
| DRP control register for TX MMCM (0x124) More... | |
| #define | XHDMIPHY1_DRP_STATUS_TXMMCM_REG 0x128 |
| DRP status register for TX MMCM (0x128) More... | |
| #define | XHDMIPHY1_DRP_CONTROL_RXMMCM_REG 0x144 |
| DRP control register for RX MMCM (0x144) More... | |
| #define | XHDMIPHY1_DRP_STATUS_RXMMCM_REG 0x148 |
| DRP status register for RX MMCM (0x148) More... | |
HDMIPHY core registers: CPLL Calibration registers. | |
| #define | XHDMIPHY1_CPLL_CAL_PERIOD_REG 0x068 |
| CPLL calibration period register (0x068) More... | |
| #define | XHDMIPHY1_CPLL_CAL_TOL_REG 0x06C |
| CPLL calibration tolerance register (0x06C) More... | |
HDMIPHY core registers: GT Debug INTF registers. | |
| #define | XHDMIPHY1_GT_DBG_GPI_REG 0x068 |
| GT debug GPI register (0x068) More... | |
| #define | XHDMIPHY1_GT_DBG_GPO_REG 0x06C |
| GT debug GPO register (0x06C) More... | |
HDMIPHY core registers: Transmitter function registers. | |
| #define | XHDMIPHY1_TX_CONTROL_REG 0x070 |
| TX control register (0x070) More... | |
| #define | XHDMIPHY1_TX_BUFFER_BYPASS_REG 0x074 |
| TX buffer bypass register (0x074) More... | |
| #define | XHDMIPHY1_TX_STATUS_REG 0x078 |
| TX status register (0x078) More... | |
| #define | XHDMIPHY1_TX_DRIVER_CH12_REG 0x07C |
| TX driver register for channels 1 and 2 (0x07C) More... | |
| #define | XHDMIPHY1_TX_DRIVER_CH34_REG 0x080 |
| TX driver register for channels 3 and 4 (0x080) More... | |
| #define | XHDMIPHY1_TX_DRIVER_EXT_REG 0x084 |
| TX driver extended register (0x084) More... | |
| #define | XHDMIPHY1_TX_RATE_CH12_REG 0x08C |
| TX rate register for channels 1 and 2 (0x08C) More... | |
| #define | XHDMIPHY1_TX_RATE_CH34_REG 0x090 |
| TX rate register for channels 3 and 4 (0x090) More... | |
HDMIPHY core registers: Receiver function registers. | |
| #define | XHDMIPHY1_RX_RATE_CH12_REG 0x98 |
| RX rate register for channels 1 and 2 (0x98) More... | |
| #define | XHDMIPHY1_RX_RATE_CH34_REG 0x9C |
| RX rate register for channels 3 and 4 (0x9C) More... | |
| #define | XHDMIPHY1_RX_CONTROL_REG 0x100 |
| RX control register (0x100) More... | |
| #define | XHDMIPHY1_RX_STATUS_REG 0x104 |
| RX status register (0x104) More... | |
| #define | XHDMIPHY1_RX_EQ_CDR_REG 0x108 |
| RX equalization and CDR register (0x108) More... | |
| #define | XHDMIPHY1_RX_TDLOCK_REG 0x10C |
| RX TDLOCK register (0x10C) More... | |
HDMIPHY core registers: Interrupt registers. | |
| #define | XHDMIPHY1_INTR_EN_REG 0x110 |
| Interrupt enable register (0x110) More... | |
| #define | XHDMIPHY1_INTR_DIS_REG 0x114 |
| Interrupt disable register (0x114) More... | |
| #define | XHDMIPHY1_INTR_MASK_REG 0x118 |
| Interrupt mask register (0x118) More... | |
| #define | XHDMIPHY1_INTR_STS_REG 0x11C |
| Interrupt status register (0x11C) More... | |
User clocking registers: MMCM and BUFGGT registers. | |
| #define | XHDMIPHY1_MMCM_TXUSRCLK_CTRL_REG 0x0120 |
| MMCM TX user clock control register (0x0120) More... | |
| #define | XHDMIPHY1_MMCM_TXUSRCLK_REG1 0x0124 |
| MMCM TX user clock register 1 (0x0124) More... | |
| #define | XHDMIPHY1_MMCM_TXUSRCLK_REG2 0x0128 |
| MMCM TX user clock register 2 (0x0128) More... | |
| #define | XHDMIPHY1_MMCM_TXUSRCLK_REG3 0x012C |
| MMCM TX user clock register 3 (0x012C) More... | |
| #define | XHDMIPHY1_MMCM_TXUSRCLK_REG4 0x0130 |
| MMCM TX user clock register 4 (0x0130) More... | |
| #define | XHDMIPHY1_BUFGGT_TXUSRCLK_REG 0x0134 |
| BUFGGT TX user clock register (0x0134) More... | |
| #define | XHDMIPHY1_MISC_TXUSRCLK_REG 0x0138 |
| Miscellaneous TX user clock register (0x0138) More... | |
| #define | XHDMIPHY1_MMCM_RXUSRCLK_CTRL_REG 0x0140 |
| MMCM RX user clock control register (0x0140) More... | |
| #define | XHDMIPHY1_MMCM_RXUSRCLK_REG1 0x0144 |
| MMCM RX user clock register 1 (0x0144) More... | |
| #define | XHDMIPHY1_MMCM_RXUSRCLK_REG2 0x0148 |
| MMCM RX user clock register 2 (0x0148) More... | |
| #define | XHDMIPHY1_MMCM_RXUSRCLK_REG3 0x014C |
| MMCM RX user clock register 3 (0x014C) More... | |
| #define | XHDMIPHY1_MMCM_RXUSRCLK_REG4 0x0150 |
| MMCM RX user clock register 4 (0x0150) More... | |
| #define | XHDMIPHY1_BUFGGT_RXUSRCLK_REG 0x0154 |
| BUFGGT RX user clock register (0x0154) More... | |
| #define | XHDMIPHY1_MISC_RXUSRCLK_REG 0x0158 |
| Miscellaneous RX user clock register (0x0158) More... | |
Clock detector (HDMI) registers. | |
| #define | XHDMIPHY1_CLKDET_CTRL_REG 0x0200 |
| Clock detector control register (0x0200) More... | |
| #define | XHDMIPHY1_CLKDET_STAT_REG 0x0204 |
| Clock detector status register (0x0204) More... | |
| #define | XHDMIPHY1_CLKDET_FREQ_TMR_TO_REG 0x0208 |
| Clock detector frequency timer timeout register (0x0208) More... | |
| #define | XHDMIPHY1_CLKDET_FREQ_TX_REG 0x020C |
| Clock detector TX frequency register (0x020C) More... | |
| #define | XHDMIPHY1_CLKDET_FREQ_RX_REG 0x0210 |
| Clock detector RX frequency register (0x0210) More... | |
| #define | XHDMIPHY1_CLKDET_TMR_TX_REG 0x0214 |
| Clock detector TX timer register (0x0214) More... | |
| #define | XHDMIPHY1_CLKDET_TMR_RX_REG 0x0218 |
| Clock detector RX timer register (0x0218) More... | |
| #define | XHDMIPHY1_CLKDET_FREQ_DRU_REG 0x021C |
| Clock detector DRU frequency register (0x021C) More... | |
| #define | XHDMIPHY1_CLKDET_FREQ_TX_FRL_REG 0x0230 |
| Clock detector TX FRL frequency register (0x0230) More... | |
| #define | XHDMIPHY1_CLKDET_FREQ_RX_FRL_REG 0x0234 |
| Clock detector RX FRL frequency register (0x0234) More... | |
Data recovery unit registers (HDMI). | |
| #define | XHDMIPHY1_DRU_CTRL_REG 0x0300 |
| DRU control register (0x0300) More... | |
| #define | XHDMIPHY1_DRU_STAT_REG 0x0304 |
| DRU status register (0x0304) More... | |
| #define | XHDMIPHY1_DRU_CFREQ_L_REG(Ch) (0x0308 + (12 * (Ch - 1))) |
| DRU Center Frequency Lower register address calculation. More... | |
| #define | XHDMIPHY1_DRU_CFREQ_H_REG(Ch) (0x030C + (12 * (Ch - 1))) |
| DRU Center Frequency Higher register address calculation. More... | |
| #define | XHDMIPHY1_DRU_GAIN_REG(Ch) (0x0310 + (12 * (Ch - 1))) |
| DRU Gain register address calculation. More... | |
TMDS Clock Pattern Generator registers (HDMI). | |
| #define | XHDMIPHY1_PATGEN_CTRL_REG 0x0340 |
| PATGEN control register (0x0340) More... | |
HDMIPHY core masks, shifts, and register values. | |
| #define | XHDMIPHY1_VERSION_INTER_REV_MASK 0x000000FF |
| Internal revision. More... | |
| #define | XHDMIPHY1_VERSION_CORE_PATCH_MASK 0x00000F00 |
| Core patch details. More... | |
| #define | XHDMIPHY1_VERSION_CORE_PATCH_SHIFT 8 |
| Shift bits for core patch details. More... | |
| #define | XHDMIPHY1_VERSION_CORE_VER_REV_MASK 0x0000F000 |
| Core version revision. More... | |
| #define | XHDMIPHY1_VERSION_CORE_VER_REV_SHIFT 12 |
| Shift bits for core version revision. More... | |
| #define | XHDMIPHY1_VERSION_CORE_VER_MNR_MASK 0x00FF0000 |
| Core minor version. More... | |
| #define | XHDMIPHY1_VERSION_CORE_VER_MNR_SHIFT 16 |
| Shift bits for core minor version. More... | |
| #define | XHDMIPHY1_VERSION_CORE_VER_MJR_MASK 0xFF000000 |
| Core major version. More... | |
| #define | XHDMIPHY1_VERSION_CORE_VER_MJR_SHIFT 24 |
| Shift bits for core major version. More... | |
| #define | XHDMIPHY1_BANK_SELECT_TX_MASK 0x00F |
| TX bank select mask (0x00F) More... | |
| #define | XHDMIPHY1_BANK_SELECT_RX_MASK 0xF00 |
| RX bank select mask (0xF00) More... | |
| #define | XHDMIPHY1_BANK_SELECT_RX_SHIFT 8 |
| RX bank select shift (8) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_QPLL0_MASK 0x0000000F |
| QPLL0 reference clock select mask (0x0000000F) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_CPLL_MASK 0x000000F0 |
| CPLL reference clock select mask (0x000000F0) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_CPLL_SHIFT 4 |
| CPLL reference clock select shift (4) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_QPLL1_MASK 0x00000F00 |
| QPLL1 reference clock select mask (0x00000F00) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_QPLL1_SHIFT 8 |
| QPLL1 reference clock select shift (8) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTREFCLK0 1 |
| GT reference clock 0 selection value (1) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTREFCLK1 2 |
| GT reference clock 1 selection value (2) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTNORTHREFCLK0 3 |
| GT north reference clock 0 selection value (3) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTNORTHREFCLK1 4 |
| GT north reference clock 1 selection value (4) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTSOUTHREFCLK0 5 |
| GT south reference clock 0 selection value (5) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTSOUTHREFCLK1 6 |
| GT south reference clock 1 selection value (6) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTEASTREFCLK0 3 |
| GT east reference clock 0 selection value (3) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTEASTREFCLK1 4 |
| GT east reference clock 1 selection value (4) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTWESTREFCLK0 5 |
| GT west reference clock 0 selection value (5) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTWESTREFCLK1 6 |
| GT west reference clock 1 selection value (6) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XPLL_GTGREFCLK 7 |
| GT global reference clock selection value (7) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_SYSCLKSEL_MASK 0x0F000000 |
| System clock select mask (0x0F000000) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_SYSCLKSEL_SHIFT 24 |
| System clock select shift (24) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL0 0 |
| System clock data PLL0 selection value (0) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_PLL1 1 |
| System clock data PLL1 selection value (1) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_CPLL 0 |
| System clock data CPLL selection value (0) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL 1 |
| System clock data QPLL selection value (1) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL0 3 |
| System clock data QPLL0 selection value (3) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_DATA_QPLL1 2 |
| System clock data QPLL1 selection value (2) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CH 0 |
| System clock output channel selection value (0) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN 1 |
| System clock output common selection value (1) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN0 2 |
| System clock output common 0 selection value (2) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_XXSYSCLKSEL_OUT_CMN1 3 |
| System clock output common 1 selection value (3) More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_OUT_MASK(G) |
| RX System Clock Select Output mask based on GT type. More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_OUT_MASK(G) |
| TX System Clock Select Output mask based on GT type. More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_DATA_MASK(G) |
| RX System Clock Select Data mask based on GT type. More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_DATA_MASK(G) |
| TX System Clock Select Data mask based on GT type. More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_OUT_SHIFT(G) |
| RX System Clock Select Output shift based on GT type. More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_OUT_SHIFT(G) |
| TX System Clock Select Output shift based on GT type. More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_RXSYSCLKSEL_DATA_SHIFT(G) |
| RX System Clock Select Data shift based on GT type. More... | |
| #define | XHDMIPHY1_REF_CLK_SEL_TXSYSCLKSEL_DATA_SHIFT(G) |
| TX System Clock Select Data shift based on GT type. More... | |
| #define | XHDMIPHY1_PLL_RESET_CPLL_MASK 0x1 |
| CPLL reset mask (0x1) More... | |
| #define | XHDMIPHY1_PLL_RESET_QPLL0_MASK 0x2 |
| QPLL0 reset mask (0x2) More... | |
| #define | XHDMIPHY1_PLL_RESET_QPLL1_MASK 0x4 |
| QPLL1 reset mask (0x4) More... | |
| #define | XHDMIPHY1_GTWIZ_RESET_ALL_MASK 0x1 |
| GT wizard reset all mask (0x1) More... | |
| #define | XHDMIPHY1_PCIERST_ALL_CH_MASK 0x2 |
| PCIe reset all channels mask (0x2) More... | |
| #define | XHDMIPHY1_PLL_LOCK_STATUS_CPLL_MASK(Ch) (0x01 << (Ch - 1)) |
| CPLL lock status mask for specific channel. More... | |
| #define | XHDMIPHY1_PLL_LOCK_STATUS_QPLL0_MASK 0x10 |
| QPLL0 lock status mask (0x10) More... | |
| #define | XHDMIPHY1_PLL_LOCK_STATUS_QPLL1_MASK 0x20 |
| QPLL1 lock status mask (0x20) More... | |
| #define | XHDMIPHY1_PLL_LOCK_STATUS_CPLL_ALL_MASK |
| CPLL lock status mask for all channels. More... | |
| #define | XHDMIPHY1_PLL_LOCK_STATUS_CPLL_HDMI_MASK |
| CPLL lock status mask for HDMI channels (1-3) More... | |
| #define | XHDMIPHY1_PLL_LOCK_STATUS_RPLL_MASK 0xC0 |
| RPLL lock status mask (0xC0) More... | |
| #define | XHDMIPHY1_PLL_LOCK_STATUS_LCPLL_MASK 0x300 |
| LCPLL lock status mask (0x300) More... | |
| #define | XHDMIPHY1_TXRX_INIT_GTRESET_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| GT reset mask for specific channel. More... | |
| #define | XHDMIPHY1_TXRX_INIT_PMARESET_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| PMA reset mask for specific channel. More... | |
| #define | XHDMIPHY1_TXRX_INIT_PCSRESET_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| PCS reset mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_INIT_USERRDY_MASK(Ch) (0x08 << (8 * (Ch - 1))) |
| TX user ready mask for specific channel. More... | |
| #define | XHDMIPHY1_TXRX_LNKRDY_SB_MASK(Ch) (0x10 << (8 * (Ch - 1))) |
| Link ready sideband mask for specific channel. More... | |
| #define | XHDMIPHY1_TXRX_MSTRESET_MASK(Ch) (0x20 << (8 * (Ch - 1))) |
| Master reset mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_INIT_USERRDY_MASK(Ch) (0x40 << (8 * (Ch - 1))) |
| RX user ready mask for specific channel. More... | |
| #define | XHDMIPHY1_TXRX_INIT_PLLGTRESET_MASK(Ch) (0x80 << (8 * (Ch - 1))) |
| PLL GT reset mask for specific channel. More... | |
| #define | XHDMIPHY1_TXRX_INIT_GTRESET_ALL_MASK |
| GT reset mask for all channels. More... | |
| #define | XHDMIPHY1_TXRX_LNKRDY_SB_ALL_MASK |
| Link ready sideband mask for all channels. More... | |
| #define | XHDMIPHY1_TXRX_MSTRESET_ALL_MASK |
| Master reset mask for all channels. More... | |
| #define | XHDMIPHY1_TX_INIT_USERRDY_ALL_MASK |
| TX User Ready initialization mask for all channels. More... | |
| #define | XHDMIPHY1_RX_INIT_USERRDY_ALL_MASK |
| RX User Ready initialization mask for all channels. More... | |
| #define | XHDMIPHY1_TXRX_INIT_PLLGTRESET_ALL_MASK |
| TX/RX PLL GT reset initialization mask for all channels. More... | |
| #define | XHDMIPHY1_TXRX_INIT_STATUS_RESETDONE_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| TX/RX initialization status reset done mask for specific channel. More... | |
| #define | XHDMIPHY1_TXRX_INIT_STATUS_PMARESETDONE_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| TX/RX initialization status PMA reset done mask for specific channel. More... | |
| #define | XHDMIPHY1_TXRX_INIT_STATUS_POWERGOOD_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| TX/RX initialization status power good mask for specific channel. More... | |
| #define | XHDMIPHY1_TXRX_INIT_STATUS_RESETDONE_ALL_MASK |
| TX/RX initialization status reset done mask for all channels. More... | |
| #define | XHDMIPHY1_TXRX_INIT_STATUS_PMARESETDONE_ALL_MASK |
| TX/RX initialization status PMA reset done mask for all channels. More... | |
| #define | XHDMIPHY1_IBUFDS_GTXX_CTRL_GTREFCLK0_CEB_MASK 0x1 |
| IBUFDS GT reference clock 0 CEB (Clock Enable Bar) control mask. More... | |
| #define | XHDMIPHY1_IBUFDS_GTXX_CTRL_GTREFCLK1_CEB_MASK 0x2 |
| IBUFDS GT reference clock 1 CEB (Clock Enable Bar) control mask. More... | |
| #define | XHDMIPHY1_POWERDOWN_CONTROL_CPLLPD_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| CPLL power down mask for specific channel. More... | |
| #define | XHDMIPHY1_POWERDOWN_CONTROL_QPLL0PD_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| QPLL0 power down mask for specific channel. More... | |
| #define | XHDMIPHY1_POWERDOWN_CONTROL_QPLL1PD_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| QPLL1 power down mask for specific channel. More... | |
| #define | XHDMIPHY1_POWERDOWN_CONTROL_RXPD_MASK(Ch) (0x18 << (8 * (Ch - 1))) |
| RX power down mask for specific channel. More... | |
| #define | XHDMIPHY1_POWERDOWN_CONTROL_RXPD_SHIFT(Ch) (3 + (8 * (Ch - 1))) |
| RX power down shift for specific channel. More... | |
| #define | XHDMIPHY1_POWERDOWN_CONTROL_TXPD_MASK(Ch) (0x60 << (8 * (Ch - 1))) |
| TX power down mask for specific channel. More... | |
| #define | XHDMIPHY1_POWERDOWN_CONTROL_TXPD_SHIFT(Ch) (5 + (8 * (Ch - 1))) |
| TX power down shift for specific channel. More... | |
| #define | XHDMIPHY1_LOOPBACK_CONTROL_CH_MASK(Ch) (0x03 << (8 * (Ch - 1))) |
| Loopback control channel mask for specific channel. More... | |
| #define | XHDMIPHY1_LOOPBACK_CONTROL_CH_SHIFT(Ch) (8 * (Ch - 1)) |
| Loopback control channel shift for specific channel. More... | |
| #define | XHDMIPHY1_DRP_CONTROL_DRPADDR_MASK 0x00000FFF |
| DRP control address mask. More... | |
| #define | XHDMIPHY1_DRP_CONTROL_DRPEN_MASK 0x00001000 |
| DRP control enable mask. More... | |
| #define | XHDMIPHY1_DRP_CONTROL_DRPWE_MASK 0x00002000 |
| DRP control write enable mask. More... | |
| #define | XHDMIPHY1_DRP_CONTROL_DRPRESET_MASK 0x00004000 |
| DRP control reset mask. More... | |
| #define | XHDMIPHY1_DRP_CONTROL_DRPDI_MASK 0xFFFF0000 |
| DRP control data input mask. More... | |
| #define | XHDMIPHY1_DRP_CONTROL_DRPDI_SHIFT 16 |
| DRP control data input shift. More... | |
| #define | XHDMIPHY1_DRP_STATUS_DRPO_MASK 0x0FFFF |
| DRP status data output mask. More... | |
| #define | XHDMIPHY1_DRP_STATUS_DRPRDY_MASK 0x10000 |
| DRP status ready mask. More... | |
| #define | XHDMIPHY1_DRP_STATUS_DRPBUSY_MASK 0x20000 |
| DRP status busy mask. More... | |
| #define | XHDMIPHY1_CPLL_CAL_PERIOD_MASK 0x3FFFF |
| CPLL calibration period mask. More... | |
| #define | XHDMIPHY1_CPLL_CAL_TOL_MASK 0x3FFFF |
| CPLL calibration tolerance mask. More... | |
| #define | XHDMIPHY1_TX_GPI_MASK(Ch) (0x01 << (Ch - 1)) |
| TX GPI mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_GPI_MASK(Ch) (0x10 << (Ch - 1)) |
| RX GPI mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_GPO_MASK(Ch) (0x01 << (Ch - 1)) |
| TX GPO mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_GPO_MASK_ALL(NCh) ((NCh == 3) ? 0x7 : 0xF) |
| TX GPO mask for all channels based on number of channels. More... | |
| #define | XHDMIPHY1_TX_GPO_SHIFT 0 |
| #define | XHDMIPHY1_RX_GPO_MASK(Ch) (0x10 << (Ch - 1)) |
| RX GPO mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_GPO_MASK_ALL(NCh) ((NCh == 3) ? 0x70 : 0xF0) |
| RX GPO mask for all channels based on number of channels. More... | |
| #define | XHDMIPHY1_RX_GPO_SHIFT 4 |
| RX GPO bit shift offset. More... | |
| #define | XHDMIPHY1_TX_CONTROL_TX8B10BEN_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| TX 8B/10B enable mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_CONTROL_TX8B10BEN_ALL_MASK |
| TX 8B/10B enable mask for all channels. More... | |
| #define | XHDMIPHY1_TX_CONTROL_TXPOLARITY_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| TX polarity mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_CONTROL_TXPOLARITY_ALL_MASK |
| TX polarity mask for all channels. More... | |
| #define | XHDMIPHY1_TX_CONTROL_TXPRBSSEL_MASK(Ch) (0x5C << (8 * (Ch - 1))) |
| TX PRBS select mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_CONTROL_TXPRBSSEL_ALL_MASK |
| TX PRBS select mask for all channels. More... | |
| #define | XHDMIPHY1_TX_CONTROL_TXPRBSSEL_SHIFT(Ch) (2 + (8 * (Ch - 1))) |
| TX PRBS select shift for specific channel. More... | |
| #define | XHDMIPHY1_TX_CONTROL_TXPRBSFORCEERR_MASK(Ch) (0x20 << (8 * (Ch - 1))) |
| TX PRBS force error mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_CONTROL_TXPRBSFORCEERR_ALL_MASK |
| TX PRBS force error mask for all channels. More... | |
| #define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHDLYRESET_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| TX phase delay reset mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHALIGN_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| TX phase align mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHALIGNEN_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| TX phase align enable mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHDLYPD_MASK(Ch) (0x08 << (8 * (Ch - 1))) |
| TX phase delay power down mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_BUFFER_BYPASS_TXPHINIT_MASK(Ch) (0x10 << (8 * (Ch - 1))) |
| TX phase initialize mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_BUFFER_BYPASS_TXDLYRESET_MASK(Ch) (0x20 << (8 * (Ch - 1))) |
| TX delay reset mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_BUFFER_BYPASS_TXDLYBYPASS_MASK(Ch) (0x40 << (8 * (Ch - 1))) |
| TX delay bypass mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_BUFFER_BYPASS_TXDLYEN_MASK(Ch) (0x80 << (8 * (Ch - 1))) |
| TX delay enable mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_STATUS_TXPHALIGNDONE_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| TX phase align done mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_STATUS_TXPHINITDONE_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| TX phase initialize done mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_STATUS_TXDLYRESETDONE_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| TX delay reset done mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_STATUS_TXBUFSTATUS_MASK(Ch) (0x18 << (8 * (Ch - 1))) |
| TX buffer status mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_STATUS_TXBUFSTATUS_SHIFT(Ch) (3 + (8 * (Ch - 1))) |
| TX buffer status shift for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXDIFFCTRL_MASK(Ch) (0x000F << (16 * ((Ch - 1) % 2))) |
| TX differential control mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXDIFFCTRL_SHIFT(Ch) (16 * ((Ch - 1) % 2)) |
| TX differential control shift for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXELECIDLE_MASK(Ch) (0x0010 << (16 * ((Ch - 1) % 2))) |
| TX electrical idle mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXELECIDLE_SHIFT(Ch) (4 + (16 * ((Ch - 1) % 2))) |
| TX electrical idle shift for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXINHIBIT_MASK(Ch) (0x0020 << (16 * ((Ch - 1) % 2))) |
| TX inhibit mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXINHIBIT_SHIFT(Ch) (5 + (16 * ((Ch - 1) % 2))) |
| TX inhibit shift for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXPOSTCURSOR_MASK(Ch) (0x07C0 << (16 * ((Ch - 1) % 2))) |
| TX post-cursor mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXPOSTCURSOR_SHIFT(Ch) (6 + (16 * ((Ch - 1) % 2))) |
| TX post-cursor shift for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXPRECURSOR_MASK(Ch) (0xF800 << (16 * ((Ch - 1) % 2))) |
| TX pre-cursor mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_TXPRECURSOR_SHIFT(Ch) (11 + (16 * ((Ch - 1) % 2))) |
| TX pre-cursor shift for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_EXT_TXDIFFCTRL_MASK(Ch) (0x0001 << (8 * (Ch - 1))) |
| TX extended differential control mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_DRIVER_EXT_TXDIFFCTRL_SHIFT(Ch) (8 * (Ch - 1)) |
| TX extended differential control shift for specific channel. More... | |
| #define | XHDMIPHY1_TX_RATE_MASK(Ch) (0x00FF << (16 * ((Ch - 1) % 2))) |
| TX rate mask for specific channel. More... | |
| #define | XHDMIPHY1_TX_RATE_SHIFT(Ch) (16 * ((Ch - 1) % 2)) |
| TX rate shift for specific channel. More... | |
| #define | XHDMIPHY1_RX_RATE_MASK(Ch) (0x00FF << (16 * ((Ch - 1) % 2))) |
| RX rate mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_RATE_SHIFT(Ch) (16 * ((Ch - 1) % 2)) |
| RX rate shift for specific channel. More... | |
| #define | XHDMIPHY1_RX_CONTROL_RX8B10BEN_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| RX 8B/10B enable mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_CONTROL_RX8B10BEN_ALL_MASK |
| RX 8B/10B enable mask for all channels. More... | |
| #define | XHDMIPHY1_RX_CONTROL_RXPOLARITY_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| RX polarity mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_CONTROL_RXPOLARITY_ALL_MASK |
| RX polarity mask for all channels. More... | |
| #define | XHDMIPHY1_RX_CONTROL_RXPRBSCNTRESET_MASK(Ch) (0x08 << (8 * (Ch - 1))) |
| RX PRBS counter reset mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_CONTROL_RXPRBSSEL_MASK(Ch) (0xF0 << (8 * (Ch - 1))) |
| RX PRBS select mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_CONTROL_RXPRBSSEL_ALL_MASK |
| RX PRBS select mask for all channels. More... | |
| #define | XHDMIPHY1_RX_CONTROL_RXPRBSSEL_SHIFT(Ch) (4 + (8 * (Ch - 1))) |
| RX PRBS select shift for specific channel. More... | |
| #define | XHDMIPHY1_RX_STATUS_RXCDRLOCK_MASK(Ch) (0x1 << (8 * (Ch - 1))) |
| RX CDR lock mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_STATUS_RXBUFSTATUS_MASK(Ch) (0xE << (8 * (Ch - 1))) |
| RX buffer status mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_STATUS_RXBUFSTATUS_SHIFT(Ch) (1 + (8 * (Ch - 1))) |
| RX buffer status shift for specific channel. More... | |
RX Equalizer and CDR control masks | |
| #define | XHDMIPHY1_RX_CONTROL_RXLPMEN_MASK(Ch) (0x01 << (8 * (Ch - 1))) |
| RX LPM enable mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_STATUS_RXCDRHOLD_MASK(Ch) (0x02 << (8 * (Ch - 1))) |
| RX CDR hold mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_STATUS_RXOSOVRDEN_MASK(Ch) (0x04 << (8 * (Ch - 1))) |
| RX OS override enable mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_STATUS_RXLPMLFKLOVRDEN_MASK(Ch) (0x08 << (8 * (Ch - 1))) |
| RX LPM LFK override enable mask for specific channel. More... | |
| #define | XHDMIPHY1_RX_STATUS_RXLPMHFOVRDEN_MASK(Ch) (0x10 << (8 * (Ch - 1))) |
| RX LPM HF override enable mask for specific channel. More... | |
Register access macro definitions. | |
| #define | XHdmiphy1_In32 Xil_In32 |
| Read 32-bit value from register. More... | |
| #define | XHdmiphy1_Out32 Xil_Out32 |
| Write 32-bit value to register. More... | |
| #define XHdmiphy1_In32 Xil_In32 |
Read 32-bit value from register.
This macro provides a wrapper for reading 32-bit values from memory-mapped registers. It maps to the Xilinx library function Xil_In32.
| Addr | Memory address to read from. |
| #define XHdmiphy1_Out32 Xil_Out32 |
Write 32-bit value to register.
This macro provides a wrapper for writing 32-bit values to memory-mapped registers. It maps to the Xilinx library function Xil_Out32.
| Addr | Memory address to write to. |
| Data | 32-bit value to write to the specified address. |
| #define XHdmiphy1_ReadReg | ( | BaseAddress, | |
| RegOffset | |||
| ) | XHdmiphy1_In32((BaseAddress) + (RegOffset)) |
This is a low-level function that reads from the specified register.
| BaseAddress | is the base address of the device. |
| RegOffset | is the register offset to be read from. |
Referenced by XHdmiphy1_ClkDetAccuracyRange(), XHdmiphy1_ClkDetCheckFreqZero(), XHdmiphy1_ClkDetEnable(), XHdmiphy1_ClkDetFreqReset(), XHdmiphy1_ClkDetGetRefClkFreqHz(), XHdmiphy1_ClkDetSetFreqLockThreshold(), XHdmiphy1_ClkDetTimerClear(), XHdmiphy1_Clkout1OBufTdsEnable(), XHdmiphy1_DruEnable(), XHdmiphy1_DruGetRefClkFreqHz(), XHdmiphy1_DruGetVersion(), XHdmiphy1_DruReset(), XHdmiphy1_GetSysClkDataSel(), XHdmiphy1_GetSysClkOutSel(), XHdmiphy1_GetVersion(), XHdmiphy1_GtUserRdyEnable(), XHdmiphy1_HdmiDebugInfo(), XHdmiphy1_HdmiGtDruModeEnable(), XHdmiphy1_HdmiGtRxResetDoneLockHandler(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), XHdmiphy1_IBufDsEnable(), XHdmiphy1_InterruptHandler(), XHdmiphy1_IntrDisable(), XHdmiphy1_IntrEnable(), XHdmiphy1_IsPllLocked(), XHdmiphy1_MmcmLocked(), XHdmiphy1_MmcmLockedMaskEnable(), XHdmiphy1_MmcmPowerDown(), XHdmiphy1_MmcmReset(), XHdmiphy1_MmcmSetClkinsel(), XHdmiphy1_PatgenEnable(), XHdmiphy1_PatgenSetRatio(), XHdmiphy1_PowerDownGtPll(), XHdmiphy1_RegisterDebug(), XHdmiphy1_ResetGtPll(), XHdmiphy1_ResetGtTxRx(), XHdmiphy1_SelfTest(), XHdmiphy1_SetBufgGtDiv(), XHdmiphy1_SetPolarity(), XHdmiphy1_SetPrbsSel(), XHdmiphy1_SetRxLpm(), XHdmiphy1_SetTxPostCursor(), XHdmiphy1_SetTxPreEmphasis(), XHdmiphy1_SetTxVoltageSwing(), XHdmiphy1_TxAlignReset(), XHdmiphy1_TxAlignStart(), and XHdmiphy1_TxPrbsForceError().
| #define XHdmiphy1_WriteReg | ( | BaseAddress, | |
| RegOffset, | |||
| Data | |||
| ) | XHdmiphy1_Out32((BaseAddress) + (RegOffset), (Data)) |
This is a low-level function that writes to the specified register.
| BaseAddress | is the base address of the device. |
| RegOffset | is the register offset to write to. |
| Data | is the 32-bit data to write to the specified register. |
Referenced by XHdmiphy1_ClkDetAccuracyRange(), XHdmiphy1_ClkDetEnable(), XHdmiphy1_ClkDetFreqReset(), XHdmiphy1_ClkDetSetFreqLockThreshold(), XHdmiphy1_ClkDetSetFreqTimeout(), XHdmiphy1_ClkDetTimerClear(), XHdmiphy1_ClkDetTimerLoad(), XHdmiphy1_Clkout1OBufTdsEnable(), XHdmiphy1_DruEnable(), XHdmiphy1_DruReset(), XHdmiphy1_DruSetCenterFreqHz(), XHdmiphy1_GtUserRdyEnable(), XHdmiphy1_Hdmi_CfgInitialize(), XHdmiphy1_HdmiGtDruModeEnable(), XHdmiphy1_HdmiGtRxResetDoneLockHandler(), XHdmiphy1_HdmiGtTxResetDoneLockHandler(), XHdmiphy1_HdmiRxClkDetFreqChangeHandler(), XHdmiphy1_HdmiTxClkDetFreqChangeHandler(), XHdmiphy1_IBufDsEnable(), XHdmiphy1_IntrDisable(), XHdmiphy1_IntrEnable(), XHdmiphy1_MmcmLockedMaskEnable(), XHdmiphy1_MmcmPowerDown(), XHdmiphy1_MmcmReset(), XHdmiphy1_MmcmSetClkinsel(), XHdmiphy1_PatgenEnable(), XHdmiphy1_PatgenSetRatio(), XHdmiphy1_PowerDownGtPll(), XHdmiphy1_ResetGtPll(), XHdmiphy1_ResetGtTxRx(), XHdmiphy1_SetBufgGtDiv(), XHdmiphy1_SetPolarity(), XHdmiphy1_SetPrbsSel(), XHdmiphy1_SetRxLpm(), XHdmiphy1_SetTxPostCursor(), XHdmiphy1_SetTxPreEmphasis(), XHdmiphy1_SetTxVoltageSwing(), XHdmiphy1_TxAlignReset(), XHdmiphy1_TxAlignStart(), XHdmiphy1_TxPrbsForceError(), and XHdmiphy1_WriteCfgRefClkSelReg().