Kria™ KR260 Robotics Starter Kit Tutorial
Using Vivado to Build the Hardware Design
Using Vivado to Build the Hardware Design¶
This tutorial shows how to build the hardware design for applications running on KR260 Robotics AI Starter Kit.
AMD Vivado Design Suite™ of the appropiate version
TSN Subsytem IP evaluation license when building the kr260_tsn_rs485pmod platform
Info: To request TSN Subsystem IP evaluation license, send an email to firstname.lastname@example.org.
Accessing the Tutorial Reference Files¶
Note: Skip the following steps if the design files have already been cloned and extracted to a working repository.
To access the reference files, type the following into a terminal:
git clone --branch xlnx_rel_v2022.1 --recursive https://github.com/Xilinx/kria-vitis-platforms.git
Navigate to the
kria-vitis-platforms/kr260, which is the working directory.
Generating an Extensible XSA¶
Go to the platform directory specific to the application.
Applications and their corresponding platform names are listed in the following table.
|ROS 2 Multi-Node Communications via TSN||kr260_tsn_rs485pmod|
|Precision time Management with Digilent PMOD GPS||kr260_pmod_gps|
To build the XSA, source an AMD Vivado™ and run the following command. The Makefile uses the scripts/main.tcl file to create a Vivado project, populate the block design and finally build a XSA. The XSA generation may take some time depending on the system specification.
The generated XSA is located at:
Note: The steps under Modifying the Vivado design and creating a new XSA are optional and are required only if you need to change the platform design.
Modifying the Vivado design and creating a new XSA¶
Go to the directory specific to the platform design.
To open the Vivado project, first open the Vivado GUI, then run the following command from the Vivado tcl console:
In the Flow Navigator pane on the left-hand side under IP integrator, click on Open Block Design. An IP integrator block design becomes visible that contains the Processing System (PS) IP and other PL IPs.
To view the Platform interfaces that are enabled for the AMD Vitis™ compiler to stitch in accelerators, click on Window > Platform Setup on the tool bar at the top. Platform interfaces that are enabled are:
Clocks: To drive clock inputs on the accelerator.
Master AXI: AXI memory-mapped master ports on the Interconnect IP to drive the accelerator’s control port.
Slave AXI: AXI memory-mapped slave ports driven by the accelerator’s read/write data ports.
Interrupts: interrupt controller for the accelerator to drive interrupt signals.
You can now modify the block design and validate it (tool bar at the top: Tools → Validate design). Then click on Run Synthesis to complete the synthesis.
To write out a new extensible platform XSA file, run the following command from the Vivado tcl console:
write_hw_platform -force -file <platform_name>.xsa
The generated XSA or the modified XSA file can now be used to create a Vitis Platform.