Kria™ K260 SOM Starter Kit NLP SmartVision Tutorial
Hardware Architecture of the Accelerator
Hardware Architecture of the Accelerator¶
Preprocessing IPs and DPU¶
The Vitis™ software platform overlay includes DPU, as shown in the following figure.
The DPU IP can be configured, and for this design, the following features should be enabled:
Relu, LeakyRelu and Relu6
To learn more about the DPU, please refer the PG338
As shown in the following table, we integrate the DPU in the nlp_smartvision platform. We analysis the utilization and do some optimizations of the whole hardware design.
|Resource usage of current design (estimated)|
As shown in the following table, we estimated DPU performance and overall power on K26 chip (including all the other IPs). The DPU is assumed to run at 300MHz.
|DPU performance and power (estimated)|
|TOPS (Peak)||TOPS (DenseBox)1||Power (Overall)2|
We use DenseBox_640x360 model to estimate the real performance of DPU, and this model has 1.1GOPs;
We can only estimate the overall power of K26 (including DPU and other IPs)
As shown in Table 3, DPU B3136 bandwidth requirements.
|Table 3 – DPU B3136 bandwidth requirements|
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