| addModelProperty(uint32_t prop) | xilinx::AIE::AIETargetModel | inline |
| AIETargetModel(TargetModelKind k) | xilinx::AIE::AIETargetModel | inline |
| columns() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getAccumulatorCascadeSize() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getAddressGenGranularity() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getColumnShift() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getDmaBdAddress(int col, int row, uint32_t bd_id, int channel=-1, AIE::DMAChannelDir direction=AIE::DMAChannelDir::MM2S) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getDmaBdAddressOffset(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getDmaControlAddress(int col, int row, int channel, AIE::DMAChannelDir direction) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getKind() const | xilinx::AIE::AIETargetModel | inline |
| getLocalLockAddress(uint32_t lockId, TileID tile) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getLocalMemorySize() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getLockLocalBaseIndex(int localCol, int localRow, int lockCol, int lockRow) const | xilinx::AIE::AIETargetModel | |
| getMaxChannelNumForAdjacentMemTile(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMaxLockValue() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemEast(TileID src) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemEastBaseAddress() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemInternalBaseAddress(TileID src) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemLocalBaseAddress(int localCol, int localRow, int memCol, int memRow) const | xilinx::AIE::AIETargetModel | |
| getMemNorth(TileID src) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemNorthBaseAddress() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemSouth(TileID src) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemSouthBaseAddress() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemTileSize() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemWest(TileID src) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getMemWestBaseAddress() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getModelProperties() const | xilinx::AIE::AIETargetModel | inline |
| getNumBanks(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getNumBDs(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getNumDestShimMuxConnections(int col, int row, WireBundle bundle) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getNumDestSwitchboxConnections(int col, int row, WireBundle bundle) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getNumLocks(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getNumMemTileRows() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getNumSourceShimMuxConnections(int col, int row, WireBundle bundle) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getNumSourceSwitchboxConnections(int col, int row, WireBundle bundle) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getRowShift() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getShimBurstEncodingsAndLengths() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getTargetArch() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| hasProperty(ModelProperty Prop) const | xilinx::AIE::AIETargetModel | inline |
| isBdChannelAccessible(int col, int row, uint32_t bd_id, int channel) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isCoreTile(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isEast(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| isInternal(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| isLegalMemAffinity(int coreCol, int coreRow, int memCol, int memRow) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isLegalTileConnection(int col, int row, WireBundle srcBundle, int srcChan, WireBundle dstBundle, int dstChan) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isMemEast(int srcCol, int srcRow, int dstCol, int dstRow) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isMemNorth(int srcCol, int srcRow, int dstCol, int dstRow) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isMemSouth(int srcCol, int srcRow, int dstCol, int dstRow) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isMemTile(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isMemWest(int srcCol, int srcRow, int dstCol, int dstRow) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isNorth(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| IsNPU enum value | xilinx::AIE::AIETargetModel | |
| isShimNOCorPLTile(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isShimNOCTile(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isShimPLTile(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| isSouth(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| isSupportedBlockFormat(std::string const &format) const | xilinx::AIE::AIETargetModel | virtual |
| isValidTile(TileID src) const | xilinx::AIE::AIETargetModel | inlinevirtual |
| IsVirtualized enum value | xilinx::AIE::AIETargetModel | |
| isWest(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| ModelProperty enum name | xilinx::AIE::AIETargetModel | |
| rows() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| TargetModelKind enum name | xilinx::AIE::AIETargetModel | |
| TK_AIE1_Last enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE1_VC1902 enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_Last enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_1Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_2Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_3Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_4Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_Last enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2 enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_1Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_2Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_3Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_4Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_5Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_6Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_7Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_Last enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_VE2302 enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_VE2802 enum value | xilinx::AIE::AIETargetModel | |
| UsesMultiDimensionalBDs enum value | xilinx::AIE::AIETargetModel | |
| UsesSemaphoreLocks enum value | xilinx::AIE::AIETargetModel | |
| validate() const | xilinx::AIE::AIETargetModel | |
| ~AIETargetModel() | xilinx::AIE::AIETargetModel | virtual |
