MLIR-AIE
Classes | Typedefs | Enumerations | Functions | Variables
xilinx::AIE Namespace Reference

Include the generated interface declarations. More...

Classes

class  Address
 
class  AIE1TargetModel
 
class  AIE2TargetModel
 
struct  AIEOpRemoval
 
struct  AIEPathfinderPass
 Overall Flow: rewrite switchboxes to assign unassigned connections, ensure this can be done concurrently ( by different threads) More...
 
struct  AIERTControl
 
class  AIETargetModel
 
class  BaseNPU1TargetModel
 
class  BaseNPU2TargetModel
 
struct  BDInfo
 
class  DynamicTileAnalysis
 
class  Field
 
struct  HasValidBDs
 
struct  HasValidDMAChannels
 
struct  MERegDMABD
 
struct  MyOffsetSizeAndStrideOpInterface
 
struct  MyOffsetSizeAndStrideOpInterfaceTrait
 
class  NPU2TargetModel
 
class  Pathfinder
 
struct  RegDMAMM2S
 
struct  RegDMAS2MM
 
class  Router
 
class  Section
 
struct  ShimDMABD
 
struct  ShimDMAllocationGetter
 
struct  SkipAccessibilityCheckTrait
 
class  TileAddress
 
class  VC1902TargetModel
 
class  VE2302TargetModel
 
class  VE2802TargetModel
 
class  VirtualizedNPU1TargetModel
 
class  VirtualizedNPU2TargetModel
 

Typedefs

using Port = Port { WireBundle bundle
 
using Connect = Connect { Port src
 
using DMAChannel = DMAChannel { DMAChannelDir direction
 
using TileID = TileID { friend std::ostream &operator<<(std::ostream &os, const TileID &s) { os<< "TileID("<< s.col<< ", "<< s.row<< ")"
 
using SwitchboxConnect = SwitchboxConnect { SwitchboxConnect()=default
 
using PathEndPoint = PathEndPoint { PathEndPoint()=default
 
using Flow = Flow { int packetGroupId
 
using SwitchSetting = SwitchSetting { SwitchSetting()=default
 
using SwitchSettings = std::map< TileID, SwitchSetting >
 
using DMABDRegBlock = MERegDMABD[ME_DMA_BD_COUNT]
 
using DMAS2MMRegBlock = RegDMAS2MM[DMA_S2MM_CHANNEL_COUNT]
 
using DMAMM2SRegBlock = RegDMAMM2S[DMA_MM2S_CHANNEL_COUNT]
 
using MESSMasterBlock = uint32_t[ME_SS_MASTER_COUNT]
 
using MESSSlaveCfgBlock = uint32_t[ME_SS_SLAVE_CFG_COUNT]
 
using MESSSlaveSlotBlock = uint32_t[ME_SS_SLAVE_SLOT_COUNT][SS_SLOT_NUM_PORTS]
 
using ShimDMABDBlock = ShimDMABD[SHIM_DMA_BD_COUNT]
 
using ShimSSMasterBlock = uint32_t[SHIM_SS_MASTER_COUNT]
 
using ShimSSSlaveCfgBlock = uint32_t[SHIM_SS_SLAVE_CFG_COUNT]
 
using ShimSSSlaveSlotBlock = uint32_t[SHIM_SS_SLAVE_SLOT_COUNT]
 
using Write = std::pair< uint64_t, uint32_t >
 

Enumerations

enum class  Connectivity { INVALID = 0 , AVAILABLE = 1 }
 
enum  {
  SEC_IDX_NULL , SEC_IDX_SSMAST , SEC_IDX_SSSLVE , SEC_IDX_SSPCKT ,
  SEC_IDX_SDMA_BD , SEC_IDX_SHMMUX , SEC_IDX_SDMA_CTL , SEC_IDX_PRGM_MEM ,
  SEC_IDX_TDMA_BD , SEC_IDX_TDMA_CTL , SEC_IDX_DEPRECATED , SEC_IDX_DATA_MEM ,
  SEC_IDX_MAX
}
 

Functions

std::unique_ptr< mlir::OperationPass< xilinx::AIE::DeviceOp > > createConvertAIEToTransactionPass ()
 
std::unique_ptr< mlir::OperationPass< xilinx::AIE::DeviceOp > > createConvertAIEToControlPacketsPass ()
 
std::optional< mlir::ModuleOp > convertTransactionBinaryToMLIR (mlir::MLIRContext *ctx, std::vector< uint8_t > &binary)
 
uint32_t getShimBurstLengthBytes (const AIE::AIETargetModel &tm, uint32_t burstLength)
 
uint32_t getShimBurstLengthEncoding (const AIE::AIETargetModel &tm, uint32_t burstLength)
 
mlir::LogicalResult verifyOffsetSizeAndStrideOp (mlir::OffsetSizeAndStrideOpInterface op)
 
mlir::LogicalResult myVerifyOffsetSizeAndStrideOp (mlir::OffsetSizeAndStrideOpInterface op)
 
void registerAIETranslations ()
 
WireBundle getConnectingBundle (WireBundle dir)
 
bool operator== (const Port &rhs) const
 
bool operator!= (const Port &rhs) const
 
bool operator< (const Port &rhs) const
 
std::ostream & operator<< (std::ostream &os, const Port &port)
 
llvm::raw_ostream & operator<< (llvm::raw_ostream &os, const Port &port)
 
bool operator== (const Connect &rhs) const
 
bool operator== (const DMAChannel &rhs) const
 
const AIETargetModel & getTargetModel (mlir::Operation *op)
 
const AIETargetModel & getTargetModel (AIEDevice device)
 
mlir::ParseResult parseObjectFifoProducerTile (mlir::OpAsmParser &parser, mlir::OpAsmParser::UnresolvedOperand &operand, BDDimLayoutArrayAttr &dimensions)
 
void printObjectFifoProducerTile (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::Value tile, BDDimLayoutArrayAttr dimensions)
 
mlir::ParseResult parseObjectFifoConsumerTiles (mlir::OpAsmParser &parser, llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &tiles, BDDimLayoutArrayArrayAttr &dimensions)
 
void printObjectFifoConsumerTiles (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::OperandRange tiles, BDDimLayoutArrayArrayAttr dimensions)
 
int32_t getBufferBaseAddress (mlir::Operation *bufOp)
 
std::string to_string (const TileID &s)
 
llvm::raw_ostream & operator<< (llvm::raw_ostream &os, const TileID &s)
 
bool operator< (const TileID &rhs) const
 
bool operator== (const TileID &rhs) const
 
bool operator!= (const TileID &rhs) const
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEAssignBufferAddressesPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEAssignLockIDsPass ()
 
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > createAIECanonicalizeDevicePass ()
 
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > createAIECoreToStandardPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEFindFlowsPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIELocalizeLocksPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIENormalizeAddressSpacesPass ()
 
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > createAIERouteFlowsPass ()
 
std::unique_ptr< mlir::OperationPass< mlir::func::FuncOp > > createAIEVectorOptPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEPathfinderPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoStatefulTransformPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoRegisterProcessPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIELowerCascadeFlowsPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEAssignBufferDescriptorIDsPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEGenerateColumnControlOverlayPass ()
 
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEAssignTileCtrlIDsPass ()
 
 SwitchboxConnect (TileID coords)
 
 SwitchboxConnect (TileID srcCoords, TileID dstCoords)
 
void resize ()
 
void updateDemand ()
 
void bumpDemand (size_t i, size_t j)
 
 PathEndPoint (TileID coords, Port port)
 
std::ostream & operator<< (std::ostream &os, const PathEndPoint &s)
 
llvm::raw_ostream & operator<< (llvm::raw_ostream &os, const PathEndPoint &s)
 
bool operator< (const PathEndPoint &rhs) const
 
bool operator== (const PathEndPoint &rhs) const
 
 SwitchSetting (std::vector< Port > srcs)
 
 SwitchSetting (std::vector< Port > srcs, std::vector< Port > dsts)
 
std::ostream & operator<< (std::ostream &os, const SwitchSetting &setting)
 
llvm::raw_ostream & operator<< (llvm::raw_ostream &os, const SwitchSetting &s)
 
bool operator< (const SwitchSetting &rhs) const
 
int getWireBundleAsInt (WireBundle bundle)
 
mlir::LogicalResult AIETranslateToXAIEV2 (mlir::ModuleOp module, llvm::raw_ostream &output)
 
mlir::LogicalResult AIETranslateToHSA (mlir::ModuleOp module, llvm::raw_ostream &output)
 
mlir::LogicalResult AIEFlowsToJSON (mlir::ModuleOp module, llvm::raw_ostream &output)
 
mlir::LogicalResult ADFGenerateCPPGraph (mlir::ModuleOp module, llvm::raw_ostream &output)
 
mlir::LogicalResult AIETranslateSCSimConfig (mlir::ModuleOp module, llvm::raw_ostream &output)
 
mlir::LogicalResult AIETranslateShimSolution (mlir::ModuleOp module, llvm::raw_ostream &)
 
mlir::LogicalResult AIETranslateGraphXPE (mlir::ModuleOp module, llvm::raw_ostream &)
 
mlir::LogicalResult AIETranslateNpuToBinary (mlir::ModuleOp, std::vector< uint32_t > &, llvm::StringRef sequenceName="")
 
mlir::LogicalResult AIETranslateControlPacketsToUI32Vec (mlir::ModuleOp, std::vector< uint32_t > &, llvm::StringRef sequenceName="")
 
mlir::LogicalResult AIETranslateToLdScript (mlir::ModuleOp module, llvm::raw_ostream &output, int tileCol, int tileRow)
 
mlir::LogicalResult AIETranslateToBCF (mlir::ModuleOp module, llvm::raw_ostream &output, int tileCol, int tileRow)
 
mlir::LogicalResult AIELLVMLink (llvm::raw_ostream &output, std::vector< std::string > Files, bool DisableDITypeMap=false, bool NoVerify=false, bool Internalize=false, bool OnlyNeeded=false, bool PreserveAssemblyUseListOrder=false, bool Verbose=false)
 
mlir::LogicalResult AIETranslateToCDODirect (mlir::ModuleOp m, llvm::StringRef workDirPath, bool bigEndian=false, bool emitUnified=false, bool cdoDebug=false, bool aieSim=false, bool xaieDebug=false, bool enableCores=true)
 
mlir::LogicalResult AIETranslateToTargetArch (mlir::ModuleOp module, llvm::raw_ostream &output)
 
std::string tileLocStr (llvm::StringRef col, llvm::StringRef row)
 
std::string tileLocStr (int col, int row)
 
std::string tileDMAInstStr (llvm::StringRef col, llvm::StringRef row, llvm::StringRef bdNum)
 
std::string tileDMAInstStr (int col, int row, int bdNum)
 
std::string tileDMAInstRefStr (llvm::StringRef col, llvm::StringRef row, llvm::StringRef bdNum)
 
std::string tileDMAInstRefStr (int col, int row, int bdNum)
 
std::string packetStr (llvm::StringRef id, llvm::StringRef type)
 
std::string packetStr (int id, int type)
 
void generateXAieDmaSetMultiDimAddr (llvm::raw_ostream &output, int ndims, llvm::ArrayRef< BDDimLayoutAttr > dims, int col, int row, int bdNum, int baseAddrA, int offsetA, int lenA, int elementWidthInBytes, const char *errorRet)
 
llvm::SetVector< mlir::Block * > getOrderedChainOfBlocks (mlir::Region *region)
 
TileID getNextCoords (int col, int row, WireBundle bundle)
 
void translateSwitchboxes (DeviceOp targetOp, raw_ostream &output)
 
void translateCircuitFlows (DeviceOp targetOp, int &flowCount, raw_ostream &output)
 
void translatePacketFlows (DeviceOp targetOp, int &flowCount, raw_ostream &output)
 
mlir::LogicalResult AIEFlowsToJSON (ModuleOp module, raw_ostream &output)
 
Elf_Data * sectionAddData (Elf_Scn *scn, const Section *section)
 
mlir::LogicalResult AIETranslateToAirbin (mlir::ModuleOp module, const std::string &outputFilename, const std::string &coreFilesDir, bool testAirBin)
 
LogicalResult AIETranslateToBCF (ModuleOp module, raw_ostream &output, int tileCol, int tileRow)
 
std::optional< AIE::ShimDMAAllocationOp > getAllocOpForSymbol (AIE::DeviceOp dev, StringRef sym_name)
 
mlir::LogicalResult AIETranslateToHSA (ModuleOp module, raw_ostream &output)
 
void writeBufferMap (raw_ostream &output, BufferOp buf, int offset)
 
LogicalResult AIETranslateToTargetArch (ModuleOp module, raw_ostream &output)
 
std::string tileLocStr (StringRef col, StringRef row)
 
std::string tileDMAInstStr (StringRef col, StringRef row, StringRef bdNum)
 
std::string tileDMAInstRefStr (StringRef col, StringRef row, StringRef bdNum)
 
std::string packetStr (StringRef id, StringRef type)
 
void generateXAieDmaSetMultiDimAddr (raw_ostream &output, int ndims, ArrayRef< BDDimLayoutAttr > dims, int col, int row, int bdNum, int baseAddrA, int offsetA, int lenA, int elementWidthInBytes, const char *errorRetval)
 
llvm::SetVector< Block * > getOrderedChainOfBlocks (Region *region)
 

Variables

int channel
 
Port dst
 
return os
 
int col
 
int row
 
TileID srcCoords
 
TileID dstCoords
 
std::vector< Port > srcPorts
 
std::vector< Port > dstPorts
 
std::vector< std::vector< Connectivity > > connectivity
 
std::vector< std::vector< double > > demand
 
std::vector< std::vector< int > > overCapacity
 
std::vector< std::vector< int > > usedCapacity
 
std::vector< std::vector< int > > packetFlowCount
 
std::vector< std::vector< int > > packetGroupId
 
std::vector< std::vector< bool > > isPriority
 
TileID coords
 
Port port
 
bool isPriorityFlow
 
PathEndPoint src
 
std::vector< PathEndPoint > dsts
 
std::vector< Port > srcs
 
auto regDMAAddrABD
 
auto regDMAAddrBBD
 
auto regDMA2DXBD
 
auto regDMA2DYBD
 
auto regDMAPktBD
 
auto regDMAIntStateBD
 
auto regDMACtrlBD
 
auto regDMAS2MMCtrl
 
auto regDMAS2MMQueue
 
auto regDMAMM2SCtrl
 
auto regDMAMM2SQueue
 
auto regMESSMaster
 
auto regMESSSlaveCfg
 
auto regMESSSlaveSlot
 
const char * hsa_cpp_file_header
 

Detailed Description

Include the generated interface declarations.

Typedef Documentation

◆ Connect

using xilinx::AIE::Connect = typedef Connect { Port src

Definition at line 149 of file AIEDialect.h.

◆ DMABDRegBlock

using xilinx::AIE::DMABDRegBlock = typedef MERegDMABD[ME_DMA_BD_COUNT]

Definition at line 102 of file AIETargetAirbin.cpp.

◆ DMAChannel

using xilinx::AIE::DMAChannel = typedef DMAChannel { DMAChannelDir direction

Definition at line 158 of file AIEDialect.h.

◆ DMAMM2SRegBlock

using xilinx::AIE::DMAMM2SRegBlock = typedef RegDMAMM2S[DMA_MM2S_CHANNEL_COUNT]

Definition at line 177 of file AIETargetAirbin.cpp.

◆ DMAS2MMRegBlock

using xilinx::AIE::DMAS2MMRegBlock = typedef RegDMAS2MM[DMA_S2MM_CHANNEL_COUNT]

Definition at line 151 of file AIETargetAirbin.cpp.

◆ Flow

using xilinx::AIE::Flow = typedef Flow { int packetGroupId

Definition at line 125 of file AIEPathFinder.h.

◆ MESSMasterBlock

using xilinx::AIE::MESSMasterBlock = typedef uint32_t[ME_SS_MASTER_COUNT]

Definition at line 197 of file AIETargetAirbin.cpp.

◆ MESSSlaveCfgBlock

using xilinx::AIE::MESSSlaveCfgBlock = typedef uint32_t[ME_SS_SLAVE_CFG_COUNT]

Definition at line 209 of file AIETargetAirbin.cpp.

◆ MESSSlaveSlotBlock

using xilinx::AIE::MESSSlaveSlotBlock = typedef uint32_t[ME_SS_SLAVE_SLOT_COUNT][SS_SLOT_NUM_PORTS]

Definition at line 221 of file AIETargetAirbin.cpp.

◆ PathEndPoint

using xilinx::AIE::PathEndPoint = typedef PathEndPoint { PathEndPoint() = default

Definition at line 95 of file AIEPathFinder.h.

◆ Port

using xilinx::AIE::Port = typedef Port { WireBundle bundle

Definition at line 118 of file AIEDialect.h.

◆ ShimDMABDBlock

using xilinx::AIE::ShimDMABDBlock = typedef ShimDMABD[SHIM_DMA_BD_COUNT]

Definition at line 266 of file AIETargetAirbin.cpp.

◆ ShimSSMasterBlock

using xilinx::AIE::ShimSSMasterBlock = typedef uint32_t[SHIM_SS_MASTER_COUNT]

Definition at line 280 of file AIETargetAirbin.cpp.

◆ ShimSSSlaveCfgBlock

using xilinx::AIE::ShimSSSlaveCfgBlock = typedef uint32_t[SHIM_SS_SLAVE_CFG_COUNT]

Definition at line 281 of file AIETargetAirbin.cpp.

◆ ShimSSSlaveSlotBlock

using xilinx::AIE::ShimSSSlaveSlotBlock = typedef uint32_t[SHIM_SS_SLAVE_SLOT_COUNT]

Definition at line 282 of file AIETargetAirbin.cpp.

◆ SwitchboxConnect

using xilinx::AIE::SwitchboxConnect = typedef SwitchboxConnect { SwitchboxConnect() = default

Definition at line 33 of file AIEPathFinder.h.

◆ SwitchSetting

using xilinx::AIE::SwitchSetting = typedef SwitchSetting { SwitchSetting() = default

Definition at line 135 of file AIEPathFinder.h.

◆ SwitchSettings

using xilinx::AIE::SwitchSettings = typedef std::map<TileID, SwitchSetting>

Definition at line 180 of file AIEPathFinder.h.

◆ TileID

using xilinx::AIE::TileID = typedef TileID { friend std::ostream &operator<<(std::ostream &os, const TileID &s) { os << "TileID(" << s.col << ", " << s.row << ")"

Definition at line 22 of file AIETargetModel.h.

◆ Write

using xilinx::AIE::Write = typedef std::pair<uint64_t, uint32_t>

Definition at line 361 of file AIETargetAirbin.cpp.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
SEC_IDX_NULL 
SEC_IDX_SSMAST 
SEC_IDX_SSSLVE 
SEC_IDX_SSPCKT 
SEC_IDX_SDMA_BD 
SEC_IDX_SHMMUX 
SEC_IDX_SDMA_CTL 
SEC_IDX_PRGM_MEM 
SEC_IDX_TDMA_BD 
SEC_IDX_TDMA_CTL 
SEC_IDX_DEPRECATED 
SEC_IDX_DATA_MEM 
SEC_IDX_MAX 

Definition at line 38 of file AIETargetAirbin.cpp.

◆ Connectivity

enum class xilinx::AIE::Connectivity
strong
Enumerator
INVALID 
AVAILABLE 

Definition at line 31 of file AIEPathFinder.h.

Function Documentation

◆ ADFGenerateCPPGraph()

mlir::LogicalResult xilinx::AIE::ADFGenerateCPPGraph ( mlir::ModuleOp  module,
llvm::raw_ostream &  output 
)

◆ AIEFlowsToJSON() [1/2]

mlir::LogicalResult xilinx::AIE::AIEFlowsToJSON ( mlir::ModuleOp  module,
llvm::raw_ostream &  output 
)

◆ AIEFlowsToJSON() [2/2]

mlir::LogicalResult xilinx::AIE::AIEFlowsToJSON ( ModuleOp  module,
raw_ostream &  output 
)

Definition at line 425 of file AIEFlowsToJSON.cpp.

References translateCircuitFlows(), translatePacketFlows(), and translateSwitchboxes().

◆ AIELLVMLink()

mlir::LogicalResult xilinx::AIE::AIELLVMLink ( llvm::raw_ostream &  output,
std::vector< std::string >  Files,
bool  DisableDITypeMap = false,
bool  NoVerify = false,
bool  Internalize = false,
bool  OnlyNeeded = false,
bool  PreserveAssemblyUseListOrder = false,
bool  Verbose = false 
)

Definition at line 123 of file AIELLVMLink.cpp.

References linkFiles().

Referenced by aieLLVMLink().

◆ AIETranslateControlPacketsToUI32Vec()

mlir::LogicalResult xilinx::AIE::AIETranslateControlPacketsToUI32Vec ( mlir::ModuleOp  ,
std::vector< uint32_t > &  ,
llvm::StringRef  sequenceName = "" 
)

Referenced by aieTranslateControlPacketsToUI32Vec().

◆ AIETranslateGraphXPE()

mlir::LogicalResult xilinx::AIE::AIETranslateGraphXPE ( mlir::ModuleOp  module,
llvm::raw_ostream &  output 
)

Definition at line 215 of file AIETargetSimulationFiles.cpp.

References AIETranslateGraphXPE().

Referenced by AIETranslateGraphXPE().

◆ AIETranslateNpuToBinary()

mlir::LogicalResult xilinx::AIE::AIETranslateNpuToBinary ( mlir::ModuleOp  ,
std::vector< uint32_t > &  ,
llvm::StringRef  sequenceName = "" 
)

Referenced by aieTranslateNpuToBinary().

◆ AIETranslateSCSimConfig()

mlir::LogicalResult xilinx::AIE::AIETranslateSCSimConfig ( mlir::ModuleOp  module,
llvm::raw_ostream &  output 
)

Definition at line 23 of file AIETargetSimulationFiles.cpp.

◆ AIETranslateShimSolution()

mlir::LogicalResult xilinx::AIE::AIETranslateShimSolution ( mlir::ModuleOp  module,
llvm::raw_ostream &  output 
)

Definition at line 156 of file AIETargetSimulationFiles.cpp.

References AIETranslateShimSolution().

Referenced by AIETranslateShimSolution().

◆ AIETranslateToAirbin()

mlir::LogicalResult xilinx::AIE::AIETranslateToAirbin ( mlir::ModuleOp  module,
const std::string &  outputFilename,
const std::string &  coreFilesDir,
bool  testAirBin 
)

Definition at line 1181 of file AIETargetAirbin.cpp.

◆ AIETranslateToBCF() [1/2]

mlir::LogicalResult xilinx::AIE::AIETranslateToBCF ( mlir::ModuleOp  module,
llvm::raw_ostream &  output,
int  tileCol,
int  tileRow 
)

Referenced by aieTranslateToBCF().

◆ AIETranslateToBCF() [2/2]

LogicalResult xilinx::AIE::AIETranslateToBCF ( ModuleOp  module,
raw_ostream &  output,
int  tileCol,
int  tileRow 
)

Definition at line 29 of file AIETargetBCF.cpp.

References getBufferBaseAddress(), getTargetModel(), and utohexstr().

◆ AIETranslateToCDODirect()

mlir::LogicalResult xilinx::AIE::AIETranslateToCDODirect ( mlir::ModuleOp  m,
llvm::StringRef  workDirPath,
bool  bigEndian = false,
bool  emitUnified = false,
bool  cdoDebug = false,
bool  aieSim = false,
bool  xaieDebug = false,
bool  enableCores = true 
)

Referenced by aieTranslateToCDODirect().

◆ AIETranslateToHSA() [1/2]

mlir::LogicalResult xilinx::AIE::AIETranslateToHSA ( mlir::ModuleOp  module,
llvm::raw_ostream &  output 
)

Referenced by aieTranslateToHSA().

◆ AIETranslateToHSA() [2/2]

mlir::LogicalResult xilinx::AIE::AIETranslateToHSA ( ModuleOp  module,
raw_ostream &  output 
)

Definition at line 59 of file AIETargetHSA.cpp.

References col, getAllocOpForSymbol(), and hsa_cpp_file_header.

◆ AIETranslateToLdScript()

mlir::LogicalResult xilinx::AIE::AIETranslateToLdScript ( mlir::ModuleOp  module,
llvm::raw_ostream &  output,
int  tileCol,
int  tileRow 
)

◆ AIETranslateToTargetArch() [1/2]

mlir::LogicalResult xilinx::AIE::AIETranslateToTargetArch ( mlir::ModuleOp  module,
llvm::raw_ostream &  output 
)

◆ AIETranslateToTargetArch() [2/2]

LogicalResult xilinx::AIE::AIETranslateToTargetArch ( ModuleOp  module,
raw_ostream &  output 
)

Definition at line 107 of file AIETargets.cpp.

◆ AIETranslateToXAIEV2()

mlir::LogicalResult xilinx::AIE::AIETranslateToXAIEV2 ( mlir::ModuleOp  module,
llvm::raw_ostream &  output 
)

Referenced by aieTranslateToXAIEV2().

◆ bumpDemand()

void xilinx::AIE::bumpDemand ( size_t  i,
size_t  j 
)

Definition at line 87 of file AIEPathFinder.h.

References demand, DEMAND_COEFF, isPriority, MAX_CIRCUIT_STREAM_CAPACITY, and usedCapacity.

◆ convertTransactionBinaryToMLIR()

std::optional< mlir::ModuleOp > xilinx::AIE::convertTransactionBinaryToMLIR ( mlir::MLIRContext *  ctx,
std::vector< uint8_t > &  binary 
)

Definition at line 418 of file AIEToConfiguration.cpp.

References Transaction.

Referenced by aieTranslateBinaryToTxn().

◆ createAIEAssignBufferAddressesPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignBufferAddressesPass ( )

Definition at line 529 of file AIEAssignBuffers.cpp.

◆ createAIEAssignBufferDescriptorIDsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignBufferDescriptorIDsPass ( )

Definition at line 197 of file AIEAssignBufferDescriptorIDs.cpp.

◆ createAIEAssignLockIDsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignLockIDsPass ( )

Definition at line 101 of file AIEAssignLockIDs.cpp.

◆ createAIEAssignTileCtrlIDsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignTileCtrlIDsPass ( )

Definition at line 403 of file AIEGenerateColumnControlOverlay.cpp.

◆ createAIECanonicalizeDevicePass()

std::unique_ptr< OperationPass< ModuleOp > > xilinx::AIE::createAIECanonicalizeDevicePass ( )

Definition at line 56 of file AIECanonicalizeDevice.cpp.

◆ createAIECoreToStandardPass()

std::unique_ptr< OperationPass< ModuleOp > > xilinx::AIE::createAIECoreToStandardPass ( )

Definition at line 644 of file AIECoreToStandard.cpp.

◆ createAIEFindFlowsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEFindFlowsPass ( )

Definition at line 286 of file AIEFindFlows.cpp.

◆ createAIEGenerateColumnControlOverlayPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEGenerateColumnControlOverlayPass ( )

Definition at line 408 of file AIEGenerateColumnControlOverlay.cpp.

◆ createAIELocalizeLocksPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIELocalizeLocksPass ( )

Definition at line 77 of file AIELocalizeLocks.cpp.

◆ createAIELowerCascadeFlowsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIELowerCascadeFlowsPass ( )

Definition at line 94 of file AIELowerCascadeFlows.cpp.

◆ createAIENormalizeAddressSpacesPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIENormalizeAddressSpacesPass ( )

Definition at line 74 of file AIENormalizeAddressSpaces.cpp.

◆ createAIEObjectFifoRegisterProcessPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoRegisterProcessPass ( )

Definition at line 230 of file AIEObjectFifoRegisterProcess.cpp.

◆ createAIEObjectFifoStatefulTransformPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoStatefulTransformPass ( )

Definition at line 2195 of file AIEObjectFifoStatefulTransform.cpp.

◆ createAIEPathfinderPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEPathfinderPass ( )

Definition at line 1022 of file AIECreatePathFindFlows.cpp.

◆ createAIERouteFlowsPass()

std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > xilinx::AIE::createAIERouteFlowsPass ( )

◆ createAIEVectorOptPass()

std::unique_ptr< OperationPass< func::FuncOp > > xilinx::AIE::createAIEVectorOptPass ( )

Definition at line 56 of file AIEVectorOpt.cpp.

◆ createConvertAIEToControlPacketsPass()

std::unique_ptr< mlir::OperationPass< xilinx::AIE::DeviceOp > > xilinx::AIE::createConvertAIEToControlPacketsPass ( )

Definition at line 532 of file AIEToConfiguration.cpp.

◆ createConvertAIEToTransactionPass()

std::unique_ptr< mlir::OperationPass< xilinx::AIE::DeviceOp > > xilinx::AIE::createConvertAIEToTransactionPass ( )

Definition at line 527 of file AIEToConfiguration.cpp.

◆ generateXAieDmaSetMultiDimAddr() [1/2]

void xilinx::AIE::generateXAieDmaSetMultiDimAddr ( llvm::raw_ostream &  output,
int  ndims,
llvm::ArrayRef< BDDimLayoutAttr >  dims,
int  col,
int  row,
int  bdNum,
int  baseAddrA,
int  offsetA,
int  lenA,
int  elementWidthInBytes,
const char *  errorRet 
)

◆ generateXAieDmaSetMultiDimAddr() [2/2]

void xilinx::AIE::generateXAieDmaSetMultiDimAddr ( raw_ostream &  output,
int  ndims,
ArrayRef< BDDimLayoutAttr >  dims,
int  col,
int  row,
int  bdNum,
int  baseAddrA,
int  offsetA,
int  lenA,
int  elementWidthInBytes,
const char *  errorRetval 
)

Definition at line 86 of file AIETargetShared.cpp.

References col, row, and tileDMAInstRefStr().

◆ getAllocOpForSymbol()

std::optional< AIE::ShimDMAAllocationOp > xilinx::AIE::getAllocOpForSymbol ( AIE::DeviceOp  dev,
StringRef  sym_name 
)

Definition at line 46 of file AIETargetHSA.cpp.

Referenced by AIETranslateToHSA().

◆ getBufferBaseAddress()

int32_t xilinx::AIE::getBufferBaseAddress ( mlir::Operation *  bufOp)

Referenced by AIETranslateToBCF(), and writeBufferMap().

◆ getConnectingBundle()

WireBundle xilinx::AIE::getConnectingBundle ( WireBundle  dir)

Definition at line 2207 of file AIEDialect.cpp.

Referenced by xilinx::AIE::Pathfinder::dijkstraShortestPaths(), translateCircuitFlows(), and translatePacketFlows().

◆ getNextCoords()

TileID xilinx::AIE::getNextCoords ( int  col,
int  row,
WireBundle  bundle 
)

Definition at line 34 of file AIEFlowsToJSON.cpp.

References col, and row.

Referenced by translateCircuitFlows(), and translatePacketFlows().

◆ getOrderedChainOfBlocks() [1/2]

llvm::SetVector< mlir::Block * > xilinx::AIE::getOrderedChainOfBlocks ( mlir::Region *  region)

Referenced by xilinx::AIE::AIERTControl::addInitConfig().

◆ getOrderedChainOfBlocks() [2/2]

llvm::SetVector< Block * > xilinx::AIE::getOrderedChainOfBlocks ( Region *  region)

Definition at line 136 of file AIETargetShared.cpp.

◆ getShimBurstLengthBytes()

uint32_t xilinx::AIE::getShimBurstLengthBytes ( const AIE::AIETargetModel &  tm,
uint32_t  burstLength 
)

Definition at line 160 of file AIEDialect.cpp.

Referenced by configureBdInBlock().

◆ getShimBurstLengthEncoding()

uint32_t xilinx::AIE::getShimBurstLengthEncoding ( const AIE::AIETargetModel &  tm,
uint32_t  burstLength 
)

Definition at line 166 of file AIEDialect.cpp.

◆ getTargetModel() [1/2]

const AIETargetModel & xilinx::AIE::getTargetModel ( AIEDevice  device)

Definition at line 229 of file AIEDialect.cpp.

◆ getTargetModel() [2/2]

const AIETargetModel & xilinx::AIE::getTargetModel ( mlir::Operation *  op)

Referenced by aieGetTargetModel(), AIETranslateToBCF(), basicAllocation(), DMAChannelAnalysis::getDMAChannelIndex(), AIEAssignRuntimeSequenceBDIDsPass::getGeneratorForTile(), LockAnalysis::getLockID(), xilinx::AIEX::TokenAnalysis::getShareableTileOp(), AIEObjectFifoStatefulTransformPass::isSharedMemory(), registerAIETranslations(), AIEDMATasksToNPUPass::rewriteSingleBD(), AIELocalizeLocksPass::runOnOperation(), AIEDMATasksToNPUPass::setAddressForSingleBD(), simpleBankAwareAllocation(), xilinx::AIEX::verifyStridesWraps(), and xilinx::AIE::HasValidBDs< ConcreteType >::verifyTrait().

◆ getWireBundleAsInt()

int xilinx::AIE::getWireBundleAsInt ( WireBundle  bundle)

Definition at line 697 of file AIEPathFinder.cpp.

Referenced by xilinx::AIE::Pathfinder::sortFlows().

◆ myVerifyOffsetSizeAndStrideOp()

LogicalResult xilinx::AIE::myVerifyOffsetSizeAndStrideOp ( mlir::OffsetSizeAndStrideOpInterface  op)

Definition at line 173 of file AIEDialect.cpp.

Referenced by xilinx::AIE::MyOffsetSizeAndStrideOpInterfaceTrait< ConcreteOp >::verifyTrait().

◆ operator!=() [1/2]

bool xilinx::AIE::operator!= ( const Port &  rhs) const

Definition at line 126 of file AIEDialect.h.

◆ operator!=() [2/2]

bool xilinx::AIE::operator!= ( const TileID &  rhs) const

Definition at line 50 of file AIETargetModel.h.

◆ operator<() [1/4]

bool xilinx::AIE::operator< ( const PathEndPoint &  rhs) const

Definition at line 116 of file AIEPathFinder.h.

References coords, and port.

◆ operator<() [2/4]

bool xilinx::AIE::operator< ( const Port &  rhs) const

Definition at line 128 of file AIEDialect.h.

References channel.

◆ operator<() [3/4]

bool xilinx::AIE::operator< ( const SwitchSetting &  rhs) const

Definition at line 177 of file AIEPathFinder.h.

References srcs.

◆ operator<() [4/4]

bool xilinx::AIE::operator< ( const TileID &  rhs) const
inline

Definition at line 42 of file AIETargetModel.h.

References col, and row.

◆ operator<<() [1/7]

friend llvm::raw_ostream & xilinx::AIE::operator<< ( llvm::raw_ostream &  os,
const PathEndPoint &  s 
)

Definition at line 109 of file AIEPathFinder.h.

References os, and to_string().

◆ operator<<() [2/7]

friend llvm::raw_ostream & xilinx::AIE::operator<< ( llvm::raw_ostream &  os,
const Port &  port 
)

Definition at line 141 of file AIEDialect.h.

References os, port, and to_string().

◆ operator<<() [3/7]

friend llvm::raw_ostream & xilinx::AIE::operator<< ( llvm::raw_ostream &  os,
const SwitchSetting &  s 
)

Definition at line 171 of file AIEPathFinder.h.

References os, and to_string().

◆ operator<<() [4/7]

friend llvm::raw_ostream & xilinx::AIE::operator<< ( llvm::raw_ostream &  os,
const TileID &  s 
)

Definition at line 36 of file AIETargetModel.h.

References os, and to_string().

◆ operator<<() [5/7]

friend std::ostream & xilinx::AIE::operator<< ( std::ostream &  os,
const PathEndPoint &  s 
)

Definition at line 102 of file AIEPathFinder.h.

References os.

◆ operator<<() [6/7]

friend std::ostream & xilinx::AIE::operator<< ( std::ostream &  os,
const Port &  port 
)

Definition at line 132 of file AIEDialect.h.

References os, and port.

◆ operator<<() [7/7]

friend std::ostream & xilinx::AIE::operator<< ( std::ostream &  os,
const SwitchSetting &  setting 
)

Definition at line 146 of file AIEPathFinder.h.

References os, and port.

◆ operator==() [1/5]

bool xilinx::AIE::operator== ( const Connect &  rhs) const

Definition at line 153 of file AIEDialect.h.

References dst, and src.

◆ operator==() [2/5]

bool xilinx::AIE::operator== ( const DMAChannel &  rhs) const

Definition at line 162 of file AIEDialect.h.

References channel.

◆ operator==() [3/5]

bool xilinx::AIE::operator== ( const PathEndPoint &  rhs) const

Definition at line 120 of file AIEPathFinder.h.

References coords, and port.

◆ operator==() [4/5]

bool xilinx::AIE::operator== ( const Port &  rhs) const

Definition at line 122 of file AIEDialect.h.

References channel.

◆ operator==() [5/5]

bool xilinx::AIE::operator== ( const TileID &  rhs) const

Definition at line 46 of file AIETargetModel.h.

References col, and row.

◆ packetStr() [1/3]

std::string xilinx::AIE::packetStr ( int  id,
int  type 
)

Definition at line 69 of file AIETargetShared.cpp.

References packetStr().

◆ packetStr() [2/3]

std::string xilinx::AIE::packetStr ( llvm::StringRef  id,
llvm::StringRef  type 
)

Referenced by packetStr().

◆ packetStr() [3/3]

std::string xilinx::AIE::packetStr ( StringRef  id,
StringRef  type 
)

Definition at line 62 of file AIETargetShared.cpp.

◆ parseObjectFifoConsumerTiles()

mlir::ParseResult xilinx::AIE::parseObjectFifoConsumerTiles ( mlir::OpAsmParser &  parser,
llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &  tiles,
BDDimLayoutArrayArrayAttr &  dimensions 
)

◆ parseObjectFifoProducerTile()

mlir::ParseResult xilinx::AIE::parseObjectFifoProducerTile ( mlir::OpAsmParser &  parser,
mlir::OpAsmParser::UnresolvedOperand &  operand,
BDDimLayoutArrayAttr &  dimensions 
)

◆ PathEndPoint()

xilinx::AIE::PathEndPoint ( TileID  coords,
Port  port 
)

Definition at line 97 of file AIEPathFinder.h.

◆ printObjectFifoConsumerTiles()

void xilinx::AIE::printObjectFifoConsumerTiles ( mlir::OpAsmPrinter &  printer,
mlir::Operation *  op,
mlir::OperandRange  tiles,
BDDimLayoutArrayArrayAttr  dimensions 
)

◆ printObjectFifoProducerTile()

void xilinx::AIE::printObjectFifoProducerTile ( mlir::OpAsmPrinter &  printer,
mlir::Operation *  op,
mlir::Value  tile,
BDDimLayoutArrayAttr  dimensions 
)

◆ registerAIETranslations()

void xilinx::AIE::registerAIETranslations ( )

Definition at line 120 of file AIETargets.cpp.

References getTargetModel(), and writeBufferMap().

◆ resize()

void xilinx::AIE::resize ( )

Definition at line 58 of file AIEPathFinder.h.

References connectivity, demand, dstPorts, INVALID, isPriority, overCapacity, packetFlowCount, packetGroupId, srcPorts, and usedCapacity.

◆ sectionAddData()

Elf_Data * xilinx::AIE::sectionAddData ( Elf_Scn *  scn,
const Section *  section 
)

Definition at line 1162 of file AIETargetAirbin.cpp.

◆ SwitchboxConnect() [1/2]

xilinx::AIE::SwitchboxConnect ( TileID  coords)

Definition at line 35 of file AIEPathFinder.h.

◆ SwitchboxConnect() [2/2]

xilinx::AIE::SwitchboxConnect ( TileID  srcCoords,
TileID  dstCoords 
)

Definition at line 36 of file AIEPathFinder.h.

◆ SwitchSetting() [1/2]

xilinx::AIE::SwitchSetting ( std::vector< Port >  srcs)

Definition at line 137 of file AIEPathFinder.h.

◆ SwitchSetting() [2/2]

xilinx::AIE::SwitchSetting ( std::vector< Port >  srcs,
std::vector< Port >  dsts 
)

Definition at line 138 of file AIEPathFinder.h.

◆ tileDMAInstRefStr() [1/3]

std::string xilinx::AIE::tileDMAInstRefStr ( int  col,
int  row,
int  bdNum 
)

Definition at line 57 of file AIETargetShared.cpp.

References col, row, and tileDMAInstRefStr().

◆ tileDMAInstRefStr() [2/3]

std::string xilinx::AIE::tileDMAInstRefStr ( llvm::StringRef  col,
llvm::StringRef  row,
llvm::StringRef  bdNum 
)

Referenced by generateXAieDmaSetMultiDimAddr(), and tileDMAInstRefStr().

◆ tileDMAInstRefStr() [3/3]

std::string xilinx::AIE::tileDMAInstRefStr ( StringRef  col,
StringRef  row,
StringRef  bdNum 
)

Definition at line 50 of file AIETargetShared.cpp.

References col, row, and tileDMAInstStr().

◆ tileDMAInstStr() [1/3]

std::string xilinx::AIE::tileDMAInstStr ( int  col,
int  row,
int  bdNum 
)

Definition at line 45 of file AIETargetShared.cpp.

References col, row, and tileDMAInstStr().

◆ tileDMAInstStr() [2/3]

std::string xilinx::AIE::tileDMAInstStr ( llvm::StringRef  col,
llvm::StringRef  row,
llvm::StringRef  bdNum 
)

Referenced by tileDMAInstRefStr(), and tileDMAInstStr().

◆ tileDMAInstStr() [3/3]

std::string xilinx::AIE::tileDMAInstStr ( StringRef  col,
StringRef  row,
StringRef  bdNum 
)

Definition at line 38 of file AIETargetShared.cpp.

References col, and row.

◆ tileLocStr() [1/3]

std::string xilinx::AIE::tileLocStr ( int  col,
int  row 
)

Definition at line 34 of file AIETargetShared.cpp.

References col, row, and tileLocStr().

◆ tileLocStr() [2/3]

std::string xilinx::AIE::tileLocStr ( llvm::StringRef  col,
llvm::StringRef  row 
)

Referenced by tileLocStr().

◆ tileLocStr() [3/3]

std::string xilinx::AIE::tileLocStr ( StringRef  col,
StringRef  row 
)

Definition at line 27 of file AIETargetShared.cpp.

References col, and row.

◆ to_string()

friend std::string xilinx::AIE::to_string ( const TileID &  s)

Definition at line 30 of file AIETargetModel.h.

Referenced by operator<<(), operator<<(), operator<<(), and operator<<().

◆ translateCircuitFlows()

void xilinx::AIE::translateCircuitFlows ( DeviceOp  targetOp,
int &  flowCount,
raw_ostream &  output 
)

Definition at line 156 of file AIEFlowsToJSON.cpp.

References getConnectingBundle(), and getNextCoords().

Referenced by AIEFlowsToJSON().

◆ translatePacketFlows()

void xilinx::AIE::translatePacketFlows ( DeviceOp  targetOp,
int &  flowCount,
raw_ostream &  output 
)

Definition at line 276 of file AIEFlowsToJSON.cpp.

References getConnectingBundle(), and getNextCoords().

Referenced by AIEFlowsToJSON().

◆ translateSwitchboxes()

void xilinx::AIE::translateSwitchboxes ( DeviceOp  targetOp,
raw_ostream &  output 
)

Definition at line 49 of file AIEFlowsToJSON.cpp.

References col, port, and row.

Referenced by AIEFlowsToJSON().

◆ updateDemand()

void xilinx::AIE::updateDemand ( )

Definition at line 73 of file AIEPathFinder.h.

References demand, DEMAND_BASE, dstPorts, OVER_CAPACITY_COEFF, overCapacity, srcPorts, USED_CAPACITY_COEFF, and usedCapacity.

◆ verifyOffsetSizeAndStrideOp()

mlir::LogicalResult xilinx::AIE::verifyOffsetSizeAndStrideOp ( mlir::OffsetSizeAndStrideOpInterface  op)

◆ writeBufferMap()

void xilinx::AIE::writeBufferMap ( raw_ostream &  output,
BufferOp  buf,
int  offset 
)

Definition at line 98 of file AIETargets.cpp.

References getBufferBaseAddress().

Referenced by registerAIETranslations().

Variable Documentation

◆ channel

int xilinx::AIE::channel

Definition at line 120 of file AIEDialect.h.

Referenced by xilinx::AIE::AIE1TargetModel::getDmaControlAddress(), xilinx::AIE::AIE2TargetModel::getDmaControlAddress(), xilinx::AIE::Pathfinder::initialize(), xilinx::AIE::AIE2TargetModel::isBdChannelAccessible(), operator<(), operator==(), and operator==().

◆ col

int xilinx::AIE::col

Definition at line 52 of file AIETargetModel.h.

Referenced by xilinx::AIE::AIERTControl::addAieElf(), xilinx::AIE::AIERTControl::addAieElfs(), xilinx::AIE::Pathfinder::addFixedConnection(), xilinx::AIE::AIERTControl::addInitConfig(), aieRtDmaUpdateBdAddr(), aieTranslateToBCF(), AIETranslateToHSA(), configureBdInBlock(), xilinx::AIE::AIERTControl::configureLocksAndBd(), configureLocksInBdBlock(), xilinx::AIE::AIERTControl::configureSwitches(), xilinx::AIE::AIERTControl::dmaUpdateBdAddr(), AIEObjectFifoStatefulTransformPass::findOrCreateTile(), AIEGenerateColumnControlOverlayPass::generatePacketFlowsForControl(), generateXAieDmaSetMultiDimAddr(), xilinx::AIE::AIE1TargetModel::getDmaBdAddress(), xilinx::AIE::AIE2TargetModel::getDmaBdAddress(), xilinx::AIE::AIE1TargetModel::getDmaBdAddressOffset(), xilinx::AIE::AIE2TargetModel::getDmaBdAddressOffset(), xilinx::AIE::AIE1TargetModel::getDmaControlAddress(), xilinx::AIE::AIE2TargetModel::getDmaControlAddress(), getNextCoords(), xilinx::AIE::AIE2TargetModel::getNumBanks(), xilinx::AIE::AIE2TargetModel::getNumBDs(), xilinx::AIE::AIE1TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumLocks(), xilinx::AIE::AIE1TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::DynamicTileAnalysis::getShimMux(), xilinx::AIE::DynamicTileAnalysis::getSwitchbox(), xilinx::AIE::DynamicTileAnalysis::getTile(), getTileToControllerIdMap(), getTileToControllerIdMap6RowsOrLess(), xilinx::AIE::Pathfinder::initialize(), xilinx::AIE::AIE2TargetModel::isBdChannelAccessible(), xilinx::AIE::AIE1TargetModel::isLegalTileConnection(), xilinx::AIE::AIE2TargetModel::isLegalTileConnection(), xilinx::AIE::VC1902TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2302TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2802TargetModel::isShimNOCorPLTile(), xilinx::AIE::BaseNPU1TargetModel::isShimNOCorPLTile(), xilinx::AIE::BaseNPU2TargetModel::isShimNOCorPLTile(), xilinx::AIE::VC1902TargetModel::isShimNOCTile(), xilinx::AIE::VE2302TargetModel::isShimNOCTile(), xilinx::AIE::VE2802TargetModel::isShimNOCTile(), xilinx::AIE::VC1902TargetModel::isShimPLTile(), xilinx::AIE::VE2302TargetModel::isShimPLTile(), xilinx::AIE::VE2802TargetModel::isShimPLTile(), AIEBufferToStandard::matchAndRewrite(), AIECoreToStandardFunc::matchAndRewrite(), SetLockToWrite32Pattern::matchAndRewrite(), operator<(), operator==(), xilinx::AIE::AIERTControl::pushToBdQueueAndEnable(), xilinx::AIE::DynamicTileAnalysis::runAnalysis(), xilinx::AIE::AIEPathfinderPass::runOnOperation(), AIEAssignBufferDescriptorIDsPass::runOnOperation(), AIEAssignTileCtrlIDsPass::runOnOperation(), AIEGenerateColumnControlOverlayPass::runOnOperation(), AIELocalizeLocksPass::runOnOperation(), AIECtrlPacketToDmaPass::runOnOperation(), xilinx::AIE::AIEPathfinderPass::runOnPacketFlow(), tileDMAInstRefStr(), tileDMAInstRefStr(), tileDMAInstStr(), tileDMAInstStr(), tileLocStr(), tileLocStr(), and translateSwitchboxes().

◆ connectivity

std::vector<std::vector<Connectivity> > xilinx::AIE::connectivity

Definition at line 43 of file AIEPathFinder.h.

Referenced by resize().

◆ coords

TileID xilinx::AIE::coords

Definition at line 99 of file AIEPathFinder.h.

Referenced by xilinx::AIE::Pathfinder::addFixedConnection(), xilinx::AIE::Pathfinder::findPaths(), xilinx::AIE::Pathfinder::initialize(), operator<(), and operator==().

◆ demand

std::vector<std::vector<double> > xilinx::AIE::demand

Definition at line 45 of file AIEPathFinder.h.

Referenced by bumpDemand(), resize(), and updateDemand().

◆ dst

Port xilinx::AIE::dst

Definition at line 151 of file AIEDialect.h.

Referenced by xilinx::AIE::Pathfinder::addFlow(), getAvailableDestChannel(), operator==(), and AIELowerCascadeFlowsPass::runOnOperation().

◆ dstCoords

TileID xilinx::AIE::dstCoords

Definition at line 39 of file AIEPathFinder.h.

Referenced by xilinx::AIE::Pathfinder::addFlow(), and xilinx::AIE::DynamicTileAnalysis::runAnalysis().

◆ dstPorts

std::vector<Port> xilinx::AIE::dstPorts

Definition at line 41 of file AIEPathFinder.h.

Referenced by resize(), and updateDemand().

◆ dsts

std::vector< Port > xilinx::AIE::dsts

Definition at line 129 of file AIEPathFinder.h.

Referenced by xilinx::AIE::Pathfinder::addFlow(), and xilinx::AIE::Pathfinder::findPaths().

◆ hsa_cpp_file_header

const char* xilinx::AIE::hsa_cpp_file_header
Initial value:
= R"code(
// This file was auto-generated by aiecc.py --aie-generate-hsa
#ifndef MLIR_AIE_QUIET
#define __mlir_aie_verbose(x) x
#else
#define __mlir_aie_verbose(x)
#endif
)code"

Definition at line 34 of file AIETargetHSA.cpp.

Referenced by AIETranslateToHSA().

◆ isPriority

std::vector<std::vector<bool> > xilinx::AIE::isPriority

Definition at line 55 of file AIEPathFinder.h.

Referenced by bumpDemand(), xilinx::AIE::Pathfinder::findPaths(), and resize().

◆ isPriorityFlow

bool xilinx::AIE::isPriorityFlow

Definition at line 127 of file AIEPathFinder.h.

Referenced by xilinx::AIE::Pathfinder::addFlow().

◆ os

return xilinx::AIE::os

Definition at line 27 of file AIETargetModel.h.

Referenced by aieLLVMLink(), aieTranslateAIEVecToCpp(), aieTranslateModuleToLLVMIR(), aieTranslateToBCF(), aieTranslateToHSA(), aieTranslateToXAIEV2(), operator<<(), operator<<(), operator<<(), operator<<(), operator<<(), operator<<(), operator<<(), and xilinx::AIEX::TokenAnalysis::print().

◆ overCapacity

std::vector<std::vector<int> > xilinx::AIE::overCapacity

Definition at line 47 of file AIEPathFinder.h.

Referenced by resize(), and updateDemand().

◆ packetFlowCount

std::vector<std::vector<int> > xilinx::AIE::packetFlowCount

Definition at line 51 of file AIEPathFinder.h.

Referenced by resize().

◆ packetGroupId

std::vector<std::vector<int> > xilinx::AIE::packetGroupId

Definition at line 53 of file AIEPathFinder.h.

Referenced by xilinx::AIE::Pathfinder::addFlow(), xilinx::AIE::Pathfinder::findPaths(), and resize().

◆ port

Port xilinx::AIE::port

Definition at line 100 of file AIEPathFinder.h.

Referenced by AIEObjectFifoStatefulTransformPass::createUseLocks(), AIEObjectFifoStatefulTransformPass::dynamicGlobalObjectFifos(), xilinx::AIE::Pathfinder::findPaths(), getAvailableDestChannel(), ConnectivityAnalysis::getConnectedTiles(), operator<(), operator<<(), operator<<(), operator<<(), operator==(), AIEObjectFifoStatefulTransformPass::runOnOperation(), and translateSwitchboxes().

◆ regDMA2DXBD

auto xilinx::AIE::regDMA2DXBD
Initial value:
= [](auto idx) {
return reinterpret_cast<uint64_t>(&DMABdRegs[idx].x2d);
}

Definition at line 117 of file AIETargetAirbin.cpp.

◆ regDMA2DYBD

auto xilinx::AIE::regDMA2DYBD
Initial value:
= [](auto idx) {
return reinterpret_cast<uint64_t>(&DMABdRegs[idx].y2d);
}

Definition at line 121 of file AIETargetAirbin.cpp.

◆ regDMAAddrABD

auto xilinx::AIE::regDMAAddrABD
Initial value:
= [](auto idx) {
return reinterpret_cast<uint64_t>(&DMABdRegs[idx].addrA);
}

Definition at line 109 of file AIETargetAirbin.cpp.

◆ regDMAAddrBBD

auto xilinx::AIE::regDMAAddrBBD
Initial value:
= [](auto idx) {
return reinterpret_cast<uint64_t>(&DMABdRegs[idx].addrB);
}

Definition at line 113 of file AIETargetAirbin.cpp.

◆ regDMACtrlBD

auto xilinx::AIE::regDMACtrlBD
Initial value:
= [](auto idx) {
return reinterpret_cast<uint64_t>(&DMABdRegs[idx].control);
}

Definition at line 133 of file AIETargetAirbin.cpp.

◆ regDMAIntStateBD

auto xilinx::AIE::regDMAIntStateBD
Initial value:
= [](auto idx) {
return reinterpret_cast<uint64_t>(&DMABdRegs[idx].interleave);
}

Definition at line 129 of file AIETargetAirbin.cpp.

◆ regDMAMM2SCtrl

auto xilinx::AIE::regDMAMM2SCtrl
Initial value:
= [](auto ch) {
return reinterpret_cast<uint64_t>(&DMAMM2SRegs[ch].ctrl);
}

Definition at line 181 of file AIETargetAirbin.cpp.

◆ regDMAMM2SQueue

auto xilinx::AIE::regDMAMM2SQueue
Initial value:
= [](auto ch) {
return reinterpret_cast<uint64_t>(&DMAMM2SRegs[ch].queue);
}

Definition at line 185 of file AIETargetAirbin.cpp.

◆ regDMAPktBD

auto xilinx::AIE::regDMAPktBD
Initial value:
= [](auto idx) {
return reinterpret_cast<uint64_t>(&DMABdRegs[idx].packet);
}

Definition at line 125 of file AIETargetAirbin.cpp.

◆ regDMAS2MMCtrl

auto xilinx::AIE::regDMAS2MMCtrl
Initial value:
= [](auto ch) {
return reinterpret_cast<uint64_t>(&DMAS2MMRegs[ch].ctrl);
}

Definition at line 155 of file AIETargetAirbin.cpp.

◆ regDMAS2MMQueue

auto xilinx::AIE::regDMAS2MMQueue
Initial value:
= [](auto ch) {
return reinterpret_cast<uint64_t>(&DMAS2MMRegs[ch].queue);
}

Definition at line 159 of file AIETargetAirbin.cpp.

◆ regMESSMaster

auto xilinx::AIE::regMESSMaster
Initial value:
= [](auto idx) {
return reinterpret_cast<uint64_t>(&MESSMaster[idx]);
}

Definition at line 205 of file AIETargetAirbin.cpp.

◆ regMESSSlaveCfg

auto xilinx::AIE::regMESSSlaveCfg
Initial value:
= [](auto idx) {
return reinterpret_cast<uint64_t>(&MESSSlaveCfg[idx]);
}

Definition at line 217 of file AIETargetAirbin.cpp.

◆ regMESSSlaveSlot

auto xilinx::AIE::regMESSSlaveSlot
Initial value:
= [](auto port, auto slot) {
return reinterpret_cast<uint64_t>(&MESSSlaveSlot[slot][port]);
}

Definition at line 230 of file AIETargetAirbin.cpp.

◆ row

int xilinx::AIE::row

Definition at line 52 of file AIETargetModel.h.

Referenced by xilinx::AIE::AIERTControl::addAieElf(), xilinx::AIE::AIERTControl::addAieElfs(), xilinx::AIE::Pathfinder::addFixedConnection(), xilinx::AIE::AIERTControl::addInitConfig(), aieRtDmaUpdateBdAddr(), aieTranslateToBCF(), configureBdInBlock(), xilinx::AIE::AIERTControl::configureLocksAndBd(), configureLocksInBdBlock(), xilinx::AIE::AIERTControl::configureSwitches(), xilinx::AIE::AIERTControl::dmaUpdateBdAddr(), AIEObjectFifoStatefulTransformPass::findOrCreateTile(), generateXAieDmaSetMultiDimAddr(), xilinx::AIE::AIE1TargetModel::getDmaBdAddress(), xilinx::AIE::AIE2TargetModel::getDmaBdAddress(), xilinx::AIE::AIE1TargetModel::getDmaBdAddressOffset(), xilinx::AIE::AIE2TargetModel::getDmaBdAddressOffset(), xilinx::AIE::AIE1TargetModel::getDmaControlAddress(), xilinx::AIE::AIE2TargetModel::getDmaControlAddress(), getNextCoords(), xilinx::AIE::AIE2TargetModel::getNumBanks(), xilinx::AIE::AIE2TargetModel::getNumBDs(), xilinx::AIE::AIE1TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumLocks(), xilinx::AIE::AIE1TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::DynamicTileAnalysis::getShimMux(), xilinx::AIE::DynamicTileAnalysis::getSwitchbox(), xilinx::AIE::DynamicTileAnalysis::getTile(), getTileToControllerIdMap(), getTileToControllerIdMap6RowsOrLess(), xilinx::AIE::Pathfinder::initialize(), xilinx::AIE::AIE2TargetModel::isBdChannelAccessible(), xilinx::AIE::AIE1TargetModel::isCoreTile(), xilinx::AIE::VE2302TargetModel::isCoreTile(), xilinx::AIE::VE2802TargetModel::isCoreTile(), xilinx::AIE::BaseNPU1TargetModel::isCoreTile(), xilinx::AIE::BaseNPU2TargetModel::isCoreTile(), xilinx::AIE::AIE1TargetModel::isLegalTileConnection(), xilinx::AIE::AIE2TargetModel::isLegalTileConnection(), xilinx::AIE::VE2302TargetModel::isMemTile(), xilinx::AIE::VE2802TargetModel::isMemTile(), xilinx::AIE::BaseNPU1TargetModel::isMemTile(), xilinx::AIE::BaseNPU2TargetModel::isMemTile(), xilinx::AIE::VC1902TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2302TargetModel::isShimNOCorPLTile(), xilinx::AIE::VE2802TargetModel::isShimNOCorPLTile(), xilinx::AIE::BaseNPU1TargetModel::isShimNOCorPLTile(), xilinx::AIE::BaseNPU2TargetModel::isShimNOCorPLTile(), xilinx::AIE::VC1902TargetModel::isShimNOCTile(), xilinx::AIE::VE2302TargetModel::isShimNOCTile(), xilinx::AIE::VE2802TargetModel::isShimNOCTile(), xilinx::AIE::VirtualizedNPU1TargetModel::isShimNOCTile(), xilinx::AIE::BaseNPU2TargetModel::isShimNOCTile(), xilinx::AIE::VC1902TargetModel::isShimPLTile(), xilinx::AIE::VE2302TargetModel::isShimPLTile(), xilinx::AIE::VE2802TargetModel::isShimPLTile(), AIEBufferToStandard::matchAndRewrite(), AIECoreToStandardFunc::matchAndRewrite(), SetLockToWrite32Pattern::matchAndRewrite(), operator<(), operator==(), xilinx::AIE::AIERTControl::pushToBdQueueAndEnable(), xilinx::AIE::DynamicTileAnalysis::runAnalysis(), xilinx::AIE::AIEPathfinderPass::runOnOperation(), AIEAssignBufferDescriptorIDsPass::runOnOperation(), AIELocalizeLocksPass::runOnOperation(), AIECtrlPacketToDmaPass::runOnOperation(), xilinx::AIE::AIEPathfinderPass::runOnPacketFlow(), xilinx::AIE::TileAddress::TileAddress(), tileDMAInstRefStr(), tileDMAInstRefStr(), tileDMAInstStr(), tileDMAInstStr(), tileLocStr(), tileLocStr(), and translateSwitchboxes().

◆ src

PathEndPoint xilinx::AIE::src

Definition at line 128 of file AIEPathFinder.h.

Referenced by xilinx::AIE::Pathfinder::addFlow(), xilinx::AIE::Pathfinder::dijkstraShortestPaths(), xilinx::AIE::Pathfinder::findPaths(), xilinx::AIE::AIEPathfinderPass::findPathToDest(), getAvailableDestChannel(), xilinx::AIE::AIE1TargetModel::getMemEast(), xilinx::AIE::AIE2TargetModel::getMemEast(), xilinx::AIE::AIE1TargetModel::getMemInternalBaseAddress(), xilinx::AIE::AIE1TargetModel::getMemNorth(), xilinx::AIE::AIE2TargetModel::getMemNorth(), xilinx::AIE::AIE1TargetModel::getMemSouth(), xilinx::AIE::AIE2TargetModel::getMemSouth(), xilinx::AIE::AIE1TargetModel::getMemWest(), xilinx::AIE::AIE2TargetModel::getMemWest(), xilinx::AIE::AIETargetModel::isValidTile(), operator==(), AIELowerCascadeFlowsPass::runOnOperation(), and xilinx::AIE::AIEPathfinderPass::runOnPacketFlow().

◆ srcCoords

TileID xilinx::AIE::srcCoords

Definition at line 39 of file AIEPathFinder.h.

Referenced by xilinx::AIE::Pathfinder::addFlow(), xilinx::AIE::DynamicTileAnalysis::runAnalysis(), and xilinx::AIE::AIEPathfinderPass::runOnPacketFlow().

◆ srcPorts

std::vector<Port> xilinx::AIE::srcPorts

Definition at line 40 of file AIEPathFinder.h.

Referenced by resize(), and updateDemand().

◆ srcs

std::vector<Port> xilinx::AIE::srcs

Definition at line 141 of file AIEPathFinder.h.

Referenced by operator<().

◆ usedCapacity

std::vector<std::vector<int> > xilinx::AIE::usedCapacity

Definition at line 49 of file AIEPathFinder.h.

Referenced by bumpDemand(), resize(), and updateDemand().

Generated on Sat Aug 23 2025 00:55:48 for MLIR-AIE by doxygen 1.9.8