xilinx::AIE::AIETargetModel Class Reference

#include "aie/Dialect/AIE/IR/AIETargetModel.h"

Inheritance diagram for xilinx::AIE::AIETargetModel:

Public Types
enum	TargetModelKind {   TK_AIE1_VC1902 , TK_AIE1_Last , TK_AIE2_VE2302 , TK_AIE2_VE2802 ,   TK_AIE2_NPU1 , TK_AIE2_NPU1_1Col , TK_AIE2_NPU1_2Col , TK_AIE2_NPU1_3Col ,   TK_AIE2_NPU1_4Col , TK_AIE2_NPU1_Last , TK_AIE2_NPU2 = TK_AIE2_NPU1_Last , TK_AIE2_NPU2_1Col ,   TK_AIE2_NPU2_2Col , TK_AIE2_NPU2_3Col , TK_AIE2_NPU2_4Col , TK_AIE2_NPU2_5Col ,   TK_AIE2_NPU2_6Col , TK_AIE2_NPU2_7Col , TK_AIE2_NPU2_Last , TK_AIE2_Last = TK_AIE2_NPU2_Last }
enum	ModelProperty { UsesSemaphoreLocks = 1U << 0 , IsNPU = 1U << 1 , IsVirtualized = 1U << 2 , UsesMultiDimensionalBDs = 1U << 3 }

Public Member Functions
TargetModelKind	getKind () const
	AIETargetModel (TargetModelKind k)
virtual	~AIETargetModel ()
virtual AIEArch	getTargetArch () const =0
	Return the target architecture.
virtual uint32_t	getAddressGenGranularity () const =0
	Return the data bus width of the device.
virtual int	columns () const =0
	Return the number of columns in the device.
virtual int	rows () const =0
	Return the number of rows in the device.
virtual bool	isCoreTile (int col, int row) const =0
	Return true if the given tile is a 'Core' tile.
virtual bool	isMemTile (int col, int row) const =0
	Return true if the given tile is an AIE2 'Memory' tile.
virtual bool	isShimNOCTile (int col, int row) const =0
	Return true if the given tile is a Shim NOC tile.
virtual bool	isShimPLTile (int col, int row) const =0
	Return true if the given tile is a Shim PL interface tile.
virtual bool	isShimNOCorPLTile (int col, int row) const =0
	Return true if the given tile is either a Shim NOC or a Shim PL interface tile.
virtual bool	isValidTile (TileID src) const
	Return true if the given tile ID is valid.
virtual std::optional< TileID >	getMemWest (TileID src) const =0
	Return the tile ID of the memory to the west of the given tile, if it exists.
virtual std::optional< TileID >	getMemEast (TileID src) const =0
	Return the tile ID of the memory to the east of the given tile, if it exists.
virtual std::optional< TileID >	getMemNorth (TileID src) const =0
	Return the tile ID of the memory to the north of the given tile, if it exists.
virtual std::optional< TileID >	getMemSouth (TileID src) const =0
	Return the tile ID of the memory to the south of the given tile, if it exists.
bool	isInternal (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is the internal memory of dst.
bool	isWest (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is West of dst.
bool	isEast (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is East of dst.
bool	isNorth (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is North of dst.
bool	isSouth (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is South of dst.
virtual bool	isMemWest (int srcCol, int srcRow, int dstCol, int dstRow) const =0
	Return true if src has a memory tile which is West of dst.
virtual bool	isMemEast (int srcCol, int srcRow, int dstCol, int dstRow) const =0
	Return true if src has a memory tile which is East of dst.
virtual bool	isMemNorth (int srcCol, int srcRow, int dstCol, int dstRow) const =0
	Return true if src has a memory tile which is North of dst.
virtual bool	isMemSouth (int srcCol, int srcRow, int dstCol, int dstRow) const =0
	Return true if src has a memory tile which is South of dst.
virtual bool	isLegalMemAffinity (int coreCol, int coreRow, int memCol, int memRow) const =0
	Return true if core can access the memory in mem.
virtual uint32_t	getMemInternalBaseAddress (TileID src) const =0
	Return the base address in the local address map for a core.
virtual uint32_t	getMemSouthBaseAddress () const =0
	Return the base address in the local address map for a core.
virtual uint32_t	getMemWestBaseAddress () const =0
	Return the base address in the local address map for a core.
virtual uint32_t	getMemNorthBaseAddress () const =0
	Return the base address in the local address map for a core.
virtual uint32_t	getMemEastBaseAddress () const =0
	Return the base address in the local address map for a core.
std::optional< uint32_t >	getLockLocalBaseIndex (int localCol, int localRow, int lockCol, int lockRow) const
	Return the lock base index (or offset) in the local tile when accessing a neighbor's lock or an empty optional if an invalid neighbor is given Takes into account differences between Memory and Core tiles.
std::optional< uint32_t >	getMemLocalBaseAddress (int localCol, int localRow, int memCol, int memRow) const
	Return the memory base address (or offset) in the local tile when accessing a neighbor's memory or an empty optional if an invalid neighbor is given Takes into account differences between Memory and Core tiles.
virtual uint32_t	getLocalMemorySize () const =0
	Return the size (in bytes) of the local data memory of a core.
virtual uint32_t	getAccumulatorCascadeSize () const =0
	Return the size (in bits) of the accumulator/cascade.
virtual uint32_t	getNumLocks (int col, int row) const =0
	Return the number of lock objects.
virtual uint32_t	getMaxLockValue () const =0
	Return the maximum value that can be stored in a lock register.
virtual std::optional< uint32_t >	getLocalLockAddress (uint32_t lockId, TileID tile) const =0
virtual uint32_t	getNumBDs (int col, int row) const =0
	Return the number of buffer descriptors supported by the DMA in the given tile.
virtual bool	isBdChannelAccessible (int col, int row, uint32_t bd_id, int channel) const =0
	Return true iff buffer descriptor bd_id on tile (col, row) can be submitted on channel channel.
virtual uint32_t	getNumMemTileRows () const =0
virtual uint32_t	getMemTileSize () const =0
	Return the size (in bytes) of a MemTile.
virtual uint32_t	getNumBanks (int col, int row) const =0
	Return the number of memory banks of a given tile.
virtual uint32_t	getNumDestSwitchboxConnections (int col, int row, WireBundle bundle) const =0
	Return the number of destinations of connections inside a switchbox.
virtual uint32_t	getNumSourceSwitchboxConnections (int col, int row, WireBundle bundle) const =0
	Return the number of sources of connections inside a switchbox.
virtual uint32_t	getNumDestShimMuxConnections (int col, int row, WireBundle bundle) const =0
	Return the number of destinations of connections inside a shimmux.
virtual uint32_t	getNumSourceShimMuxConnections (int col, int row, WireBundle bundle) const =0
	Return the number of sources of connections inside a shimmux.
virtual bool	isLegalTileConnection (int col, int row, WireBundle srcBundle, int srcChan, WireBundle dstBundle, int dstChan) const =0
void	validate () const
uint32_t	getModelProperties () const
void	addModelProperty (uint32_t prop)
bool	hasProperty (ModelProperty Prop) const
virtual uint32_t	getColumnShift () const =0
virtual uint32_t	getRowShift () const =0
virtual std::vector< std::pair< uint32_t, uint32_t > >	getShimBurstEncodingsAndLengths () const =0

Detailed Description

Definition at line 55 of file AIETargetModel.h.

Member Enumeration Documentation

ModelProperty

enum xilinx::AIE::AIETargetModel::ModelProperty

Enumerator
UsesSemaphoreLocks
IsNPU
IsVirtualized
UsesMultiDimensionalBDs

Definition at line 82 of file AIETargetModel.h.

TargetModelKind

enum xilinx::AIE::AIETargetModel::TargetModelKind

Enumerator
TK_AIE1_VC1902
TK_AIE1_Last
TK_AIE2_VE2302
TK_AIE2_VE2802
TK_AIE2_NPU1
TK_AIE2_NPU1_1Col
TK_AIE2_NPU1_2Col
TK_AIE2_NPU1_3Col
TK_AIE2_NPU1_4Col
TK_AIE2_NPU1_Last
TK_AIE2_NPU2
TK_AIE2_NPU2_1Col
TK_AIE2_NPU2_2Col
TK_AIE2_NPU2_3Col
TK_AIE2_NPU2_4Col
TK_AIE2_NPU2_5Col
TK_AIE2_NPU2_6Col
TK_AIE2_NPU2_7Col
TK_AIE2_NPU2_Last
TK_AIE2_Last

Definition at line 58 of file AIETargetModel.h.

Constructor & Destructor Documentation

AIETargetModel()

xilinx::AIE::AIETargetModel::AIETargetModel ( TargetModelKind  k )

inline

Definition at line 103 of file AIETargetModel.h.

~AIETargetModel()

xilinx::AIE::AIETargetModel::~AIETargetModel ( )

virtualdefault

Member Function Documentation

addModelProperty()

void xilinx::AIE::AIETargetModel::addModelProperty ( uint32_t  prop )

inline

Definition at line 284 of file AIETargetModel.h.

Referenced by xilinx::AIE::AIE2TargetModel::AIE2TargetModel(), xilinx::AIE::BaseNPUTargetModel::BaseNPUTargetModel(), xilinx::AIE::VirtualizedNPU2TargetModel::VirtualizedNPU2TargetModel(), and xilinx::AIE::VirtualizedNPUTargetModel::VirtualizedNPUTargetModel().

columns()

virtual int xilinx::AIE::AIETargetModel::columns ( ) const

pure virtual

Return the number of columns in the device.

Implemented in xilinx::AIE::VC1902TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, xilinx::AIE::NPUTargetModel, xilinx::AIE::VirtualizedNPUTargetModel, xilinx::AIE::NPU2TargetModel, and xilinx::AIE::VirtualizedNPU2TargetModel.

Referenced by xilinx::AIE::AIERTControl::AIERTControl(), aieTargetModelColumns(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), getRowToShimChanMap(), getTileToControllerIdMap(), getTileToControllerIdMap6RowsOrLess(), isValidTile(), and validate().

getAccumulatorCascadeSize()

virtual uint32_t xilinx::AIE::AIETargetModel::getAccumulatorCascadeSize ( ) const

pure virtual

Return the size (in bits) of the accumulator/cascade.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

getAddressGenGranularity()

virtual uint32_t xilinx::AIE::AIETargetModel::getAddressGenGranularity ( ) const

pure virtual

Return the data bus width of the device.

Implemented in xilinx::AIE::AIE2TargetModel, xilinx::AIE::VC1902TargetModel, xilinx::AIE::VirtualizedNPUTargetModel, and xilinx::AIE::VirtualizedNPU2TargetModel.

Referenced by aieGetTargetModelAddressGenGranularity(), and xilinx::AIEX::getHardwareStridesWraps().

getColumnShift()

virtual uint32_t xilinx::AIE::AIETargetModel::getColumnShift ( ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetColumnShift(), and xilinx::AIEX::getBufferDescriptorAddressRegisterAddress().

getKind()

TargetModelKind xilinx::AIE::AIETargetModel::getKind ( ) const

inline

Definition at line 101 of file AIETargetModel.h.

Referenced by xilinx::AIE::AIE1TargetModel::classof(), xilinx::AIE::AIE2TargetModel::classof(), xilinx::AIE::VC1902TargetModel::classof(), xilinx::AIE::VE2302TargetModel::classof(), xilinx::AIE::VE2802TargetModel::classof(), xilinx::AIE::BaseNPUTargetModel::classof(), xilinx::AIE::NPUTargetModel::classof(), xilinx::AIE::VirtualizedNPUTargetModel::classof(), xilinx::AIE::NPU2TargetModel::classof(), and xilinx::AIE::VirtualizedNPU2TargetModel::classof().

getLocalLockAddress()

virtual std::optional< uint32_t > xilinx::AIE::AIETargetModel::getLocalLockAddress ( uint32_t  lockId, TileID  tile  ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

getLocalMemorySize()

virtual uint32_t xilinx::AIE::AIETargetModel::getLocalMemorySize ( ) const

pure virtual

Return the size (in bytes) of the local data memory of a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetLocalMemorySize().

getLockLocalBaseIndex()

std::optional< uint32_t > xilinx::AIE::AIETargetModel::getLockLocalBaseIndex	(	int	localCol,
		int	localRow,
		int	lockCol,
		int	lockRow
	)		const

Return the lock base index (or offset) in the local tile when accessing a neighbor's lock or an empty optional if an invalid neighbor is given Takes into account differences between Memory and Core tiles.

Definition at line 751 of file AIETargetModel.cpp.

References getNumLocks(), isCoreTile(), isEast(), isInternal(), isMemEast(), isMemNorth(), isMemSouth(), isMemTile(), isMemWest(), and isWest().

Referenced by xilinx::AIE::AIERTControl::configureLocksInBdBlock().

getMaxLockValue()

virtual uint32_t xilinx::AIE::AIETargetModel::getMaxLockValue ( ) const

pure virtual

Return the maximum value that can be stored in a lock register.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

getMemEast()

virtual std::optional< TileID > xilinx::AIE::AIETargetModel::getMemEast ( TileID  src ) const

pure virtual

Return the tile ID of the memory to the east of the given tile, if it exists.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

getMemEastBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemEastBaseAddress ( ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetMemEastBaseAddress(), and getMemLocalBaseAddress().

getMemInternalBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemInternalBaseAddress ( TileID  src ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

getMemLocalBaseAddress()

std::optional< uint32_t > xilinx::AIE::AIETargetModel::getMemLocalBaseAddress	(	int	localCol,
		int	localRow,
		int	memCol,
		int	memRow
	)		const

Return the memory base address (or offset) in the local tile when accessing a neighbor's memory or an empty optional if an invalid neighbor is given Takes into account differences between Memory and Core tiles.

Definition at line 777 of file AIETargetModel.cpp.

References getMemEastBaseAddress(), getMemNorthBaseAddress(), getMemSouthBaseAddress(), getMemTileSize(), getMemWestBaseAddress(), isCoreTile(), isEast(), isInternal(), isMemEast(), isMemNorth(), isMemSouth(), isMemTile(), isMemWest(), and isWest().

Referenced by xilinx::AIE::AIERTControl::configureBdInBlock().

getMemNorth()

virtual std::optional< TileID > xilinx::AIE::AIETargetModel::getMemNorth ( TileID  src ) const

pure virtual

Return the tile ID of the memory to the north of the given tile, if it exists.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

getMemNorthBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemNorthBaseAddress ( ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetMemNorthBaseAddress(), and getMemLocalBaseAddress().

getMemSouth()

virtual std::optional< TileID > xilinx::AIE::AIETargetModel::getMemSouth ( TileID  src ) const

pure virtual

Return the tile ID of the memory to the south of the given tile, if it exists.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

getMemSouthBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemSouthBaseAddress ( ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetMemSouthBaseAddress(), and getMemLocalBaseAddress().

getMemTileSize()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemTileSize ( ) const

pure virtual

Return the size (in bytes) of a MemTile.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetMemTileSize(), and getMemLocalBaseAddress().

getMemWest()

virtual std::optional< TileID > xilinx::AIE::AIETargetModel::getMemWest ( TileID  src ) const

pure virtual

Return the tile ID of the memory to the west of the given tile, if it exists.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

getMemWestBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemWestBaseAddress ( ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetMemWestBaseAddress(), and getMemLocalBaseAddress().

getModelProperties()

uint32_t xilinx::AIE::AIETargetModel::getModelProperties ( ) const

inline

Definition at line 283 of file AIETargetModel.h.

Referenced by hasProperty().

getNumBanks()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumBanks ( int  col, int  row  ) const

pure virtual

Return the number of memory banks of a given tile.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetNumBanks().

getNumBDs()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumBDs ( int  col, int  row  ) const

pure virtual

Return the number of buffer descriptors supported by the DMA in the given tile.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetNumBDs(), xilinx::AIEX::getBufferDescriptorAddressRegisterAddress(), BdIdGenerator::nextBdId(), and AIEAssignBufferDescriptorIDsPass::runOnOperation().

getNumDestShimMuxConnections()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumDestShimMuxConnections ( int  col, int  row, WireBundle  bundle  ) const

pure virtual

Return the number of destinations of connections inside a shimmux.

These are the targets of connect operations in the switchbox.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::Pathfinder::initialize().

getNumDestSwitchboxConnections()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumDestSwitchboxConnections ( int  col, int  row, WireBundle  bundle  ) const

pure virtual

Return the number of destinations of connections inside a switchbox.

These are the targets of connect operations in the switchbox.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::Pathfinder::initialize(), and validate().

getNumLocks()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumLocks ( int  col, int  row  ) const

pure virtual

Return the number of lock objects.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetNumLocks(), and getLockLocalBaseIndex().

getNumMemTileRows()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumMemTileRows ( ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, and xilinx::AIE::BaseNPUTargetModel.

Referenced by aieTargetModelGetNumMemTileRows(), and validate().

getNumSourceShimMuxConnections()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumSourceShimMuxConnections ( int  col, int  row, WireBundle  bundle  ) const

pure virtual

Return the number of sources of connections inside a shimmux.

These are the origins of connect operations in the switchbox.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getRowToShimChanMap(), and xilinx::AIE::Pathfinder::initialize().

getNumSourceSwitchboxConnections()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumSourceSwitchboxConnections ( int  col, int  row, WireBundle  bundle  ) const

pure virtual

Return the number of sources of connections inside a switchbox.

These are the origins of connect operations in the switchbox.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::Pathfinder::initialize(), and validate().

getRowShift()

virtual uint32_t xilinx::AIE::AIETargetModel::getRowShift ( ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelGetRowShift(), and xilinx::AIEX::getBufferDescriptorAddressRegisterAddress().

getShimBurstEncodingsAndLengths()

virtual std::vector< std::pair< uint32_t, uint32_t > > xilinx::AIE::AIETargetModel::getShimBurstEncodingsAndLengths ( ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2TargetModel, and xilinx::AIE::NPU2TargetModel.

getTargetArch()

virtual AIEArch xilinx::AIE::AIETargetModel::getTargetArch ( ) const

pure virtual

Return the target architecture.

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2TargetModel, and xilinx::AIE::NPU2TargetModel.

hasProperty()

bool xilinx::AIE::AIETargetModel::hasProperty ( ModelProperty  Prop ) const

inline

Definition at line 286 of file AIETargetModel.h.

References getModelProperties().

Referenced by xilinx::AIE::AIERTControl::AIERTControl(), aieTargetModelIsNPU(), and xilinx::AIE::AIERTControl::configureSwitches().

isBdChannelAccessible()

virtual bool xilinx::AIE::AIETargetModel::isBdChannelAccessible ( int  col, int  row, uint32_t  bd_id, int  channel  ) const

pure virtual

Return true iff buffer descriptor bd_id on tile (col, row) can be submitted on channel channel.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by BdIdGenerator::nextBdId().

isCoreTile()

virtual bool xilinx::AIE::AIETargetModel::isCoreTile ( int  col, int  row  ) const

pure virtual

Return true if the given tile is a 'Core' tile.

These tiles include a Core, TileDMA, tile memory, and stream connections.

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, and xilinx::AIE::BaseNPUTargetModel.

Referenced by aieTargetModelIsCoreTile(), xilinx::AIE::AIE2TargetModel::getLocalLockAddress(), getLockLocalBaseIndex(), getMemLocalBaseAddress(), xilinx::AIE::AIE2TargetModel::isLegalTileConnection(), and validate().

isEast()

bool xilinx::AIE::AIETargetModel::isEast ( int  srcCol, int  srcRow, int  dstCol, int  dstRow  ) const

inline

Return true if src is East of dst.

Definition at line 171 of file AIETargetModel.h.

Referenced by aieTargetModelIsEast(), getLockLocalBaseIndex(), getMemLocalBaseAddress(), xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE2TargetModel::isLegalMemAffinity(), and xilinx::AIE::AIE1TargetModel::isMemEast().

isInternal()

bool xilinx::AIE::AIETargetModel::isInternal ( int  srcCol, int  srcRow, int  dstCol, int  dstRow  ) const

inline

Return true if src is the internal memory of dst.

Definition at line 161 of file AIETargetModel.h.

Referenced by aieTargetModelIsInternal(), getLockLocalBaseIndex(), getMemLocalBaseAddress(), xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE2TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE1TargetModel::isMemEast(), xilinx::AIE::AIE2TargetModel::isMemEast(), and xilinx::AIE::AIE1TargetModel::isMemWest().

isLegalMemAffinity()

virtual bool xilinx::AIE::AIETargetModel::isLegalMemAffinity ( int  coreCol, int  coreRow, int  memCol, int  memRow  ) const

pure virtual

Return true if core can access the memory in mem.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelIsLegalMemAffinity().

isLegalTileConnection()

virtual bool xilinx::AIE::AIETargetModel::isLegalTileConnection ( int  col, int  row, WireBundle  srcBundle, int  srcChan, WireBundle  dstBundle, int  dstChan  ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::Pathfinder::initialize(), isLegalTileConnection(), and isLegalTileConnection().

isMemEast()

virtual bool xilinx::AIE::AIETargetModel::isMemEast ( int  srcCol, int  srcRow, int  dstCol, int  dstRow  ) const

pure virtual

Return true if src has a memory tile which is East of dst.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelIsMemEast(), getLockLocalBaseIndex(), and getMemLocalBaseAddress().

isMemNorth()

virtual bool xilinx::AIE::AIETargetModel::isMemNorth ( int  srcCol, int  srcRow, int  dstCol, int  dstRow  ) const

pure virtual

Return true if src has a memory tile which is North of dst.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelIsMemNorth(), getLockLocalBaseIndex(), and getMemLocalBaseAddress().

isMemSouth()

virtual bool xilinx::AIE::AIETargetModel::isMemSouth ( int  srcCol, int  srcRow, int  dstCol, int  dstRow  ) const

pure virtual

Return true if src has a memory tile which is South of dst.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelIsMemSouth(), getLockLocalBaseIndex(), and getMemLocalBaseAddress().

isMemTile()

virtual bool xilinx::AIE::AIETargetModel::isMemTile ( int  col, int  row  ) const

pure virtual

Return true if the given tile is an AIE2 'Memory' tile.

These tiles include a TileDMA, tile memory, and stream connections, but no core.

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, and xilinx::AIE::BaseNPUTargetModel.

Referenced by aieTargetModelIsMemTile(), xilinx::AIE::AIE2TargetModel::getLocalLockAddress(), getLockLocalBaseIndex(), getMemLocalBaseAddress(), xilinx::AIE::AIE2TargetModel::getMemSouth(), xilinx::AIE::AIE2TargetModel::getNumBanks(), xilinx::AIE::AIE2TargetModel::getNumBDs(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumLocks(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::isBdChannelAccessible(), xilinx::AIE::AIE2TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE2TargetModel::isLegalTileConnection(), and validate().

isMemWest()

virtual bool xilinx::AIE::AIETargetModel::isMemWest ( int  srcCol, int  srcRow, int  dstCol, int  dstRow  ) const

pure virtual

Return true if src has a memory tile which is West of dst.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieTargetModelIsMemWest(), getLockLocalBaseIndex(), and getMemLocalBaseAddress().

isNorth()

bool xilinx::AIE::AIETargetModel::isNorth ( int  srcCol, int  srcRow, int  dstCol, int  dstRow  ) const

inline

Return true if src is North of dst.

Definition at line 176 of file AIETargetModel.h.

Referenced by aieTargetModelIsNorth(), xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE1TargetModel::isMemNorth(), and xilinx::AIE::AIE2TargetModel::isMemNorth().

isShimNOCorPLTile()

virtual bool xilinx::AIE::AIETargetModel::isShimNOCorPLTile ( int  col, int  row  ) const

pure virtual

Return true if the given tile is either a Shim NOC or a Shim PL interface tile.

Implemented in xilinx::AIE::VC1902TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, and xilinx::AIE::BaseNPUTargetModel.

Referenced by aieTargetModelIsShimNOCorPLTile(), xilinx::AIE::AIE2TargetModel::getLocalLockAddress(), xilinx::AIE::AIE1TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::Pathfinder::initialize(), xilinx::AIE::AIE1TargetModel::isLegalTileConnection(), and xilinx::AIE::AIE2TargetModel::isLegalTileConnection().

isShimNOCTile()

virtual bool xilinx::AIE::AIETargetModel::isShimNOCTile ( int  col, int  row  ) const

pure virtual

Return true if the given tile is a Shim NOC tile.

These tiles include a ShimDMA and a connection to the memory-mapped NOC. They do not contain any memory.

Implemented in xilinx::AIE::VC1902TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, xilinx::AIE::NPUTargetModel, xilinx::AIE::VirtualizedNPUTargetModel, xilinx::AIE::NPU2TargetModel, and xilinx::AIE::VirtualizedNPU2TargetModel.

Referenced by aieTargetModelIsShimNOCTile(), xilinx::AIE::AIERTControl::configureBdInBlock(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), getRowToShimChanMap(), xilinx::AIE::BaseNPUTargetModel::isShimNOCorPLTile(), AIEDMATasksToNPUPass::setAddressForSingleBD(), and validate().

isShimPLTile()

virtual bool xilinx::AIE::AIETargetModel::isShimPLTile ( int  col, int  row  ) const

pure virtual

Return true if the given tile is a Shim PL interface tile.

These tiles do not include a ShimDMA and instead include connections to the PL. They do not contain any memory.

Implemented in xilinx::AIE::VC1902TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, xilinx::AIE::BaseNPUTargetModel, xilinx::AIE::NPUTargetModel, and xilinx::AIE::NPU2TargetModel.

Referenced by aieTargetModelIsShimPLTile(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), and validate().

isSouth()

bool xilinx::AIE::AIETargetModel::isSouth ( int  srcCol, int  srcRow, int  dstCol, int  dstRow  ) const

inline

Return true if src is South of dst.

Definition at line 181 of file AIETargetModel.h.

Referenced by aieTargetModelIsSouth(), xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE1TargetModel::isMemSouth(), and xilinx::AIE::AIE2TargetModel::isMemSouth().

isValidTile()

virtual bool xilinx::AIE::AIETargetModel::isValidTile ( TileID  src ) const

inlinevirtual

Return true if the given tile ID is valid.

Definition at line 142 of file AIETargetModel.h.

References columns(), rows(), and xilinx::AIE::src.

Referenced by xilinx::AIE::AIE1TargetModel::getMemEast(), xilinx::AIE::AIE2TargetModel::getMemEast(), xilinx::AIE::AIE1TargetModel::getMemNorth(), xilinx::AIE::AIE2TargetModel::getMemNorth(), xilinx::AIE::AIE1TargetModel::getMemSouth(), xilinx::AIE::AIE2TargetModel::getMemSouth(), xilinx::AIE::AIE1TargetModel::getMemWest(), and xilinx::AIE::AIE2TargetModel::getMemWest().

isWest()

bool xilinx::AIE::AIETargetModel::isWest ( int  srcCol, int  srcRow, int  dstCol, int  dstRow  ) const

inline

Return true if src is West of dst.

Definition at line 166 of file AIETargetModel.h.

Referenced by aieTargetModelIsWest(), getLockLocalBaseIndex(), getMemLocalBaseAddress(), xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE2TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE1TargetModel::isMemWest(), and xilinx::AIE::AIE2TargetModel::isMemWest().

rows()

virtual int xilinx::AIE::AIETargetModel::rows ( ) const

pure virtual

Return the number of rows in the device.

Implemented in xilinx::AIE::VC1902TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, and xilinx::AIE::BaseNPUTargetModel.

Referenced by aieTargetModelRows(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), getRowToShimChanMap(), getTileToControllerIdMap(), getTileToControllerIdMap6RowsOrLess(), isValidTile(), and validate().

validate()

void xilinx::AIE::AIETargetModel::validate

(

)

const

Definition at line 692 of file AIETargetModel.cpp.

References columns(), getNumDestSwitchboxConnections(), getNumMemTileRows(), getNumSourceSwitchboxConnections(), isCoreTile(), isMemTile(), isShimNOCTile(), isShimPLTile(), and rows().

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The documentation for this class was generated from the following files:

• include/aie/Dialect/AIE/IR/AIETargetModel.h
• lib/Dialect/AIE/IR/AIETargetModel.cpp