19 return AieTargetModel{
reinterpret_cast<std::uintptr_t
>(&tm)};
36 return unwrap(targetModel).
columns();
40 return unwrap(targetModel).
rows();
44 return unwrap(targetModel).
isCoreTile(col, row);
48 return unwrap(targetModel).
isMemTile(col, row);
65 int src_row,
int dst_col,
int dst_row) {
66 return unwrap(targetModel).
isInternal(src_col, src_row, dst_col, dst_row);
70 int dst_col,
int dst_row) {
71 return unwrap(targetModel).
isWest(src_col, src_row, dst_col, dst_row);
75 int dst_col,
int dst_row) {
76 return unwrap(targetModel).
isEast(src_col, src_row, dst_col, dst_row);
80 int dst_col,
int dst_row) {
81 return unwrap(targetModel).
isNorth(src_col, src_row, dst_col, dst_row);
85 int dst_col,
int dst_row) {
86 return unwrap(targetModel).
isSouth(src_col, src_row, dst_col, dst_row);
90 int src_row,
int dst_col,
int dst_row) {
91 return unwrap(targetModel).
isMemWest(src_col, src_row, dst_col, dst_row);
95 int src_row,
int dst_col,
int dst_row) {
96 return unwrap(targetModel).
isMemEast(src_col, src_row, dst_col, dst_row);
100 int src_row,
int dst_col,
int dst_row) {
101 return unwrap(targetModel).
isMemNorth(src_col, src_row, dst_col, dst_row);
105 int src_row,
int dst_col,
int dst_row) {
106 return unwrap(targetModel).
isMemSouth(src_col, src_row, dst_col, dst_row);
110 int src_row,
int dst_col,
int dst_row) {
111 return unwrap(targetModel)
141 return unwrap(targetModel).
getNumBDs(col, row);
164 AieTargetModel targetModel,
int col,
int row, uint32_t bundle) {
165 xilinx::AIE::WireBundle wireBundle =
166 static_cast<xilinx::AIE::WireBundle
>(bundle);
167 return unwrap(targetModel)
172 AieTargetModel targetModel,
int col,
int row, uint32_t bundle) {
173 xilinx::AIE::WireBundle wireBundle =
174 static_cast<xilinx::AIE::WireBundle
>(bundle);
175 return unwrap(targetModel)
182 xilinx::AIE::WireBundle wireBundle =
183 static_cast<xilinx::AIE::WireBundle
>(bundle);
188 AieTargetModel targetModel,
int col,
int row, uint32_t bundle) {
189 xilinx::AIE::WireBundle wireBundle =
190 static_cast<xilinx::AIE::WireBundle
>(bundle);
191 return unwrap(targetModel)
bool aieTargetModelIsLegalMemAffinity(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
uint32_t aieTargetModelGetNumSourceShimMuxConnections(AieTargetModel targetModel, int col, int row, uint32_t bundle)
int aieTargetModelRows(AieTargetModel targetModel)
Returns the number of rows in the target model.
uint32_t aieTargetModelGetNumMemTileRows(AieTargetModel targetModel)
bool aieTargetModelIsShimNOCTile(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsCoreTile(AieTargetModel targetModel, int col, int row)
uint32_t aieTargetModelGetRowShift(AieTargetModel targetModel)
bool aieTargetModelIsInternal(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
uint32_t aieTargetModelGetLocalMemorySize(AieTargetModel targetModel)
bool aieTargetModelIsMemNorth(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
int aieTargetModelColumns(AieTargetModel targetModel)
Returns the number of columns in the target model.
uint32_t aieTargetModelGetNumBanks(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsWest(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
bool aieTargetModelIsMemSouth(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
uint32_t aieTargetModelGetNumDestSwitchboxConnections(AieTargetModel targetModel, int col, int row, uint32_t bundle)
uint32_t aieTargetModelGetMemTileSize(AieTargetModel targetModel)
AieTargetModel aieGetTargetModel(uint32_t device)
bool aieTargetModelIsMemEast(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
bool aieTargetModelIsSouth(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
bool aieTargetModelIsShimPLTile(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsNorth(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
uint32_t aieTargetModelGetNumDestShimMuxConnections(AieTargetModel targetModel, int col, int row, uint32_t bundle)
uint32_t aieTargetModelGetNumBDs(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsNPU(AieTargetModel targetModel)
Returns true if this is an NPU target model.
uint32_t aieTargetModelGetNumLocks(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsMemTile(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsShimNOCorPLTile(AieTargetModel targetModel, int col, int row)
uint32_t aieTargetModelGetMemSouthBaseAddress(AieTargetModel targetModel)
uint32_t aieTargetModelGetMaxChannelNumForAdjacentMemTile(AieTargetModel targetModel, int col, int row)
uint32_t aieTargetModelGetMemEastBaseAddress(AieTargetModel targetModel)
uint32_t aieTargetModelGetColumnShift(AieTargetModel targetModel)
bool aieTargetModelIsEast(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
bool aieTargetModelIsMemWest(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
uint32_t aieTargetModelGetMemNorthBaseAddress(AieTargetModel targetModel)
uint32_t aieTargetModelGetNumSourceSwitchboxConnections(AieTargetModel targetModel, int col, int row, uint32_t bundle)
uint32_t aieTargetModelGetMemWestBaseAddress(AieTargetModel targetModel)
uint32_t aieGetTargetModelAddressGenGranularity(AieTargetModel targetModel)
Returns the data bus width for the target model.
bool isNorth(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is North of dst.
bool isSouth(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is South of dst.
bool isWest(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is West of dst.
virtual bool isMemNorth(int srcCol, int srcRow, int dstCol, int dstRow) const =0
Return true if src has a memory tile which is North of dst.
virtual uint32_t getNumSourceShimMuxConnections(int col, int row, WireBundle bundle) const =0
Return the number of sources of connections inside a shimmux.
virtual uint32_t getNumBDs(int col, int row) const =0
Return the number of buffer descriptors supported by the DMA in the given tile.
virtual uint32_t getMemSouthBaseAddress() const =0
Return the base address in the local address map for a core.
virtual uint32_t getLocalMemorySize() const =0
Return the size (in bytes) of the local data memory of a core.
virtual bool isCoreTile(int col, int row) const =0
Return true if the given tile is a 'Core' tile.
virtual uint32_t getNumBanks(int col, int row) const =0
Return the number of memory banks of a given tile.
virtual bool isMemEast(int srcCol, int srcRow, int dstCol, int dstRow) const =0
Return true if src has a memory tile which is East of dst.
virtual bool isMemTile(int col, int row) const =0
Return true if the given tile is an AIE2 'Memory' tile.
virtual uint32_t getMaxChannelNumForAdjacentMemTile(int col, int row) const =0
bool isEast(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is East of dst.
virtual bool isMemSouth(int srcCol, int srcRow, int dstCol, int dstRow) const =0
Return true if src has a memory tile which is South of dst.
virtual uint32_t getMemWestBaseAddress() const =0
Return the base address in the local address map for a core.
virtual uint32_t getNumLocks(int col, int row) const =0
Return the number of lock objects.
virtual int rows() const =0
Return the number of rows in the device.
virtual bool isShimNOCTile(int col, int row) const =0
Return true if the given tile is a Shim NOC tile.
virtual bool isShimNOCorPLTile(int col, int row) const =0
Return true if the given tile is either a Shim NOC or a Shim PL interface tile.
virtual bool isShimPLTile(int col, int row) const =0
Return true if the given tile is a Shim PL interface tile.
virtual uint32_t getColumnShift() const =0
virtual uint32_t getMemNorthBaseAddress() const =0
Return the base address in the local address map for a core.
bool hasProperty(ModelProperty Prop) const
virtual int columns() const =0
Return the number of columns in the device.
virtual uint32_t getMemEastBaseAddress() const =0
Return the base address in the local address map for a core.
virtual uint32_t getNumMemTileRows() const =0
virtual uint32_t getNumDestShimMuxConnections(int col, int row, WireBundle bundle) const =0
Return the number of destinations of connections inside a shimmux.
virtual bool isMemWest(int srcCol, int srcRow, int dstCol, int dstRow) const =0
Return true if src has a memory tile which is West of dst.
virtual uint32_t getNumDestSwitchboxConnections(int col, int row, WireBundle bundle) const =0
Return the number of destinations of connections inside a switchbox.
bool isInternal(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is the internal memory of dst.
virtual uint32_t getRowShift() const =0
virtual bool isLegalMemAffinity(int coreCol, int coreRow, int memCol, int memRow) const =0
Return true if core can access the memory in mem.
virtual uint32_t getAddressGenGranularity() const =0
Return the data bus width of the device.
virtual uint32_t getMemTileSize() const =0
Return the size (in bytes) of a MemTile.
virtual uint32_t getNumSourceSwitchboxConnections(int col, int row, WireBundle bundle) const =0
Return the number of sources of connections inside a switchbox.
const AIETargetModel & getTargetModel(mlir::Operation *op)