MLIR-AIE
TargetModel.cpp
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1//===- TargetModel.cpp - C API for AIE TargetModel ------------------------===//
2//
3// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7// (c) Copyright 2024 Advanced Micro Devices, Inc.
8//
9//===----------------------------------------------------------------------===//
10
11#include "aie-c/TargetModel.h"
12
15
16using namespace mlir;
17
18static inline AieTargetModel wrap(const xilinx::AIE::AIETargetModel &tm) {
19 return AieTargetModel{reinterpret_cast<std::uintptr_t>(&tm)};
20}
21
22static inline const xilinx::AIE::AIETargetModel &unwrap(AieTargetModel tm) {
23 return *reinterpret_cast<const xilinx::AIE::AIETargetModel *>(tm.d);
24}
25
26AieTargetModel aieGetTargetModel(uint32_t device) {
27 return wrap(
28 xilinx::AIE::getTargetModel(static_cast<xilinx::AIE::AIEDevice>(device)));
29}
30
31uint32_t aieGetTargetModelAddressGenGranularity(AieTargetModel targetModel) {
32 return unwrap(targetModel).getAddressGenGranularity();
33}
34
35int aieTargetModelColumns(AieTargetModel targetModel) {
36 return unwrap(targetModel).columns();
37}
38
39int aieTargetModelRows(AieTargetModel targetModel) {
40 return unwrap(targetModel).rows();
41}
42
43bool aieTargetModelIsCoreTile(AieTargetModel targetModel, int col, int row) {
44 return unwrap(targetModel).isCoreTile(col, row);
45}
46
47bool aieTargetModelIsMemTile(AieTargetModel targetModel, int col, int row) {
48 return unwrap(targetModel).isMemTile(col, row);
49}
50
51bool aieTargetModelIsShimNOCTile(AieTargetModel targetModel, int col, int row) {
52 return unwrap(targetModel).isShimNOCTile(col, row);
53}
54
55bool aieTargetModelIsShimPLTile(AieTargetModel targetModel, int col, int row) {
56 return unwrap(targetModel).isShimPLTile(col, row);
57}
58
59bool aieTargetModelIsShimNOCorPLTile(AieTargetModel targetModel, int col,
60 int row) {
61 return unwrap(targetModel).isShimNOCorPLTile(col, row);
62}
63
64bool aieTargetModelIsInternal(AieTargetModel targetModel, int src_col,
65 int src_row, int dst_col, int dst_row) {
66 return unwrap(targetModel).isInternal(src_col, src_row, dst_col, dst_row);
67}
68
69bool aieTargetModelIsWest(AieTargetModel targetModel, int src_col, int src_row,
70 int dst_col, int dst_row) {
71 return unwrap(targetModel).isWest(src_col, src_row, dst_col, dst_row);
72}
73
74bool aieTargetModelIsEast(AieTargetModel targetModel, int src_col, int src_row,
75 int dst_col, int dst_row) {
76 return unwrap(targetModel).isEast(src_col, src_row, dst_col, dst_row);
77}
78
79bool aieTargetModelIsNorth(AieTargetModel targetModel, int src_col, int src_row,
80 int dst_col, int dst_row) {
81 return unwrap(targetModel).isNorth(src_col, src_row, dst_col, dst_row);
82}
83
84bool aieTargetModelIsSouth(AieTargetModel targetModel, int src_col, int src_row,
85 int dst_col, int dst_row) {
86 return unwrap(targetModel).isSouth(src_col, src_row, dst_col, dst_row);
87}
88
89bool aieTargetModelIsMemWest(AieTargetModel targetModel, int src_col,
90 int src_row, int dst_col, int dst_row) {
91 return unwrap(targetModel).isMemWest(src_col, src_row, dst_col, dst_row);
92}
93
94bool aieTargetModelIsMemEast(AieTargetModel targetModel, int src_col,
95 int src_row, int dst_col, int dst_row) {
96 return unwrap(targetModel).isMemEast(src_col, src_row, dst_col, dst_row);
97}
98
99bool aieTargetModelIsMemNorth(AieTargetModel targetModel, int src_col,
100 int src_row, int dst_col, int dst_row) {
101 return unwrap(targetModel).isMemNorth(src_col, src_row, dst_col, dst_row);
102}
103
104bool aieTargetModelIsMemSouth(AieTargetModel targetModel, int src_col,
105 int src_row, int dst_col, int dst_row) {
106 return unwrap(targetModel).isMemSouth(src_col, src_row, dst_col, dst_row);
107}
108
109bool aieTargetModelIsLegalMemAffinity(AieTargetModel targetModel, int src_col,
110 int src_row, int dst_col, int dst_row) {
111 return unwrap(targetModel)
112 .isLegalMemAffinity(src_col, src_row, dst_col, dst_row);
113}
114
115uint32_t aieTargetModelGetMemSouthBaseAddress(AieTargetModel targetModel) {
116 return unwrap(targetModel).getMemSouthBaseAddress();
117}
118
119uint32_t aieTargetModelGetMemNorthBaseAddress(AieTargetModel targetModel) {
120 return unwrap(targetModel).getMemNorthBaseAddress();
121}
122
123uint32_t aieTargetModelGetMemEastBaseAddress(AieTargetModel targetModel) {
124 return unwrap(targetModel).getMemEastBaseAddress();
125}
126
127uint32_t aieTargetModelGetMemWestBaseAddress(AieTargetModel targetModel) {
128 return unwrap(targetModel).getMemWestBaseAddress();
129}
130
131uint32_t aieTargetModelGetLocalMemorySize(AieTargetModel targetModel) {
132 return unwrap(targetModel).getLocalMemorySize();
133}
134
135uint32_t aieTargetModelGetNumLocks(AieTargetModel targetModel, int col,
136 int row) {
137 return unwrap(targetModel).getNumLocks(col, row);
138}
139
140uint32_t aieTargetModelGetNumBDs(AieTargetModel targetModel, int col, int row) {
141 return unwrap(targetModel).getNumBDs(col, row);
142}
143
144uint32_t aieTargetModelGetNumMemTileRows(AieTargetModel targetModel) {
145 return unwrap(targetModel).getNumMemTileRows();
146}
147
148uint32_t aieTargetModelGetMemTileSize(AieTargetModel targetModel) {
149 return unwrap(targetModel).getMemTileSize();
150}
151
152uint32_t aieTargetModelGetNumBanks(AieTargetModel targetModel, int col,
153 int row) {
154 return unwrap(targetModel).getNumBanks(col, row);
155}
156
157bool aieTargetModelIsNPU(AieTargetModel targetModel) {
158 return unwrap(targetModel).hasProperty(xilinx::AIE::AIETargetModel::IsNPU);
159}
160
161uint32_t aieTargetModelGetColumnShift(AieTargetModel targetModel) {
162 return unwrap(targetModel).getColumnShift();
163}
164
165uint32_t aieTargetModelGetRowShift(AieTargetModel targetModel) {
166 return unwrap(targetModel).getRowShift();
167}
bool aieTargetModelIsLegalMemAffinity(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
int aieTargetModelRows(AieTargetModel targetModel)
Returns the number of rows in the target model.
uint32_t aieTargetModelGetNumMemTileRows(AieTargetModel targetModel)
bool aieTargetModelIsShimNOCTile(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsCoreTile(AieTargetModel targetModel, int col, int row)
uint32_t aieTargetModelGetRowShift(AieTargetModel targetModel)
bool aieTargetModelIsInternal(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
uint32_t aieTargetModelGetLocalMemorySize(AieTargetModel targetModel)
bool aieTargetModelIsMemNorth(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
int aieTargetModelColumns(AieTargetModel targetModel)
Returns the number of columns in the target model.
uint32_t aieTargetModelGetNumBanks(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsWest(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
bool aieTargetModelIsMemSouth(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
uint32_t aieTargetModelGetMemTileSize(AieTargetModel targetModel)
AieTargetModel aieGetTargetModel(uint32_t device)
bool aieTargetModelIsMemEast(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
bool aieTargetModelIsSouth(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
bool aieTargetModelIsShimPLTile(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsNorth(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
uint32_t aieTargetModelGetNumBDs(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsNPU(AieTargetModel targetModel)
Returns true if this is an NPU target model.
uint32_t aieTargetModelGetNumLocks(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsMemTile(AieTargetModel targetModel, int col, int row)
bool aieTargetModelIsShimNOCorPLTile(AieTargetModel targetModel, int col, int row)
uint32_t aieTargetModelGetMemSouthBaseAddress(AieTargetModel targetModel)
uint32_t aieTargetModelGetMemEastBaseAddress(AieTargetModel targetModel)
uint32_t aieTargetModelGetColumnShift(AieTargetModel targetModel)
bool aieTargetModelIsEast(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
bool aieTargetModelIsMemWest(AieTargetModel targetModel, int src_col, int src_row, int dst_col, int dst_row)
uint32_t aieTargetModelGetMemNorthBaseAddress(AieTargetModel targetModel)
uint32_t aieTargetModelGetMemWestBaseAddress(AieTargetModel targetModel)
uint32_t aieGetTargetModelAddressGenGranularity(AieTargetModel targetModel)
Returns the data bus width for the target model.
bool isNorth(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is North of dst.
bool isSouth(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is South of dst.
bool isWest(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is West of dst.
virtual bool isMemNorth(int srcCol, int srcRow, int dstCol, int dstRow) const =0
Return true if src has a memory tile which is North of dst.
virtual uint32_t getNumBDs(int col, int row) const =0
Return the number of buffer descriptors supported by the DMA in the given tile.
virtual uint32_t getMemSouthBaseAddress() const =0
Return the base address in the local address map for a core.
virtual uint32_t getLocalMemorySize() const =0
Return the size (in bytes) of the local data memory of a core.
virtual bool isCoreTile(int col, int row) const =0
Return true if the given tile is a 'Core' tile.
virtual uint32_t getNumBanks(int col, int row) const =0
Return the number of memory banks of a given tile.
virtual bool isMemEast(int srcCol, int srcRow, int dstCol, int dstRow) const =0
Return true if src has a memory tile which is East of dst.
virtual bool isMemTile(int col, int row) const =0
Return true if the given tile is an AIE2 'Memory' tile.
bool isEast(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is East of dst.
virtual bool isMemSouth(int srcCol, int srcRow, int dstCol, int dstRow) const =0
Return true if src has a memory tile which is South of dst.
virtual uint32_t getMemWestBaseAddress() const =0
Return the base address in the local address map for a core.
virtual uint32_t getNumLocks(int col, int row) const =0
Return the number of lock objects.
virtual int rows() const =0
Return the number of rows in the device.
virtual bool isShimNOCTile(int col, int row) const =0
Return true if the given tile is a Shim NOC tile.
virtual bool isShimNOCorPLTile(int col, int row) const =0
Return true if the given tile is either a Shim NOC or a Shim PL interface tile.
virtual bool isShimPLTile(int col, int row) const =0
Return true if the given tile is a Shim PL interface tile.
virtual uint32_t getColumnShift() const =0
virtual uint32_t getMemNorthBaseAddress() const =0
Return the base address in the local address map for a core.
bool hasProperty(ModelProperty Prop) const
virtual int columns() const =0
Return the number of columns in the device.
virtual uint32_t getMemEastBaseAddress() const =0
Return the base address in the local address map for a core.
virtual uint32_t getNumMemTileRows() const =0
virtual bool isMemWest(int srcCol, int srcRow, int dstCol, int dstRow) const =0
Return true if src has a memory tile which is West of dst.
bool isInternal(int srcCol, int srcRow, int dstCol, int dstRow) const
Return true if src is the internal memory of dst.
virtual uint32_t getRowShift() const =0
virtual bool isLegalMemAffinity(int coreCol, int coreRow, int memCol, int memRow) const =0
Return true if core can access the memory in mem.
virtual uint32_t getAddressGenGranularity() const =0
Return the data bus width of the device.
virtual uint32_t getMemTileSize() const =0
Return the size (in bytes) of a MemTile.
const AIETargetModel & getTargetModel(mlir::Operation *op)