#include "AIEEnums.h"
#include "aie/Dialect/AIE/IR/AIECoreMemory.h"
#include "aie/Dialect/AIE/IR/AIETargetModel.h"
#include "mlir/Dialect/DLTI/Traits.h"
#include "mlir/Dialect/Func/IR/FuncOps.h"
#include "mlir/Dialect/MemRef/IR/MemRef.h"
#include "mlir/IR/BuiltinAttributes.h"
#include "mlir/IR/OpDefinition.h"
#include "mlir/IR/OpImplementation.h"
#include "mlir/IR/SymbolTable.h"
#include "mlir/Interfaces/DataLayoutInterfaces.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "aie/Dialect/AIE/IR/AIEDialect.h.inc"
#include "aie/Dialect/AIE/IR/AIETypes.h.inc"
#include "aie/Dialect/AIE/IR/AIEAttrs.h.inc"
#include "aie/Dialect/AIE/IR/AIEInterfaces.h.inc"
#include "aie/Dialect/AIE/IR/AIEOps.h.inc"

Include dependency graph for AIEDialect.h:

Classes
struct	xilinx::AIE::HasValidBDs< ConcreteType >
struct	xilinx::AIE::HasValidDMAChannels< ConcreteType >
struct	xilinx::AIE::SkipAccessibilityCheckTrait< ConcreteType >
struct	xilinx::AIE::AttrBasedSymbolVisibility< ConcreteType >
struct	xilinx::AIE::IsFlowEndPoint< ConcreteType >
class	xilinx::AIE::NamedOpTable
class	xilinx::AIE::NamedOpTableCollection
struct	xilinx::AIE::MyOffsetSizeAndStrideOpInterfaceTrait< ConcreteOp >
struct	xilinx::AIE::MyOffsetSizeAndStrideOpInterface
struct	xilinx::AIE::MyOffsetSizeAndStrideOpInterface::Trait< ConcreteOp >
struct	xilinx::AIE::StreamWindow
struct	xilinx::AIE::StreamWindowStep
struct	llvm::DenseMapInfo< xilinx::AIE::ObjectFifoAcquireOp >
struct	llvm::DenseMapInfo< xilinx::AIE::ObjectFifoCreateOp >
struct	llvm::DenseMapInfo< xilinx::AIE::DMAChannel >
struct	llvm::DenseMapInfo< xilinx::AIE::Port >
struct	std::less< xilinx::AIE::Port >
struct	std::hash< xilinx::AIE::Port >

Namespaces
namespace	xilinx
namespace	xilinx::AIE
namespace	llvm

Macros
#define	GET_TYPEDEF_CLASSES
#define	GET_ATTRDEF_CLASSES
#define	GENERATE_TO_STRING(TYPE_WITH_INSERTION_OP)
#define	GET_OP_CLASSES

Typedefs
using	xilinx::AIE::Port
using	xilinx::AIE::Connect
using	xilinx::AIE::DMAChannel

Functions
uint32_t	xilinx::AIE::getShimBurstLengthBytes (const AIE::AIETargetModel &tm, uint32_t burstLength)
uint32_t	xilinx::AIE::getShimBurstLengthEncoding (const AIE::AIETargetModel &tm, uint32_t burstLength)
mlir::Operation *	xilinx::AIE::lookupNamedOpIn (mlir::Operation *symbolTableOp, mlir::StringAttr name)
mlir::Operation *	xilinx::AIE::lookupNamedOpIn (mlir::Operation *symbolTableOp, llvm::StringRef name)
mlir::Operation *	xilinx::AIE::lookupNamedOp (mlir::Operation *from, mlir::StringAttr name)
mlir::Operation *	xilinx::AIE::lookupNamedOp (mlir::Operation *from, llvm::StringRef name)
template<typename OpTy, typename NameT>
OpTy	xilinx::AIE::lookupNamedOpIn (mlir::Operation *symbolTableOp, NameT name)
template<typename OpTy, typename NameT>
OpTy	xilinx::AIE::lookupNamedOp (mlir::Operation *from, NameT name)
mlir::LogicalResult	xilinx::AIE::verifyOffsetSizeAndStrideOp (mlir::OffsetSizeAndStrideOpInterface op)
mlir::ParseResult	xilinx::AIE::parseTypedDynamicIndexList (mlir::OpAsmParser &parser, llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &values, mlir::DenseI64ArrayAttr &integers, llvm::SmallVectorImpl< mlir::Type > &types)
void	xilinx::AIE::printTypedDynamicIndexList (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::OperandRange values, llvm::ArrayRef< int64_t > integers, mlir::TypeRange types)
mlir::LogicalResult	xilinx::AIE::myVerifyOffsetSizeAndStrideOp (mlir::OffsetSizeAndStrideOpInterface op)
void	xilinx::AIE::registerAIETranslations ()
WireBundle	xilinx::AIE::getConnectingBundle (WireBundle dir)
std::optional< std::pair< TileID, Port > >	xilinx::AIE::getConnectingWireEndpoint (const AIETargetModel &targetModel, TileID tile, Port port)
const AIETargetModel &	xilinx::AIE::getTargetModel (mlir::Operation *op)
const AIETargetModel &	xilinx::AIE::getTargetModel (AIEDevice device)
AIETargetModel::SharedMemory	xilinx::AIE::sharedMemory (TileOp a, TileOp b)
	Which of a's and b's memory modules both tiles can address.
mlir::ParseResult	xilinx::AIE::parseObjectFifoProducerTile (mlir::OpAsmParser &parser, mlir::OpAsmParser::UnresolvedOperand &operand, BDDimLayoutArrayAttr &dimensions)
void	xilinx::AIE::printObjectFifoProducerTile (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::Value operand, BDDimLayoutArrayAttr dimensions)
mlir::ParseResult	xilinx::AIE::parseDMAStartChannel (mlir::OpAsmParser &parser, mlir::Attribute &channel)
void	xilinx::AIE::printDMAStartChannel (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::Attribute channel)
mlir::ParseResult	xilinx::AIE::parseObjectFifoAcquireObjects (mlir::OpAsmParser &parser, ObjectFifoPortAttr &port, llvm::SmallVectorImpl< mlir::Type > &objects)
void	xilinx::AIE::printObjectFifoAcquireObjects (mlir::OpAsmPrinter &printer, mlir::Operation *op, ObjectFifoPortAttr port, mlir::TypeRange objects)
mlir::ParseResult	xilinx::AIE::parseObjectFifoReleaseCount (mlir::OpAsmParser &parser, ObjectFifoPortAttr &port, mlir::IntegerAttr &size)
void	xilinx::AIE::printObjectFifoReleaseCount (mlir::OpAsmPrinter &printer, mlir::Operation *op, ObjectFifoPortAttr port, mlir::IntegerAttr size)
mlir::ParseResult	xilinx::AIE::parseObjectFifoConsumerTiles (mlir::OpAsmParser &parser, llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &tiles, BDDimLayoutArrayArrayAttr &dimensions)
void	xilinx::AIE::printObjectFifoConsumerTiles (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::OperandRange tiles, BDDimLayoutArrayArrayAttr dimsPerTileAttr)
mlir::ParseResult	xilinx::AIE::parseFlowVias (mlir::OpAsmParser &parser, llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &vias, mlir::DenseI32ArrayAttr &ingressBundles, mlir::DenseI32ArrayAttr &ingressChannels, mlir::DenseI32ArrayAttr &egressBundles, mlir::DenseI32ArrayAttr &egressChannels)
void	xilinx::AIE::printFlowVias (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::OperandRange vias, mlir::DenseI32ArrayAttr ingressBundles, mlir::DenseI32ArrayAttr ingressChannels, mlir::DenseI32ArrayAttr egressBundles, mlir::DenseI32ArrayAttr egressChannels)
int32_t	xilinx::AIE::getBufferBaseAddress (mlir::Operation *bufOp)
mlir::ParseResult	xilinx::AIE::parseTraceEvent (mlir::AsmParser &parser, mlir::Attribute &result)
void	xilinx::AIE::printTraceEventEnum (mlir::AsmPrinter &printer, mlir::Attribute attr)
llvm::SmallVector< ObjectFifoDmaEndpointOp >	xilinx::AIE::turnEndpoints (ObjectFifoDmaEndpointOp end)
int64_t	xilinx::AIE::turnPasses (llvm::ArrayRef< std::pair< int64_t, int64_t > > ends)
bool	xilinx::AIE::keepsPktHeader (TileID tile, Port master, std::optional< bool > keep)
bool	xilinx::AIE::isDirectional (WireBundle bundle)
void	xilinx::AIE::collectTiles (DeviceOp &device, llvm::DenseMap< TileID, mlir::Operation * > &tiles)
void	xilinx::AIE::collectBuffers (DeviceOp &device, llvm::DenseMap< mlir::Operation *, llvm::SmallVector< BufferOp, 4 > > &buffers)
bool	xilinx::AIE::isContiguousBDTransfer (llvm::ArrayRef< BDDimLayoutAttr > dims)
int64_t	xilinx::AIE::paddedSize (llvm::ArrayRef< BDDimLayoutAttr > dims, llvm::ArrayRef< BDPadLayoutAttr > pads, int64_t fallback)
std::optional< llvm::SmallVector< BDDimLayoutAttr > >	xilinx::AIE::normalizedBDDims (llvm::ArrayRef< BDDimLayoutAttr > dims, int64_t len)
mlir::FailureOr< int64_t >	xilinx::AIE::getLengthUnitBytes (mlir::Operation *op, int64_t lengthUnit, mlir::BaseMemRefType buffer)
mlir::LogicalResult	xilinx::AIE::verifyLengthParameter (mlir::Operation *op, std::optional< int64_t > lengthUnit, mlir::BaseMemRefType buffer, std::optional< int64_t > lenElems, bool contiguous, llvm::ArrayRef< int64_t > innerSizes)
void	xilinx::AIE::placeRuntimeLengthDimension (llvm::MutableArrayRef< int64_t > sizes, llvm::MutableArrayRef< int64_t > strides)
mlir::LogicalResult	xilinx::AIE::verifyLengthParameterTile (mlir::Operation *op, const AIETargetModel &targetModel, int col, int row)
mlir::LogicalResult	xilinx::AIE::verifyDMABDOutOfOrderId (DMABDOp bd, bool packetEnabledByContext=false)
mlir::LogicalResult	xilinx::AIE::verifyDMABDIteration (DMABDOp bd, AIETileType tileType)
mlir::LogicalResult	xilinx::AIE::verifyAssignedPacket (mlir::Operation *op, PacketInfoAttr packet, llvm::StringRef what="packet")
mlir::LogicalResult	xilinx::AIE::verifyOutOfOrderChannel (mlir::Operation *op, DMAChannelDir dir, bool outOfOrder, llvm::ArrayRef< DMABDOp > bds, bool packetEnabledByContext=false)
mlir::LogicalResult	xilinx::AIE::verifyBdLockPair (mlir::Block &block, bool outOfOrder, UseLockOp &acquire, UseLockOp &release)
mlir::LogicalResult	xilinx::AIE::inferStreamWindow (llvm::ArrayRef< BDDimLayoutAttr > dims, llvm::ArrayRef< BDPadLayoutAttr > pads, int64_t objectSize, llvm::function_ref< mlir::InFlightDiagnostic()> emitError, StreamWindow &window)
llvm::SmallVector< StreamWindowStep >	xilinx::AIE::streamWindowSteps (const StreamWindow &w)
llvm::SmallVector< uint32_t >	xilinx::AIE::getAssignedBdIds (DmaBody program)
mlir::LogicalResult	xilinx::AIE::verifyDMAChannelsResolved (DeviceOp device)

Macro Definition Documentation

◆ GENERATE_TO_STRING

#define GENERATE_TO_STRING ( TYPE_WITH_INSERTION_OP )

Value:

  friend std::string to_string(const TYPE_WITH_INSERTION_OP &s) {              \
    std::ostringstream ss;                                                     \
    ss << s;                                                                   \
    return ss.str();                                                           \
  }

Definition at line 258 of file AIEDialect.h.

◆ GET_ATTRDEF_CLASSES

#define GET_ATTRDEF_CLASSES

Definition at line 244 of file AIEDialect.h.

◆ GET_OP_CLASSES

#define GET_OP_CLASSES

Definition at line 427 of file AIEDialect.h.

◆ GET_TYPEDEF_CLASSES

#define GET_TYPEDEF_CLASSES

Definition at line 237 of file AIEDialect.h.

Classes

Namespaces

Macros

Typedefs

Functions

Macro Definition Documentation

◆ GENERATE_TO_STRING

◆ GET_ATTRDEF_CLASSES

◆ GET_OP_CLASSES

◆ GET_TYPEDEF_CLASSES