xilinx::AIE Namespace Reference

Namespaces
namespace	aie1_port_id
namespace	aie2_port_id

Classes
struct	ResetConfig
struct	MemoryRun
struct	HasValidBDs
struct	HasValidDMAChannels
struct	SkipAccessibilityCheckTrait
struct	AttrBasedSymbolVisibility
struct	IsFlowEndPoint
class	NamedOpTable
class	NamedOpTableCollection
struct	MyOffsetSizeAndStrideOpInterfaceTrait
struct	MyOffsetSizeAndStrideOpInterface
struct	StreamWindow
struct	StreamWindowStep
struct	DmaBdField
	Bits [shift, shift + width) of register word in a buffer descriptor's register block. More...
struct	DmaBdLayout
	The register layout of one tile type's DMA buffer descriptor. More...
class	AIETargetModel
class	AIE1TargetModel
class	AIE2TargetModel
class	AIE2PSTargetModel
class	VE3858TargetModel
class	VC1902TargetModel
class	VE2302TargetModel
class	VE2802TargetModel
class	BaseNPU1TargetModel
class	VirtualizedNPU1TargetModel
class	BaseNPU2TargetModel
class	NPU2TargetModel
class	VirtualizedNPU2TargetModel
struct	TileMemoryLimits
	A memtile is reached by DMA rather than by core vector load and store, so its bus width also covers the vector-alignment requirement. More...
struct	BufferAllocation
class	CoreTurns
	The order one core moves objects through several pools, read off its program, so that one DMA channel can serve those pools in turn. More...
class	DMAChannelAnalysis
	Which DMA channels of each tile are already spoken for, so that a channel is handed out at most once across everything that programs one. More...
class	PacketIdSpace
	The packet ids a device has already spoken for. More...
struct	SwitchboxConnect
struct	PathEndPoint
struct	Flow
struct	SwitchSetting
struct	TreeHop
struct	PacketsApart
struct	TreeSplit
struct	RoutingFaults
struct	Routing
class	RoutingFailure
class	DeadlockProneRouting
class	PinnedRoutingFailure
struct	PacketConstraints
class	Pathfinder
class	DynamicTileAnalysis
struct	StreamDemand
struct	TileAvailability
class	Placer
class	SequentialPlacer
struct	SAConfig
class	SASchedule
struct	NetBoundingBox
struct	NetInfo
class	SAPlacer
class	ShimTransferSpans
	When the runtime sequences have each shim end's transfers in flight, so that ends never in flight together can take turns on one shim channel. More...
struct	StreamEndpoint
	A tile port at the edge of the stream fabric. More...
struct	TileDMAChannel
	One DMA channel of one tile. More...
struct	DmaChannelProgram
	The BD chain a DMA channel runs, as one aie.dma_start, aie.dma or runtime task programs it. More...
struct	StreamHop
	A switchbox a stream passes: the port it enters by and, where it is packet switched there, the arbiter it takes. More...
struct	RoutedStream
	One stream from a source tile port to a destination tile port, recovered from the physical switchbox and shim-mux configuration. More...
struct	HoldCycle
	A cycle of waits packet streams can deadlock in, given their routes. More...
class	StreamVolumeAnalysis
	How much data a stream carries over a run and how much a receiver takes in before it has to wait on another agent, read off BD lengths, repeat counts, lock initial values and runtime transfers. More...
class	StreamWaitGraph
	Which agent waits on which. More...
class	StreamDeadlockAnalysis
	Which streams can deadlock against each other if they share an arbiter or a link. More...
class	StreamConflicts
	The streams a device asks for or already routes, and which pairs of them must not share an arbiter or a link. More...
struct	StructuralGraph
	Ops and the labelled links between them, for ranking them by structure where a pass would otherwise fall back on op order. More...
struct	BitFieldInfo
	Bit field information for a register. More...
struct	RegisterInfo
	Register information. More...
struct	EventInfo
	Event information. More...
class	RegisterDatabase
	Register and event database for a specific architecture. More...
class	TxnLocBracket
struct	AIERTControl
struct	TxnLocEntry
class	NpuConfigCache

Typedefs
using	Port
using	Connect
using	DMAChannel
using	TileID
using	SwitchSettings = std::map<TileID, SwitchSetting>
using	PacketTrees = std::map<PathEndPoint, std::vector<TreeHop>>
using	PacketConflict
using	PacketsApartAcross
using	RoutingCheck = std::function<llvm::Error(const Routing &)>
using	PlacementResult = llvm::DenseMap<mlir::Operation *, TileID>

Enumerations
enum	AIEToConfigurationOutputType { Transaction , ControlPacket }
enum class	ResetTileType : unsigned {   None = 0 , ShimNOC = 1 << 0 , MemTile = 1 << 1 , CoreTile = 1 << 2 ,   All = ShimNOC | MemTile | CoreTile }
enum class	ResetMode {   Never , IfUsed , IfUsedFineGrained , IfChanged ,   IfChangedFineGrained , Always }
enum class	PlacerType { SequentialPlacer , SAPlacer }
	Placement algorithm type for pass option. More...

Functions
std::unique_ptr< mlir::OperationPass< xilinx::AIE::DeviceOp > >	createConvertAIEToTransactionPass ()
std::unique_ptr< mlir::OperationPass< xilinx::AIE::DeviceOp > >	createConvertAIEToControlPacketsPass ()
std::optional< mlir::ModuleOp >	convertTransactionBinaryToMLIR (mlir::MLIRContext *ctx, std::vector< uint8_t > &binary)
mlir::LogicalResult	generateAndInsertConfigOps (mlir::OpBuilder &builder, xilinx::AIE::DeviceOp device, xilinx::AIEX::BlockwriteData &blockwriteData, llvm::StringRef clElfDir="", AIEToConfigurationOutputType outputType=AIEToConfigurationOutputType::Transaction, bool skipCtrlPktOverlay=false)
mlir::LogicalResult	insertConfigOps (llvm::ArrayRef< std::pair< mlir::Operation *, xilinx::AIE::DeviceOp > > sites, AIEToConfigurationOutputType outputType)
mlir::LogicalResult	inlineWriteConfigs (mlir::ModuleOp module)
mlir::LogicalResult	generateAndInsertTeardownOps (mlir::OpBuilder &builder, xilinx::AIE::DeviceOp device, xilinx::AIEX::BlockwriteData &blockwriteData, AIEToConfigurationOutputType outputType=AIEToConfigurationOutputType::Transaction)
bool	hasFlag (ResetTileType value, ResetTileType flag)
mlir::LogicalResult	generateAndInsertResetOps (mlir::OpBuilder &builder, xilinx::AIE::DeviceOp device, ResetConfig dmaConfig, ResetConfig switchConfig, ResetConfig lockConfig, ResetConfig coreConfig, xilinx::AIE::DeviceOp previousDevice)
MemoryRun	largestFreeRunIn (MemoryRun window, llvm::SmallVector< std::pair< int64_t, int64_t > > occupied, int64_t alignBytes=1)
MemoryRun	largestFreeRun (int64_t memSize, llvm::SmallVector< std::pair< int64_t, int64_t > > occupied, int64_t alignBytes=1)
std::string	coreFrameSymbolName (int col, int row)
std::string	bankSectionName (int bank)
std::string	bankRegionName (int bank)
char	bankLetter (int bank)
uint32_t	getShimBurstLengthBytes (const AIE::AIETargetModel &tm, uint32_t burstLength)
uint32_t	getShimBurstLengthEncoding (const AIE::AIETargetModel &tm, uint32_t burstLength)
mlir::Operation *	lookupNamedOpIn (mlir::Operation *symbolTableOp, mlir::StringAttr name)
mlir::Operation *	lookupNamedOpIn (mlir::Operation *symbolTableOp, llvm::StringRef name)
mlir::Operation *	lookupNamedOp (mlir::Operation *from, mlir::StringAttr name)
mlir::Operation *	lookupNamedOp (mlir::Operation *from, llvm::StringRef name)
template<typename OpTy, typename NameT>
OpTy	lookupNamedOpIn (mlir::Operation *symbolTableOp, NameT name)
template<typename OpTy, typename NameT>
OpTy	lookupNamedOp (mlir::Operation *from, NameT name)
mlir::LogicalResult	verifyOffsetSizeAndStrideOp (mlir::OffsetSizeAndStrideOpInterface op)
mlir::ParseResult	parseTypedDynamicIndexList (mlir::OpAsmParser &parser, llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &values, mlir::DenseI64ArrayAttr &integers, llvm::SmallVectorImpl< mlir::Type > &types)
void	printTypedDynamicIndexList (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::OperandRange values, llvm::ArrayRef< int64_t > integers, mlir::TypeRange types)
mlir::LogicalResult	myVerifyOffsetSizeAndStrideOp (mlir::OffsetSizeAndStrideOpInterface op)
void	registerAIETranslations ()
WireBundle	getConnectingBundle (WireBundle dir)
std::optional< std::pair< TileID, Port > >	getConnectingWireEndpoint (const AIETargetModel &targetModel, TileID tile, Port port)
const AIETargetModel &	getTargetModel (mlir::Operation *op)
const AIETargetModel &	getTargetModel (AIEDevice device)
AIETargetModel::SharedMemory	sharedMemory (TileOp a, TileOp b)
	Which of a's and b's memory modules both tiles can address.
mlir::ParseResult	parseObjectFifoProducerTile (mlir::OpAsmParser &parser, mlir::OpAsmParser::UnresolvedOperand &operand, BDDimLayoutArrayAttr &dimensions)
void	printObjectFifoProducerTile (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::Value operand, BDDimLayoutArrayAttr dimensions)
mlir::ParseResult	parseDMAStartChannel (mlir::OpAsmParser &parser, mlir::Attribute &channel)
void	printDMAStartChannel (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::Attribute channel)
mlir::ParseResult	parseObjectFifoAcquireObjects (mlir::OpAsmParser &parser, ObjectFifoPortAttr &port, llvm::SmallVectorImpl< mlir::Type > &objects)
void	printObjectFifoAcquireObjects (mlir::OpAsmPrinter &printer, mlir::Operation *op, ObjectFifoPortAttr port, mlir::TypeRange objects)
mlir::ParseResult	parseObjectFifoReleaseCount (mlir::OpAsmParser &parser, ObjectFifoPortAttr &port, mlir::IntegerAttr &size)
void	printObjectFifoReleaseCount (mlir::OpAsmPrinter &printer, mlir::Operation *op, ObjectFifoPortAttr port, mlir::IntegerAttr size)
mlir::ParseResult	parseObjectFifoConsumerTiles (mlir::OpAsmParser &parser, llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &tiles, BDDimLayoutArrayArrayAttr &dimensions)
void	printObjectFifoConsumerTiles (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::OperandRange tiles, BDDimLayoutArrayArrayAttr dimsPerTileAttr)
mlir::ParseResult	parseFlowVias (mlir::OpAsmParser &parser, llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &vias, mlir::DenseI32ArrayAttr &ingressBundles, mlir::DenseI32ArrayAttr &ingressChannels, mlir::DenseI32ArrayAttr &egressBundles, mlir::DenseI32ArrayAttr &egressChannels)
void	printFlowVias (mlir::OpAsmPrinter &printer, mlir::Operation *op, mlir::OperandRange vias, mlir::DenseI32ArrayAttr ingressBundles, mlir::DenseI32ArrayAttr ingressChannels, mlir::DenseI32ArrayAttr egressBundles, mlir::DenseI32ArrayAttr egressChannels)
int32_t	getBufferBaseAddress (mlir::Operation *bufOp)
mlir::ParseResult	parseTraceEvent (mlir::AsmParser &parser, mlir::Attribute &result)
void	printTraceEventEnum (mlir::AsmPrinter &printer, mlir::Attribute attr)
llvm::SmallVector< ObjectFifoDmaEndpointOp >	turnEndpoints (ObjectFifoDmaEndpointOp end)
int64_t	turnPasses (llvm::ArrayRef< std::pair< int64_t, int64_t > > ends)
bool	keepsPktHeader (TileID tile, Port master, std::optional< bool > keep)
bool	isDirectional (WireBundle bundle)
void	collectTiles (DeviceOp &device, llvm::DenseMap< TileID, mlir::Operation * > &tiles)
void	collectBuffers (DeviceOp &device, llvm::DenseMap< mlir::Operation *, llvm::SmallVector< BufferOp, 4 > > &buffers)
bool	isContiguousBDTransfer (llvm::ArrayRef< BDDimLayoutAttr > dims)
int64_t	paddedSize (llvm::ArrayRef< BDDimLayoutAttr > dims, llvm::ArrayRef< BDPadLayoutAttr > pads, int64_t fallback)
std::optional< llvm::SmallVector< BDDimLayoutAttr > >	normalizedBDDims (llvm::ArrayRef< BDDimLayoutAttr > dims, int64_t len)
mlir::FailureOr< int64_t >	getLengthUnitBytes (mlir::Operation *op, int64_t lengthUnit, mlir::BaseMemRefType buffer)
mlir::LogicalResult	verifyLengthParameter (mlir::Operation *op, std::optional< int64_t > lengthUnit, mlir::BaseMemRefType buffer, std::optional< int64_t > lenElems, bool contiguous, llvm::ArrayRef< int64_t > innerSizes)
void	placeRuntimeLengthDimension (llvm::MutableArrayRef< int64_t > sizes, llvm::MutableArrayRef< int64_t > strides)
mlir::LogicalResult	verifyLengthParameterTile (mlir::Operation *op, const AIETargetModel &targetModel, int col, int row)
mlir::LogicalResult	verifyDMABDOutOfOrderId (DMABDOp bd, bool packetEnabledByContext=false)
mlir::LogicalResult	verifyDMABDIteration (DMABDOp bd, AIETileType tileType)
mlir::LogicalResult	verifyAssignedPacket (mlir::Operation *op, PacketInfoAttr packet, llvm::StringRef what="packet")
mlir::LogicalResult	verifyOutOfOrderChannel (mlir::Operation *op, DMAChannelDir dir, bool outOfOrder, llvm::ArrayRef< DMABDOp > bds, bool packetEnabledByContext=false)
mlir::LogicalResult	verifyBdLockPair (mlir::Block &block, bool outOfOrder, UseLockOp &acquire, UseLockOp &release)
mlir::LogicalResult	inferStreamWindow (llvm::ArrayRef< BDDimLayoutAttr > dims, llvm::ArrayRef< BDPadLayoutAttr > pads, int64_t objectSize, llvm::function_ref< mlir::InFlightDiagnostic()> emitError, StreamWindow &window)
llvm::SmallVector< StreamWindowStep >	streamWindowSteps (const StreamWindow &w)
llvm::SmallVector< uint32_t >	getAssignedBdIds (DmaBody program)
mlir::LogicalResult	verifyDMAChannelsResolved (DeviceOp device)
uint8_t	txnDeviceGen (const AIETargetModel &tm)
	Device generation ID written into the TXN header (aie_runtime::TxnDeviceInfo::devGen).
TileMemoryLimits	tileMemoryLimits (const AIETargetModel &targetModel, AIETileType tileType)
uint32_t	requiredBufferAlignBits (uint32_t busAlignBits, uint32_t maxVecAlignBits, int64_t sizeBytes)
	Return the alignment (in bits) a buffer of sizeBytes must satisfy.
int64_t	assignSequentialBufferAddresses (llvm::MutableArrayRef< BufferAllocation > buffers, int64_t start=0)
	The basic address allocator and resource planner share this layout: retain address pins, then place unpinned buffers largest-first, aligning each start and skipping occupied ranges.
bool	isForeverLoop (mlir::scf::WhileOp whileOp)
	Whether whileOp repeats forever: its condition is a constant true, and its condition region does nothing but forward its arguments to the body.
bool	isObjectFifoLoop (mlir::Operation *op)
	Whether op is a loop that objectFifo lowering unrolls by the rotation period of the objectFifos accessed in it: an scf.for, or an scf.while that repeats forever.
mlir::Operation *	getObjectFifoLoopParent (mlir::Operation *op)
	The innermost loop around op that isObjectFifoLoop accepts, or null.
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEPlaceTilesPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEPlaceTilesPass (const AIEPlaceTilesOptions &options)
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEPrepareBuffersPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEAssignBufferAddressesPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEAssignBufferAddressesPass (const AIEAssignBufferAddressesOptions &options)
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEAssignCoreLinkFilesPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEAssignLockIDsPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIENormalizeDmaBdDimsPass ()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > >	createAIECanonicalizeDevicePass ()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > >	createAIECoreToStandardPass ()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > >	createAIECoreToStandardPass (const AIECoreToStandardOptions &options)
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEFindFlowsPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIESplitFlowViasPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIELocalizeLocksPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIENormalizeAddressSpacesPass ()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > >	createAIERouteFlowsPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEVectorToPointerLoopsPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEVectorTransferLoweringPass ()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > >	createAIEHoistVectorTransferPointersPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIECoreIntRangeNarrowingPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEPathfinderPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEPathfinderPass (const AIERoutePathfinderFlowsOptions &options)
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEObjectFifoUnrollPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEObjectFifoUnrollPass (const AIEObjectFifoUnrollOptions &options)
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEObjectFifoSplitPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEObjectFifoVerifyPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEAssignPacketIdsPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEAssignPacketIdsPass (bool packetSwitched)
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEObjectFifoAllocatePass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEObjectFifoLowerDMAsPass ()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > >	createAIECheckAgainstImagePass ()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > >	createAIECheckAgainstImagePass (const AIECheckAgainstImageOptions &options)
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEObjectFifoLowerCoresPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEObjectFifoErasePoolsPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIELowerCascadeFlowsPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEAssignBufferDescriptorIDsPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEObjectFifoLivenessPass ()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > >	createAIEGenerateColumnControlOverlayPass ()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > >	createAIEGenerateColumnControlOverlayPass (const AIEGenerateColumnControlOverlayOptions &options)
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEAssignTileCtrlIDsPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIETraceToConfigPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIETraceRegPackWritesPass ()
std::unique_ptr< mlir::OperationPass< DeviceOp > >	createAIEInsertTraceFlowsPass ()
void	addObjectFifoLoweringPasses (mlir::OpPassManager &pm, bool packetSwitched, bool skipVerify)
	Adds the passes of aie-objectFifo-stateful-transform to pm, which anchors on DeviceOp.
void	registerAIEObjectFifoPipeline ()
	Register aie-objectFifo-stateful-transform as a pipeline over the passes that lower aie.objectfifo.
int	shimMuxChannelFrom (Port src)
int	shimMuxChannelTo (Port dst)
llvm::raw_ostream &	operator<< (llvm::raw_ostream &os, const SwitchSettings &ss)
std::pair< int, int >	getDMACapacity (const AIETargetModel &tm, TileID tile)
	Get DMA channel capacity (maxIn, maxOut) for a tile position.
template<typename F>
void	forEachPeer (mlir::Operation *op, const Placer::Adjacency &adjacency, F &&fn)
bool	isSharedComputeMemory (const AIETargetModel &targetModel, TileID a, TileID b)
template<typename F>
void	forEachMemAffinityNeighbor (const AIETargetModel &targetModel, TileID at, F &&fn)
std::string	describePort (Port port)
	Names a port the way diagnostics do, e.g. "DMA:1".
std::string	describeTilePort (TileID tile, Port port)
	Names a tile port the way diagnostics do, e.g. "(0, 2) DMA:1".
std::string	joinNames (llvm::ArrayRef< std::string > names, size_t shown=4)
	Lists names as "A, B and C", the first shown of them followed by "N more" if there are more.
std::string	describePrioritized (llvm::ArrayRef< std::string > sources)
	Says that the packet flows from sources keep the route they take alone, as a control-packet reload of a design they are prioritized in asks.
std::vector< RoutedStream >	traceRoutedStreams (DeviceOp device)
	Follows every stream from its source tile port through the configured switchboxes, using tile geometry for the links between them.
std::vector< RoutedStream >	requestedStreams (DeviceOp device)
	The streams the aie.flow and aie.packet_flow ops ask for, one per source, destination and packet id, before any of them is routed.
std::string	describeStream (const RoutedStream &stream)
	Names the stream by its endpoints and packet id, e.g.
void	emitNpuLocmapJSON (llvm::raw_ostream &output, llvm::StringRef deviceName, llvm::StringRef binaryName, const std::vector< TxnLocEntry > &locmap)
mlir::LogicalResult	AIETranslateToXAIEV2 (mlir::ModuleOp module, llvm::raw_ostream &output, llvm::StringRef deviceName="")
mlir::LogicalResult	AIEFlowsToJSON (mlir::ModuleOp module, llvm::raw_ostream &output, llvm::StringRef deviceName="")
mlir::LogicalResult	AIETranslateSCSimConfig (mlir::ModuleOp module, llvm::raw_ostream &output, llvm::StringRef deviceName="")
mlir::LogicalResult	AIETranslateShimSolution (mlir::ModuleOp module, llvm::raw_ostream &, llvm::StringRef deviceName="")
mlir::LogicalResult	AIETranslateGraphXPE (mlir::ModuleOp module, llvm::raw_ostream &, llvm::StringRef)
mlir::LogicalResult	AIETranslateNpuToBinary (mlir::ModuleOp, std::vector< uint32_t > &, llvm::StringRef deviceName="", llvm::StringRef sequenceName="", std::vector< TxnLocEntry > *locmap=nullptr, bool foldDDRAddrOffset=true, NpuConfigCache *configs=nullptr)
mlir::LogicalResult	AIETranslateNpuToCpp (mlir::ModuleOp module, llvm::raw_ostream &output, bool foldDDRAddrOffset=true, bool emitDispatchShim=false)
	Emit a C++ builder that reconstructs the TXN stream at runtime.
mlir::LogicalResult	AIETranslateToUcDma (mlir::ModuleOp module, llvm::raw_ostream &output)
mlir::LogicalResult	AIETranslateToUcDma (mlir::ModuleOp module, std::string &assembly, llvm::StringRef outputPath="")
mlir::LogicalResult	AIETranslateControlPacketsToUI32Vec (mlir::ModuleOp, std::vector< uint32_t > &, llvm::StringRef deviceName="", llvm::StringRef sequenceName="", std::vector< TxnLocEntry > *locmap=nullptr)
mlir::LogicalResult	AIETranslateToLdScript (mlir::ModuleOp module, llvm::raw_ostream &output, int tileCol, int tileRow, llvm::StringRef deviceName="", bool probe=false, llvm::function_ref< std::string(llvm::StringRef)> resolveLinkFile=nullptr)
mlir::LogicalResult	AIETranslateToBCF (mlir::ModuleOp module, llvm::raw_ostream &output, int tileCol, int tileRow, llvm::StringRef deviceName="")
mlir::LogicalResult	AIELLVMLink (llvm::raw_ostream &output, const std::vector< std::string > &Files, bool DisableDITypeMap=false, bool NoVerify=false, bool Internalize=false, bool OnlyNeeded=false, bool PreserveAssemblyUseListOrder=false, bool Verbose=false)
mlir::LogicalResult	AIETranslateToCDODirect (mlir::ModuleOp m, llvm::StringRef workDirPath, llvm::StringRef deviceName, bool bigEndian=false, bool emitUnified=false, bool cdoDebug=false, bool aieSim=false, bool xaieDebug=false, bool enableCores=true)
mlir::LogicalResult	AIETranslateToTargetArch (mlir::ModuleOp module, llvm::raw_ostream &output, llvm::StringRef deviceName)
std::string	tileLocStr (llvm::StringRef col, llvm::StringRef row)
std::string	tileLocStr (int col, int row)
std::string	tileDMAInstStr (llvm::StringRef col, llvm::StringRef row, llvm::StringRef bdNum)
std::string	tileDMAInstStr (int col, int row, int bdNum)
std::string	tileDMAInstRefStr (llvm::StringRef col, llvm::StringRef row, llvm::StringRef bdNum)
std::string	tileDMAInstRefStr (int col, int row, int bdNum)
std::string	packetStr (llvm::StringRef id, llvm::StringRef type)
std::string	packetStr (int id, int type)
void	generateXAieDmaSetMultiDimAddr (llvm::raw_ostream &output, int ndims, llvm::ArrayRef< BDDimLayoutAttr > dims, int col, int row, int bdNum, int baseAddrA, int64_t offsetA, uint32_t lenA, int elementWidthInBytes, const char *errorRet)
llvm::SetVector< mlir::Block * >	getOrderedChainOfBlocks (mlir::Region *region)
llvm::SmallPtrSet< mlir::Block *, 8 >	collectOutOfOrderBlocks (const llvm::SetVector< mlir::Block * > &blockVector)
	Collect every BD block reached from an out-of-order aie.dma_start channel.
std::optional< std::vector< char > >	denseAttrToBytes (mlir::DenseElementsAttr denseInit)
	A buffer's initial_value as the bytes to write to its tile memory, in element order.
MemoryRun	coreDataRegion (TileOp tile, llvm::ArrayRef< BufferOp > buffers)
	The extent the core compiler gets for its own .data, .rodata and .bss, tile-relative.
llvm::SmallVector< MemoryRun >	coreBankRegions (TileOp tile, llvm::ArrayRef< BufferOp > buffers, MemoryRun dataRun)
	One extent per memory bank for the core's bank-pinned statics, tile-relative and indexed by bank.
mlir::LogicalResult	AIEFlowsToJSON (ModuleOp module, raw_ostream &output, llvm::StringRef deviceName)
LogicalResult	AIETranslateToBCF (ModuleOp module, raw_ostream &output, int tileCol, int tileRow, llvm::StringRef deviceName)
LogicalResult	AIETranslateToTargetArch (ModuleOp module, raw_ostream &output, llvm::StringRef deviceName)
std::string	tileLocStr (StringRef col, StringRef row)
std::string	tileDMAInstStr (StringRef col, StringRef row, StringRef bdNum)
std::string	tileDMAInstRefStr (StringRef col, StringRef row, StringRef bdNum)
std::string	packetStr (StringRef id, StringRef type)
void	generateXAieDmaSetMultiDimAddr (raw_ostream &output, int ndims, ArrayRef< BDDimLayoutAttr > dims, int col, int row, int bdNum, int baseAddrA, int64_t offsetA, uint32_t lenA, int elementWidthInBytes, const char *errorRetval)
llvm::SetVector< Block * >	getOrderedChainOfBlocks (Region *region)
llvm::SmallPtrSet< Block *, 8 >	collectOutOfOrderBlocks (const llvm::SetVector< Block * > &blockVector)

Variables
constexpr llvm::StringLiteral	kObjectFifoUnrollHintAttrName
	Discardable attribute set by --aie-objectfifo-lower-cores on scf.for and forever scf.while loops containing ObjectFifo accesses – the loop unroll factor (the least common multiple of the depths of the objectFifos accessed within the loop) consumed by the AIEObjectFifoUnroll pass.
constexpr llvm::StringLiteral	kObjectFifoObjectSlotAttrName
	Discardable attribute set by --aie-objectfifo-lower-cores on the rank-0 memref.allocas that hold a core's objects of an objectFifo in rotation order.

Typedef Documentation

Connect

using xilinx::AIE::Connect

Initial value:

 struct Connect {
  Port src;
  Port dst;
 
  bool operator==(const Connect &rhs) const {
    return std::tie(src, dst) == std::tie(rhs.src, rhs.dst);
  }
 
  bool operator!=(const Connect &rhs) const { return !(*this == rhs); }
 
  bool operator<(const Connect &rhs) const {
    return std::tie(src, dst) < std::tie(rhs.src, rhs.dst);
  }
}

Definition at line 299 of file AIEDialect.h.

DMAChannel

using xilinx::AIE::DMAChannel

Initial value:

 struct DMAChannel {
  DMAChannelDir direction;
  int channel;
 
  bool operator==(const DMAChannel &rhs) const {
    return std::tie(direction, channel) == std::tie(rhs.direction, rhs.channel);
  }
}

Definition at line 314 of file AIEDialect.h.

PacketConflict

using xilinx::AIE::PacketConflict

Initial value:

 
    std::function<bool(const PathEndPoint &, const std::set<int> &,
                       const PathEndPoint &, const std::set<int> &)>

Definition at line 230 of file AIEPathFinder.h.

PacketsApartAcross

using xilinx::AIE::PacketsApartAcross

Initial value:

 std::function<PacketsApart(
    llvm::function_ref<bool(TileID)> low, bool up, size_t limit)>

Definition at line 242 of file AIEPathFinder.h.

PacketTrees

using xilinx::AIE::PacketTrees = std::map<PathEndPoint, std::vector<TreeHop>>

Definition at line 226 of file AIEPathFinder.h.

PlacementResult

using xilinx::AIE::PlacementResult = llvm::DenseMap<mlir::Operation *, TileID>

Definition at line 50 of file AIEPlacer.h.

Port

using xilinx::AIE::Port

Initial value:

 struct Port {
  WireBundle bundle;
  int channel;
 
  bool operator==(const Port &rhs) const {
    return std::tie(bundle, channel) == std::tie(rhs.bundle, rhs.channel);
  }
 
  bool operator!=(const Port &rhs) const { return !(*this == rhs); }
 
  bool operator<(const Port &rhs) const {
    return std::tie(bundle, channel) < std::tie(rhs.bundle, rhs.channel);
  }
 
  friend std::ostream &operator<<(std::ostream &os, const Port &port) {
    os << "(";
    os << stringifyWireBundle(port.bundle).str();
    os << ": " << std::to_string(port.channel) << ")";
    return os;
  }
 
 
 
  friend llvm::raw_ostream &operator<<(llvm::raw_ostream &os,
                                       const Port &port) {
    os << to_string(port);
    return os;
  }
}

Definition at line 265 of file AIEDialect.h.

RoutingCheck

using xilinx::AIE::RoutingCheck = std::function<llvm::Error(const Routing &)>

Definition at line 334 of file AIEPathFinder.h.

SwitchSettings

using xilinx::AIE::SwitchSettings = std::map<TileID, SwitchSetting>

Definition at line 206 of file AIEPathFinder.h.

TileID

using xilinx::AIE::TileID

Definition at line 23 of file AIETargetModel.h.

Enumeration Type Documentation

AIEToConfigurationOutputType

enum xilinx::AIE::AIEToConfigurationOutputType

Enumerator
Transaction
ControlPacket

Definition at line 28 of file AIEToConfiguration.h.

PlacerType

enum class xilinx::AIE::PlacerType

strong

Placement algorithm type for pass option.

Enumerator
SequentialPlacer
SAPlacer

Definition at line 22 of file AIEPlacer.h.

ResetMode

enum class xilinx::AIE::ResetMode

strong

Enumerator
Never
IfUsed
IfUsedFineGrained
IfChanged
IfChangedFineGrained
Always

Definition at line 93 of file AIEToConfiguration.h.

ResetTileType

enum class xilinx::AIE::ResetTileType : unsigned

strong

Enumerator
None
ShimNOC
MemTile
CoreTile
All

Definition at line 80 of file AIEToConfiguration.h.

Function Documentation

addObjectFifoLoweringPasses()

void xilinx::AIE::addObjectFifoLoweringPasses	(	mlir::OpPassManager &	pm,
		bool	packetSwitched,
		bool	skipVerify )

Adds the passes of aie-objectFifo-stateful-transform to pm, which anchors on DeviceOp.

Referenced by registerAIEObjectFifoPipeline().

AIEFlowsToJSON() [1/2]

mlir::LogicalResult xilinx::AIE::AIEFlowsToJSON	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output,
		llvm::StringRef	deviceName = "" )

Referenced by registerAIETranslations().

AIEFlowsToJSON() [2/2]

mlir::LogicalResult xilinx::AIE::AIEFlowsToJSON	(	ModuleOp	module,
		raw_ostream &	output,
		llvm::StringRef	deviceName )

Definition at line 423 of file AIEFlowsToJSON.cpp.

AIELLVMLink()

mlir::LogicalResult xilinx::AIE::AIELLVMLink	(	llvm::raw_ostream &	output,
		const std::vector< std::string > &	Files,
		bool	DisableDITypeMap = false,
		bool	NoVerify = false,
		bool	Internalize = false,
		bool	OnlyNeeded = false,
		bool	PreserveAssemblyUseListOrder = false,
		bool	Verbose = false )

Definition at line 121 of file AIELLVMLink.cpp.

Referenced by aieLLVMLink().

AIETranslateControlPacketsToUI32Vec()

mlir::LogicalResult xilinx::AIE::AIETranslateControlPacketsToUI32Vec	(	mlir::ModuleOp	,
		std::vector< uint32_t > &	,
		llvm::StringRef	deviceName = "",
		llvm::StringRef	sequenceName = "",
		std::vector< TxnLocEntry > *	locmap = nullptr )

Referenced by aieTranslateControlPacketsToUI32Vec(), and registerAIETranslations().

AIETranslateGraphXPE()

mlir::LogicalResult xilinx::AIE::AIETranslateGraphXPE	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output,
		llvm::StringRef	deviceName )

Definition at line 214 of file AIETargetSimulationFiles.cpp.

References xilinx::AIE2.

Referenced by registerAIETranslations().

AIETranslateNpuToBinary()

mlir::LogicalResult xilinx::AIE::AIETranslateNpuToBinary	(	mlir::ModuleOp	,
		std::vector< uint32_t > &	,
		llvm::StringRef	deviceName = "",
		llvm::StringRef	sequenceName = "",
		std::vector< TxnLocEntry > *	locmap = nullptr,
		bool	foldDDRAddrOffset = true,
		NpuConfigCache *	configs = nullptr )

Referenced by aieTranslateNpuToBinary(), and registerAIETranslations().

AIETranslateNpuToCpp()

mlir::LogicalResult xilinx::AIE::AIETranslateNpuToCpp	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output,
		bool	foldDDRAddrOffset = true,
		bool	emitDispatchShim = false )

Emit a C++ builder that reconstructs the TXN stream at runtime.

Parameters

foldDDRAddrOffset	apply firmware DDR folding; see aie/Runtime/TxnEncoding.h for the runtime-specific address convention.
emitDispatchShim	also emit the extern "C" dispatch_abi() / dispatch_generate() entry points the JIT dispatch bridge loads via ctypes.

Referenced by registerAIETranslations().

AIETranslateSCSimConfig()

mlir::LogicalResult xilinx::AIE::AIETranslateSCSimConfig	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output,
		llvm::StringRef	deviceName = "" )

Definition at line 20 of file AIETargetSimulationFiles.cpp.

References xilinx::AIE2.

Referenced by registerAIETranslations().

AIETranslateShimSolution()

mlir::LogicalResult xilinx::AIE::AIETranslateShimSolution	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output,
		llvm::StringRef	deviceName = "" )

Definition at line 153 of file AIETargetSimulationFiles.cpp.

References verifyDMAChannelsResolved().

Referenced by registerAIETranslations().

AIETranslateToBCF() [1/2]

mlir::LogicalResult xilinx::AIE::AIETranslateToBCF	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output,
		int	tileCol,
		int	tileRow,
		llvm::StringRef	deviceName = "" )

Referenced by aieTranslateToBCF(), and registerAIETranslations().

AIETranslateToBCF() [2/2]

LogicalResult xilinx::AIE::AIETranslateToBCF	(	ModuleOp	module,
		raw_ostream &	output,
		int	tileCol,
		int	tileRow,
		llvm::StringRef	deviceName )

Definition at line 31 of file AIETargetBCF.cpp.

References collectBuffers(), collectTiles(), coreFrameSymbolName(), getBufferBaseAddress(), getTargetModel(), xilinx::AIE::MemoryRun::size, and xilinx::AIE::MemoryRun::start.

AIETranslateToCDODirect()

mlir::LogicalResult xilinx::AIE::AIETranslateToCDODirect	(	mlir::ModuleOp	m,
		llvm::StringRef	workDirPath,
		llvm::StringRef	deviceName,
		bool	bigEndian = false,
		bool	emitUnified = false,
		bool	cdoDebug = false,
		bool	aieSim = false,
		bool	xaieDebug = false,
		bool	enableCores = true )

Referenced by aieTranslateToCDODirect(), and registerAIETranslations().

AIETranslateToLdScript()

mlir::LogicalResult xilinx::AIE::AIETranslateToLdScript	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output,
		int	tileCol,
		int	tileRow,
		llvm::StringRef	deviceName = "",
		bool	probe = false,
		llvm::function_ref< std::string(llvm::StringRef)>	resolveLinkFile = nullptr )

Referenced by registerAIETranslations().

AIETranslateToTargetArch() [1/2]

mlir::LogicalResult xilinx::AIE::AIETranslateToTargetArch	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output,
		llvm::StringRef	deviceName )

Referenced by registerAIETranslations().

AIETranslateToTargetArch() [2/2]

LogicalResult xilinx::AIE::AIETranslateToTargetArch	(	ModuleOp	module,
		raw_ostream &	output,
		llvm::StringRef	deviceName )

Definition at line 111 of file AIETargets.cpp.

AIETranslateToUcDma() [1/2]

mlir::LogicalResult xilinx::AIE::AIETranslateToUcDma	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output )

Referenced by registerAIETranslations().

AIETranslateToUcDma() [2/2]

mlir::LogicalResult xilinx::AIE::AIETranslateToUcDma	(	mlir::ModuleOp	module,
		std::string &	assembly,
		llvm::StringRef	outputPath = "" )

AIETranslateToXAIEV2()

mlir::LogicalResult xilinx::AIE::AIETranslateToXAIEV2	(	mlir::ModuleOp	module,
		llvm::raw_ostream &	output,
		llvm::StringRef	deviceName = "" )

Referenced by aieTranslateToXAIEV2(), and registerAIETranslations().

assignSequentialBufferAddresses()

int64_t xilinx::AIE::assignSequentialBufferAddresses ( llvm::MutableArrayRef< BufferAllocation > buffers, int64_t start = 0 )

inline

The basic address allocator and resource planner share this layout: retain address pins, then place unpinned buffers largest-first, aligning each start and skipping occupied ranges.

Return the high-water mark, without padding after the final buffer. Entries retain their input order.

Definition at line 70 of file AIEBufferAllocation.h.

bankLetter()

char xilinx::AIE::bankLetter ( int bank )

inline

Definition at line 42 of file AIECoreSymbols.h.

bankRegionName()

std::string xilinx::AIE::bankRegionName ( int bank )

inline

Definition at line 37 of file AIECoreSymbols.h.

bankSectionName()

std::string xilinx::AIE::bankSectionName ( int bank )

inline

Definition at line 33 of file AIECoreSymbols.h.

collectBuffers()

void xilinx::AIE::collectBuffers	(	DeviceOp &	device,
		llvm::DenseMap< mlir::Operation *, llvm::SmallVector< BufferOp, 4 > > &	buffers )

Referenced by AIETranslateToBCF(), and registerAIETranslations().

collectOutOfOrderBlocks() [1/2]

llvm::SmallPtrSet< Block *, 8 > xilinx::AIE::collectOutOfOrderBlocks

(

const llvm::SetVector< Block * > &

blockVector

)

Definition at line 161 of file AIETargetShared.cpp.

collectOutOfOrderBlocks() [2/2]

llvm::SmallPtrSet< mlir::Block *, 8 > xilinx::AIE::collectOutOfOrderBlocks

(

const llvm::SetVector< mlir::Block * > &

blockVector

)

Collect every BD block reached from an out-of-order aie.dma_start channel.

These BDs use use_next_bd=0 (placement is by header id, not the chain).

Referenced by xilinx::AIE::AIERTControl::addInitConfig().

collectTiles()

void xilinx::AIE::collectTiles	(	DeviceOp &	device,
		llvm::DenseMap< TileID, mlir::Operation * > &	tiles )

Referenced by AIETranslateToBCF(), and registerAIETranslations().

convertTransactionBinaryToMLIR()

std::optional< mlir::ModuleOp > xilinx::AIE::convertTransactionBinaryToMLIR	(	mlir::MLIRContext *	ctx,
		std::vector< uint8_t > &	binary )

Definition at line 730 of file AIEToConfiguration.cpp.

References Transaction.

Referenced by aieTranslateBinaryToTxn().

coreBankRegions()

llvm::SmallVector< MemoryRun > xilinx::AIE::coreBankRegions	(	TileOp	tile,
		llvm::ArrayRef< BufferOp >	buffers,
		MemoryRun	dataRun )

One extent per memory bank for the core's bank-pinned statics, tile-relative and indexed by bank.

Each is the largest run that bank has left once the stack, the buffers and dataRun are accounted for, so a bank with nothing spare yields a zero-sized extent rather than dropping out.

Pass an empty dataRun when no data reservation exists; the linker then bounds ordinary data using the actual bank-section extents.

Definition at line 245 of file AIETargetShared.cpp.

References xilinx::AIE::MemoryRun::end(), getBufferBaseAddress(), getTargetModel(), largestFreeRunIn(), xilinx::AIE::MemoryRun::size, and xilinx::AIE::MemoryRun::start.

coreDataRegion()

MemoryRun xilinx::AIE::coreDataRegion	(	TileOp	tile,
		llvm::ArrayRef< BufferOp >	buffers )

The extent the core compiler gets for its own .data, .rodata and .bss, tile-relative.

A core_data buffer among buffers fixes the extent; otherwise it is the largest run the buffers leave above the stack.

The linker script emitter and the aiecc driver both need this, so a diagnostic about the region names the bytes the script grants.

Definition at line 218 of file AIETargetShared.cpp.

References xilinx::AIE::MemoryRun::end(), getBufferBaseAddress(), getTargetModel(), largestFreeRun(), and xilinx::AIE::MemoryRun::start.

coreFrameSymbolName()

std::string xilinx::AIE::coreFrameSymbolName ( int col, int row )

inline

Definition at line 24 of file AIECoreSymbols.h.

Referenced by AIETranslateToBCF().

createAIEAssignBufferAddressesPass() [1/2]

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignBufferAddressesPass

(

)

Definition at line 1683 of file AIEAssignBuffers.cpp.

createAIEAssignBufferAddressesPass() [2/2]

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignBufferAddressesPass

(

const AIEAssignBufferAddressesOptions &

options

)

Definition at line 1688 of file AIEAssignBuffers.cpp.

createAIEAssignBufferDescriptorIDsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignBufferDescriptorIDsPass

(

)

Definition at line 353 of file AIEAssignBufferDescriptorIDs.cpp.

createAIEAssignCoreLinkFilesPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignCoreLinkFilesPass

(

)

Definition at line 219 of file AIEAssignCoreLinkFiles.cpp.

createAIEAssignLockIDsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignLockIDsPass

(

)

Definition at line 105 of file AIEAssignLockIDs.cpp.

createAIEAssignPacketIdsPass() [1/2]

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignPacketIdsPass

(

)

Definition at line 102 of file AIEAssignPacketIds.cpp.

createAIEAssignPacketIdsPass() [2/2]

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignPacketIdsPass

(

bool

packetSwitched

)

Definition at line 107 of file AIEAssignPacketIds.cpp.

createAIEAssignTileCtrlIDsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEAssignTileCtrlIDsPass

(

)

Definition at line 929 of file AIEGenerateColumnControlOverlay.cpp.

createAIECanonicalizeDevicePass()

std::unique_ptr< OperationPass< ModuleOp > > xilinx::AIE::createAIECanonicalizeDevicePass

(

)

Definition at line 60 of file AIECanonicalizeDevice.cpp.

createAIECheckAgainstImagePass() [1/2]

std::unique_ptr< OperationPass< ModuleOp > > xilinx::AIE::createAIECheckAgainstImagePass

(

)

Definition at line 399 of file AIECheckAgainstImage.cpp.

createAIECheckAgainstImagePass() [2/2]

std::unique_ptr< OperationPass< ModuleOp > > xilinx::AIE::createAIECheckAgainstImagePass

(

const AIECheckAgainstImageOptions &

options

)

Definition at line 404 of file AIECheckAgainstImage.cpp.

createAIECoreIntRangeNarrowingPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIECoreIntRangeNarrowingPass

(

)

Definition at line 126 of file AIECoreIntRangeNarrowing.cpp.

createAIECoreToStandardPass() [1/2]

std::unique_ptr< OperationPass< ModuleOp > > xilinx::AIE::createAIECoreToStandardPass

(

)

Definition at line 813 of file AIECoreToStandard.cpp.

createAIECoreToStandardPass() [2/2]

std::unique_ptr< OperationPass< ModuleOp > > xilinx::AIE::createAIECoreToStandardPass

(

const AIECoreToStandardOptions &

options

)

Definition at line 818 of file AIECoreToStandard.cpp.

createAIEFindFlowsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEFindFlowsPass

(

)

Definition at line 1202 of file AIEFindFlows.cpp.

createAIEGenerateColumnControlOverlayPass() [1/2]

std::unique_ptr< OperationPass< mlir::ModuleOp > > xilinx::AIE::createAIEGenerateColumnControlOverlayPass

(

)

Definition at line 934 of file AIEGenerateColumnControlOverlay.cpp.

createAIEGenerateColumnControlOverlayPass() [2/2]

std::unique_ptr< OperationPass< mlir::ModuleOp > > xilinx::AIE::createAIEGenerateColumnControlOverlayPass

(

const AIEGenerateColumnControlOverlayOptions &

options

)

Definition at line 939 of file AIEGenerateColumnControlOverlay.cpp.

createAIEHoistVectorTransferPointersPass()

std::unique_ptr< OperationPass< ModuleOp > > xilinx::AIE::createAIEHoistVectorTransferPointersPass

(

)

Definition at line 611 of file AIEHoistVectorTransferPointers.cpp.

createAIEInsertTraceFlowsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEInsertTraceFlowsPass

(

)

Definition at line 1216 of file AIEInsertTraceFlows.cpp.

createAIELocalizeLocksPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIELocalizeLocksPass

(

)

Definition at line 92 of file AIELocalizeLocks.cpp.

createAIELowerCascadeFlowsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIELowerCascadeFlowsPass

(

)

Definition at line 99 of file AIELowerCascadeFlows.cpp.

createAIENormalizeAddressSpacesPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIENormalizeAddressSpacesPass

(

)

Definition at line 86 of file AIENormalizeAddressSpaces.cpp.

createAIENormalizeDmaBdDimsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIENormalizeDmaBdDimsPass

(

)

Definition at line 95 of file AIENormalizeDmaBdDims.cpp.

createAIEObjectFifoAllocatePass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoAllocatePass

(

)

Definition at line 2182 of file AIEObjectFifoAllocate.cpp.

createAIEObjectFifoErasePoolsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoErasePoolsPass

(

)

Definition at line 47 of file AIEObjectFifoErasePools.cpp.

createAIEObjectFifoLivenessPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoLivenessPass

(

)

Definition at line 297 of file AIEObjectFifoLiveness.cpp.

createAIEObjectFifoLowerCoresPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoLowerCoresPass

(

)

Definition at line 590 of file AIEObjectFifoLowerCores.cpp.

createAIEObjectFifoLowerDMAsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoLowerDMAsPass

(

)

Definition at line 433 of file AIEObjectFifoLowerDMAs.cpp.

createAIEObjectFifoSplitPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoSplitPass

(

)

Definition at line 919 of file AIEObjectFifoSplit.cpp.

createAIEObjectFifoUnrollPass() [1/2]

std::unique_ptr< mlir::OperationPass< xilinx::AIE::DeviceOp > > xilinx::AIE::createAIEObjectFifoUnrollPass

(

)

Definition at line 548 of file AIEObjectFifoUnroll.cpp.

createAIEObjectFifoUnrollPass() [2/2]

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoUnrollPass

(

const AIEObjectFifoUnrollOptions &

options

)

Definition at line 553 of file AIEObjectFifoUnroll.cpp.

createAIEObjectFifoVerifyPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEObjectFifoVerifyPass

(

)

Definition at line 452 of file AIEObjectFifoVerify.cpp.

createAIEPathfinderPass() [1/2]

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEPathfinderPass

(

)

Definition at line 3473 of file AIECreatePathFindFlows.cpp.

createAIEPathfinderPass() [2/2]

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEPathfinderPass

(

const AIERoutePathfinderFlowsOptions &

options

)

Definition at line 3478 of file AIECreatePathFindFlows.cpp.

createAIEPlaceTilesPass() [1/2]

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEPlaceTilesPass

(

)

Definition at line 150 of file AIEPlaceTiles.cpp.

createAIEPlaceTilesPass() [2/2]

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEPlaceTilesPass

(

const AIEPlaceTilesOptions &

options

)

Definition at line 155 of file AIEPlaceTiles.cpp.

createAIEPrepareBuffersPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEPrepareBuffersPass

(

)

Definition at line 1678 of file AIEAssignBuffers.cpp.

createAIERouteFlowsPass()

std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > xilinx::AIE::createAIERouteFlowsPass

(

)

createAIESplitFlowViasPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIESplitFlowViasPass

(

)

Definition at line 386 of file AIESplitFlowVias.cpp.

createAIETraceRegPackWritesPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIETraceRegPackWritesPass

(

)

Definition at line 711 of file AIETraceToConfig.cpp.

createAIETraceToConfigPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIETraceToConfigPass

(

)

Definition at line 449 of file AIETraceToConfig.cpp.

createAIEVectorToPointerLoopsPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEVectorToPointerLoopsPass

(

)

Definition at line 502 of file AIEVectorToPointerLoops.cpp.

createAIEVectorTransferLoweringPass()

std::unique_ptr< OperationPass< DeviceOp > > xilinx::AIE::createAIEVectorTransferLoweringPass

(

)

Definition at line 70 of file AIEVectorTransferLowering.cpp.

createConvertAIEToControlPacketsPass()

std::unique_ptr< mlir::OperationPass< xilinx::AIE::DeviceOp > > xilinx::AIE::createConvertAIEToControlPacketsPass

(

)

Definition at line 1064 of file AIEToConfiguration.cpp.

createConvertAIEToTransactionPass()

std::unique_ptr< mlir::OperationPass< xilinx::AIE::DeviceOp > > xilinx::AIE::createConvertAIEToTransactionPass

(

)

Definition at line 1059 of file AIEToConfiguration.cpp.

denseAttrToBytes()

std::optional< std::vector< char > > xilinx::AIE::denseAttrToBytes

(

mlir::DenseElementsAttr

denseInit

)

A buffer's initial_value as the bytes to write to its tile memory, in element order.

Every path that delivers that value to the device calls this – the CDO and transaction writer, and the aiesim configuration source – so one buffer is initialized one way.

Returns nullopt for an element type with no byte image, meaning neither integer nor float. The callers report that type.

Definition at line 191 of file AIETargetShared.cpp.

Referenced by xilinx::AIE::AIERTControl::initBuffers().

describePort()

std::string xilinx::AIE::describePort

(

Port

port

)

Names a port the way diagnostics do, e.g. "DMA:1".

Definition at line 14 of file AIERoutingDiagnostics.cpp.

Referenced by describeTilePort(), xilinx::AIE::StreamConflicts::explain(), and xilinx::AIE::SwitchSetting::operator<<.

describePrioritized()

std::string xilinx::AIE::describePrioritized

(

llvm::ArrayRef< std::string >

sources

)

Says that the packet flows from sources keep the route they take alone, as a control-packet reload of a design they are prioritized in asks.

Definition at line 38 of file AIERoutingDiagnostics.cpp.

References joinNames().

describeStream()

std::string xilinx::AIE::describeStream

(

const RoutedStream &

stream

)

Names the stream by its endpoints and packet id, e.g.

"packet flow (0, 1) DMA:0 -> (0, 2) DMA:1 (id 3)".

Definition at line 1315 of file AIEStreamDependencyAnalysis.cpp.

References describeTilePort(), xilinx::AIE::RoutedStream::dst, xilinx::AIE::RoutedStream::packetID, xilinx::AIE::StreamEndpoint::port, xilinx::AIE::RoutedStream::src, and xilinx::AIE::StreamEndpoint::tile.

Referenced by xilinx::AIE::StreamDeadlockAnalysis::assumptions(), xilinx::AIE::StreamConflicts::explain(), and xilinx::AIE::StreamDeadlockAnalysis::explainBlock().

describeTilePort()

std::string xilinx::AIE::describeTilePort	(	TileID	tile,
		Port	port )

Names a tile port the way diagnostics do, e.g. "(0, 2) DMA:1".

Definition at line 19 of file AIERoutingDiagnostics.cpp.

References describePort().

Referenced by xilinx::AIE::StreamDeadlockAnalysis::assumptions(), describeStream(), xilinx::AIE::Pathfinder::TreeBuilder::grow(), xilinx::AIE::PathEndPoint::operator<<, xilinx::AIE::Pathfinder::TreeBuilder::placePinned(), and xilinx::AIE::Pathfinder::RouteState::splitPart().

emitNpuLocmapJSON()

void xilinx::AIE::emitNpuLocmapJSON	(	llvm::raw_ostream &	output,
		llvm::StringRef	deviceName,
		llvm::StringRef	binaryName,
		const std::vector< TxnLocEntry > &	locmap )

Definition at line 789 of file AIETargetNPU.cpp.

References xilinx::AIE::TxnLocEntry::address, xilinx::AIE::TxnLocEntry::byteOffset, xilinx::AIE::TxnLocEntry::byteSize, xilinx::AIE::TxnLocEntry::loc, xilinx::AIE::TxnLocEntry::opcodeName, xilinx::AIE::TxnLocEntry::registerModule, xilinx::AIE::TxnLocEntry::registerName, and xilinx::AIE::TxnLocEntry::sourceOpName.

Referenced by registerAIETranslations().

forEachMemAffinityNeighbor()

template<typename F>

void xilinx::AIE::forEachMemAffinityNeighbor ( const AIETargetModel & targetModel, TileID at, F && fn )

inline

Definition at line 221 of file AIEPlacer.h.

References xilinx::AIE::AIETargetModel::columns(), xilinx::AIE::AIETargetModel::getTileType(), isSharedComputeMemory(), and xilinx::AIE::AIETargetModel::rows().

forEachPeer()

template<typename F>

void xilinx::AIE::forEachPeer ( mlir::Operation * op, const Placer::Adjacency & adjacency, F && fn )

inline

Definition at line 192 of file AIEPlacer.h.

References xilinx::AIE::Placer::Adjacency::edges, and xilinx::AIE::Placer::Adjacency::tileToEdges.

Referenced by xilinx::AIE::SequentialPlacer::place().

generateAndInsertConfigOps()

mlir::LogicalResult xilinx::AIE::generateAndInsertConfigOps	(	mlir::OpBuilder &	builder,
		xilinx::AIE::DeviceOp	device,
		xilinx::AIEX::BlockwriteData &	blockwriteData,
		llvm::StringRef	clElfDir = "",
		AIEToConfigurationOutputType	outputType = AIEToConfigurationOutputType::Transaction,
		bool	skipCtrlPktOverlay = false )

References Transaction.

generateAndInsertResetOps()

mlir::LogicalResult xilinx::AIE::generateAndInsertResetOps	(	mlir::OpBuilder &	builder,
		xilinx::AIE::DeviceOp	device,
		ResetConfig	dmaConfig,
		ResetConfig	switchConfig,
		ResetConfig	lockConfig,
		ResetConfig	coreConfig,
		xilinx::AIE::DeviceOp	previousDevice )

generateAndInsertTeardownOps()

mlir::LogicalResult xilinx::AIE::generateAndInsertTeardownOps	(	mlir::OpBuilder &	builder,
		xilinx::AIE::DeviceOp	device,
		xilinx::AIEX::BlockwriteData &	blockwriteData,
		AIEToConfigurationOutputType	outputType = AIEToConfigurationOutputType::Transaction )

References Transaction.

generateXAieDmaSetMultiDimAddr() [1/2]

void xilinx::AIE::generateXAieDmaSetMultiDimAddr	(	llvm::raw_ostream &	output,
		int	ndims,
		llvm::ArrayRef< BDDimLayoutAttr >	dims,
		int	col,
		int	row,
		int	bdNum,
		int	baseAddrA,
		int64_t	offsetA,
		uint32_t	lenA,
		int	elementWidthInBytes,
		const char *	errorRet )

generateXAieDmaSetMultiDimAddr() [2/2]

void xilinx::AIE::generateXAieDmaSetMultiDimAddr	(	raw_ostream &	output,
		int	ndims,
		ArrayRef< BDDimLayoutAttr >	dims,
		int	col,
		int	row,
		int	bdNum,
		int	baseAddrA,
		int64_t	offsetA,
		uint32_t	lenA,
		int	elementWidthInBytes,
		const char *	errorRetval )

Definition at line 86 of file AIETargetShared.cpp.

References tileDMAInstRefStr().

getAssignedBdIds()

llvm::SmallVector< uint32_t > xilinx::AIE::getAssignedBdIds

(

DmaBody

program

)

Definition at line 4757 of file AIEDialect.cpp.

getBufferBaseAddress()

int32_t xilinx::AIE::getBufferBaseAddress

(

mlir::Operation *

bufOp

)

Referenced by AIETranslateToBCF(), coreBankRegions(), and coreDataRegion().

getConnectingBundle()

WireBundle xilinx::AIE::getConnectingBundle

(

WireBundle

dir

)

Definition at line 5817 of file AIEDialect.cpp.

Referenced by getConnectingWireEndpoint().

getConnectingWireEndpoint()

std::optional< std::pair< TileID, Port > > xilinx::AIE::getConnectingWireEndpoint	(	const AIETargetModel &	targetModel,
		TileID	tile,
		Port	port )

Definition at line 5833 of file AIEDialect.cpp.

References getConnectingBundle(), and xilinx::AIE::AIETargetModel::isValidTile().

getDMACapacity()

std::pair< int, int > xilinx::AIE::getDMACapacity ( const AIETargetModel & tm, TileID tile )

inline

Get DMA channel capacity (maxIn, maxOut) for a tile position.

Definition at line 25 of file AIEPlacer.h.

References xilinx::AIE::AIETargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIETargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIETargetModel::getNumSourceShimMuxConnections(), and xilinx::AIE::AIETargetModel::getNumSourceSwitchboxConnections().

getLengthUnitBytes()

mlir::FailureOr< int64_t > xilinx::AIE::getLengthUnitBytes	(	mlir::Operation *	op,
		int64_t	lengthUnit,
		mlir::BaseMemRefType	buffer )

Referenced by xilinx::AIEX::emitUpdateBdLengthFromParameter().

getObjectFifoLoopParent()

mlir::Operation * xilinx::AIE::getObjectFifoLoopParent

(

mlir::Operation *

op

)

The innermost loop around op that isObjectFifoLoop accepts, or null.

getOrderedChainOfBlocks() [1/2]

llvm::SetVector< mlir::Block * > xilinx::AIE::getOrderedChainOfBlocks

(

mlir::Region *

region

)

Referenced by xilinx::AIE::AIERTControl::addInitConfig(), and xilinx::AIE::AIERTControl::resetDmaChannels().

getOrderedChainOfBlocks() [2/2]

llvm::SetVector< Block * > xilinx::AIE::getOrderedChainOfBlocks

(

Region *

region

)

Definition at line 136 of file AIETargetShared.cpp.

getShimBurstLengthBytes()

uint32_t xilinx::AIE::getShimBurstLengthBytes	(	const AIE::AIETargetModel &	tm,
		uint32_t	burstLength )

Definition at line 142 of file AIEDialect.cpp.

getShimBurstLengthEncoding()

uint32_t xilinx::AIE::getShimBurstLengthEncoding	(	const AIE::AIETargetModel &	tm,
		uint32_t	burstLength )

Definition at line 148 of file AIEDialect.cpp.

getTargetModel() [1/2]

const AIETargetModel & xilinx::AIE::getTargetModel

(

AIEDevice

device

)

Definition at line 280 of file AIEDialect.cpp.

getTargetModel() [2/2]

const AIETargetModel & xilinx::AIE::getTargetModel

(

mlir::Operation *

op

)

Referenced by aieGetTargetModel(), AIETranslateToBCF(), coreBankRegions(), coreDataRegion(), AIEDMATasksToNPUPass::emitOutOfOrderChannelEnable(), xilinx::AIE::DMAChannelAnalysis::getDMAChannelLimit(), xilinx::AIEX::TokenAnalysis::getShareableTileOp(), xilinx::AIE::PacketIdSpace::PacketIdSpace(), registerAIETranslations(), AIEDMATasksToNPUPass::rewriteSingleBD(), AIEDMATasksToNPUPass::rewriteSingleBDDynamic(), AIEAssignLockIDsPass::runOnOperation(), AIELocalizeLocksPass::runOnOperation(), sharedMemory(), verifyDMABDIteration(), verifyDMABDOutOfOrderId(), xilinx::AIEX::verifyStridesWraps(), and xilinx::AIE::HasValidBDs< ConcreteType >::verifyTrait().

hasFlag()

bool xilinx::AIE::hasFlag ( ResetTileType value, ResetTileType flag )

inline

Definition at line 88 of file AIEToConfiguration.h.

inferStreamWindow()

mlir::LogicalResult xilinx::AIE::inferStreamWindow	(	llvm::ArrayRef< BDDimLayoutAttr >	dims,
		llvm::ArrayRef< BDPadLayoutAttr >	pads,
		int64_t	objectSize,
		llvm::function_ref< mlir::InFlightDiagnostic()>	emitError,
		StreamWindow &	window )

inlineWriteConfigs()

mlir::LogicalResult xilinx::AIE::inlineWriteConfigs

(

mlir::ModuleOp

module

)

insertConfigOps()

mlir::LogicalResult xilinx::AIE::insertConfigOps	(	llvm::ArrayRef< std::pair< mlir::Operation *, xilinx::AIE::DeviceOp > >	sites,
		AIEToConfigurationOutputType	outputType )

isContiguousBDTransfer()

bool xilinx::AIE::isContiguousBDTransfer

(

llvm::ArrayRef< BDDimLayoutAttr >

dims

)

Definition at line 4638 of file AIEDialect.cpp.

isDirectional()

bool xilinx::AIE::isDirectional ( WireBundle bundle )

inline

Definition at line 447 of file AIEDialect.h.

Referenced by xilinx::AIE::Pathfinder::TreeBuilder::claim(), and xilinx::AIE::Pathfinder::findPaths().

isForeverLoop()

bool xilinx::AIE::isForeverLoop

(

mlir::scf::WhileOp

whileOp

)

Whether whileOp repeats forever: its condition is a constant true, and its condition region does nothing but forward its arguments to the body.

This is how IRON's Worker writes a core that runs until reconfiguration. Such a loop can be unrolled by repeating its body.

isObjectFifoLoop()

bool xilinx::AIE::isObjectFifoLoop

(

mlir::Operation *

op

)

Whether op is a loop that objectFifo lowering unrolls by the rotation period of the objectFifos accessed in it: an scf.for, or an scf.while that repeats forever.

isSharedComputeMemory()

bool xilinx::AIE::isSharedComputeMemory ( const AIETargetModel & targetModel, TileID a, TileID b )

inline

Definition at line 212 of file AIEPlacer.h.

References xilinx::AIE::AIETargetModel::isLegalMemAffinity().

Referenced by forEachMemAffinityNeighbor().

joinNames()

std::string xilinx::AIE::joinNames	(	llvm::ArrayRef< std::string >	names,
		size_t	shown = 4 )

Lists names as "A, B and C", the first shown of them followed by "N more" if there are more.

Definition at line 24 of file AIERoutingDiagnostics.cpp.

Referenced by describePrioritized().

keepsPktHeader()

bool xilinx::AIE::keepsPktHeader	(	TileID	tile,
		Port	master,
		std::optional< bool >	keep )

Definition at line 3591 of file AIEDialect.cpp.

Referenced by requestedStreams().

largestFreeRun()

MemoryRun xilinx::AIE::largestFreeRun ( int64_t memSize, llvm::SmallVector< std::pair< int64_t, int64_t > > occupied, int64_t alignBytes = 1 )

inline

Definition at line 82 of file AIECoreMemory.h.

References largestFreeRunIn().

Referenced by coreDataRegion().

largestFreeRunIn()

MemoryRun xilinx::AIE::largestFreeRunIn ( MemoryRun window, llvm::SmallVector< std::pair< int64_t, int64_t > > occupied, int64_t alignBytes = 1 )

inline

Definition at line 52 of file AIECoreMemory.h.

References xilinx::AIE::MemoryRun::end(), xilinx::AIE::MemoryRun::size, and xilinx::AIE::MemoryRun::start.

Referenced by coreBankRegions(), and largestFreeRun().

lookupNamedOp() [1/3]

mlir::Operation * xilinx::AIE::lookupNamedOp	(	mlir::Operation *	from,
		llvm::StringRef	name )

lookupNamedOp() [2/3]

mlir::Operation * xilinx::AIE::lookupNamedOp	(	mlir::Operation *	from,
		mlir::StringAttr	name )

Referenced by lookupNamedOp().

lookupNamedOp() [3/3]

template<typename OpTy, typename NameT>

OpTy xilinx::AIE::lookupNamedOp	(	mlir::Operation *	from,
		NameT	name )

Definition at line 143 of file AIEDialect.h.

References lookupNamedOp().

lookupNamedOpIn() [1/3]

mlir::Operation * xilinx::AIE::lookupNamedOpIn	(	mlir::Operation *	symbolTableOp,
		llvm::StringRef	name )

lookupNamedOpIn() [2/3]

mlir::Operation * xilinx::AIE::lookupNamedOpIn	(	mlir::Operation *	symbolTableOp,
		mlir::StringAttr	name )

Referenced by lookupNamedOpIn().

lookupNamedOpIn() [3/3]

template<typename OpTy, typename NameT>

OpTy xilinx::AIE::lookupNamedOpIn	(	mlir::Operation *	symbolTableOp,
		NameT	name )

Definition at line 138 of file AIEDialect.h.

References lookupNamedOpIn().

myVerifyOffsetSizeAndStrideOp()

LogicalResult xilinx::AIE::myVerifyOffsetSizeAndStrideOp

(

mlir::OffsetSizeAndStrideOpInterface

op

)

Definition at line 210 of file AIEDialect.cpp.

Referenced by xilinx::AIE::MyOffsetSizeAndStrideOpInterfaceTrait< ConcreteOp >::verifyTrait().

normalizedBDDims()

std::optional< llvm::SmallVector< BDDimLayoutAttr > > xilinx::AIE::normalizedBDDims	(	llvm::ArrayRef< BDDimLayoutAttr >	dims,
		int64_t	len )

Referenced by aieDmaBdFits(), and AIENormalizeDmaBdDimsPass::runOnOperation().

operator<<()

llvm::raw_ostream & xilinx::AIE::operator<< ( llvm::raw_ostream & os, const SwitchSettings & ss )

inline

Definition at line 208 of file AIEPathFinder.h.

packetStr() [1/3]

std::string xilinx::AIE::packetStr	(	int	id,
		int	type )

Definition at line 69 of file AIETargetShared.cpp.

References packetStr().

packetStr() [2/3]

std::string xilinx::AIE::packetStr	(	llvm::StringRef	id,
		llvm::StringRef	type )

Referenced by packetStr().

packetStr() [3/3]

std::string xilinx::AIE::packetStr	(	StringRef	id,
		StringRef	type )

Definition at line 62 of file AIETargetShared.cpp.

paddedSize()

int64_t xilinx::AIE::paddedSize	(	llvm::ArrayRef< BDDimLayoutAttr >	dims,
		llvm::ArrayRef< BDPadLayoutAttr >	pads,
		int64_t	fallback )

Definition at line 4627 of file AIEDialect.cpp.

parseDMAStartChannel()

mlir::ParseResult xilinx::AIE::parseDMAStartChannel	(	mlir::OpAsmParser &	parser,
		mlir::Attribute &	channel )

parseFlowVias()

mlir::ParseResult xilinx::AIE::parseFlowVias	(	mlir::OpAsmParser &	parser,
		llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &	vias,
		mlir::DenseI32ArrayAttr &	ingressBundles,
		mlir::DenseI32ArrayAttr &	ingressChannels,
		mlir::DenseI32ArrayAttr &	egressBundles,
		mlir::DenseI32ArrayAttr &	egressChannels )

parseObjectFifoAcquireObjects()

mlir::ParseResult xilinx::AIE::parseObjectFifoAcquireObjects	(	mlir::OpAsmParser &	parser,
		ObjectFifoPortAttr &	port,
		llvm::SmallVectorImpl< mlir::Type > &	objects )

parseObjectFifoConsumerTiles()

mlir::ParseResult xilinx::AIE::parseObjectFifoConsumerTiles	(	mlir::OpAsmParser &	parser,
		llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &	tiles,
		BDDimLayoutArrayArrayAttr &	dimensions )

parseObjectFifoProducerTile()

mlir::ParseResult xilinx::AIE::parseObjectFifoProducerTile	(	mlir::OpAsmParser &	parser,
		mlir::OpAsmParser::UnresolvedOperand &	operand,
		BDDimLayoutArrayAttr &	dimensions )

parseObjectFifoReleaseCount()

mlir::ParseResult xilinx::AIE::parseObjectFifoReleaseCount	(	mlir::OpAsmParser &	parser,
		ObjectFifoPortAttr &	port,
		mlir::IntegerAttr &	size )

parseTraceEvent()

mlir::ParseResult xilinx::AIE::parseTraceEvent	(	mlir::AsmParser &	parser,
		mlir::Attribute &	result )

parseTypedDynamicIndexList()

mlir::ParseResult xilinx::AIE::parseTypedDynamicIndexList	(	mlir::OpAsmParser &	parser,
		llvm::SmallVectorImpl< mlir::OpAsmParser::UnresolvedOperand > &	values,
		mlir::DenseI64ArrayAttr &	integers,
		llvm::SmallVectorImpl< mlir::Type > &	types )

placeRuntimeLengthDimension()

void xilinx::AIE::placeRuntimeLengthDimension	(	llvm::MutableArrayRef< int64_t >	sizes,
		llvm::MutableArrayRef< int64_t >	strides )

Definition at line 4728 of file AIEDialect.cpp.

Referenced by AIEDMATasksToNPUPass::rewriteSingleBD().

printDMAStartChannel()

void xilinx::AIE::printDMAStartChannel	(	mlir::OpAsmPrinter &	printer,
		mlir::Operation *	op,
		mlir::Attribute	channel )

printFlowVias()

void xilinx::AIE::printFlowVias	(	mlir::OpAsmPrinter &	printer,
		mlir::Operation *	op,
		mlir::OperandRange	vias,
		mlir::DenseI32ArrayAttr	ingressBundles,
		mlir::DenseI32ArrayAttr	ingressChannels,
		mlir::DenseI32ArrayAttr	egressBundles,
		mlir::DenseI32ArrayAttr	egressChannels )

printObjectFifoAcquireObjects()

void xilinx::AIE::printObjectFifoAcquireObjects	(	mlir::OpAsmPrinter &	printer,
		mlir::Operation *	op,
		ObjectFifoPortAttr	port,
		mlir::TypeRange	objects )

printObjectFifoConsumerTiles()

void xilinx::AIE::printObjectFifoConsumerTiles	(	mlir::OpAsmPrinter &	printer,
		mlir::Operation *	op,
		mlir::OperandRange	tiles,
		BDDimLayoutArrayArrayAttr	dimsPerTileAttr )

printObjectFifoProducerTile()

void xilinx::AIE::printObjectFifoProducerTile	(	mlir::OpAsmPrinter &	printer,
		mlir::Operation *	op,
		mlir::Value	operand,
		BDDimLayoutArrayAttr	dimensions )

printObjectFifoReleaseCount()

void xilinx::AIE::printObjectFifoReleaseCount	(	mlir::OpAsmPrinter &	printer,
		mlir::Operation *	op,
		ObjectFifoPortAttr	port,
		mlir::IntegerAttr	size )

printTraceEventEnum()

void xilinx::AIE::printTraceEventEnum	(	mlir::AsmPrinter &	printer,
		mlir::Attribute	attr )

printTypedDynamicIndexList()

void xilinx::AIE::printTypedDynamicIndexList	(	mlir::OpAsmPrinter &	printer,
		mlir::Operation *	op,
		mlir::OperandRange	values,
		llvm::ArrayRef< int64_t >	integers,
		mlir::TypeRange	types )

registerAIEObjectFifoPipeline()

void xilinx::AIE::registerAIEObjectFifoPipeline

(

)

Register aie-objectFifo-stateful-transform as a pipeline over the passes that lower aie.objectfifo.

Definition at line 46 of file AIEObjectFifoPipeline.cpp.

References addObjectFifoLoweringPasses().

Referenced by aieRegisterAllPasses().

registerAIETranslations()

void xilinx::AIE::registerAIETranslations

(

)

Definition at line 125 of file AIETargets.cpp.

References AIEFlowsToJSON(), AIETranslateControlPacketsToUI32Vec(), AIETranslateGraphXPE(), AIETranslateNpuToBinary(), AIETranslateNpuToCpp(), AIETranslateSCSimConfig(), AIETranslateShimSolution(), AIETranslateToBCF(), AIETranslateToCDODirect(), AIETranslateToLdScript(), AIETranslateToTargetArch(), AIETranslateToUcDma(), AIETranslateToXAIEV2(), collectBuffers(), collectTiles(), emitNpuLocmapJSON(), and getTargetModel().

requestedStreams()

std::vector< RoutedStream > xilinx::AIE::requestedStreams

(

DeviceOp

device

)

The streams the aie.flow and aie.packet_flow ops ask for, one per source, destination and packet id, before any of them is routed.

Definition at line 419 of file AIEStreamDependencyAnalysis.cpp.

References keepsPktHeader().

Referenced by xilinx::AIE::StreamConflicts::StreamConflicts().

requiredBufferAlignBits()

uint32_t xilinx::AIE::requiredBufferAlignBits ( uint32_t busAlignBits, uint32_t maxVecAlignBits, int64_t sizeBytes )

inline

Return the alignment (in bits) a buffer of sizeBytes must satisfy.

Bus width alone is insufficient: from AIE2P on, a full-width vector access needs 512-bit alignment while the bus is 256 bits wide. An externally compiled kernel may perform such an access, so a buffer large enough to hold a full-width vector gets the stricter alignment. A smaller buffer keeps the bus width and costs no padding.

Definition at line 49 of file AIEBufferAllocation.h.

sharedMemory()

AIETargetModel::SharedMemory xilinx::AIE::sharedMemory	(	TileOp	a,
		TileOp	b )

Which of a's and b's memory modules both tiles can address.

Definition at line 275 of file AIEDialect.cpp.

References xilinx::AIE::AIETargetModel::getSharedMemory(), and getTargetModel().

shimMuxChannelFrom()

int xilinx::AIE::shimMuxChannelFrom

(

Port

src

)

Definition at line 603 of file AIEPathFinder.cpp.

Referenced by xilinx::AIE::Pathfinder::addFixedConnection().

shimMuxChannelTo()

int xilinx::AIE::shimMuxChannelTo

(

Port

dst

)

Definition at line 612 of file AIEPathFinder.cpp.

Referenced by xilinx::AIE::Pathfinder::addFixedConnection().

streamWindowSteps()

SmallVector< StreamWindowStep > xilinx::AIE::streamWindowSteps

(

const StreamWindow &

w

)

Definition at line 407 of file AIEDialect.cpp.

References xilinx::AIE::StreamWindow::advance, xilinx::AIE::StreamWindow::objects, xilinx::AIE::StreamWindow::outputs, xilinx::AIE::StreamWindow::span, and xilinx::AIE::StreamWindow::top.

tileDMAInstRefStr() [1/3]

std::string xilinx::AIE::tileDMAInstRefStr	(	int	col,
		int	row,
		int	bdNum )

Definition at line 57 of file AIETargetShared.cpp.

References tileDMAInstRefStr().

tileDMAInstRefStr() [2/3]

std::string xilinx::AIE::tileDMAInstRefStr	(	llvm::StringRef	col,
		llvm::StringRef	row,
		llvm::StringRef	bdNum )

Referenced by generateXAieDmaSetMultiDimAddr(), and tileDMAInstRefStr().

tileDMAInstRefStr() [3/3]

std::string xilinx::AIE::tileDMAInstRefStr	(	StringRef	col,
		StringRef	row,
		StringRef	bdNum )

Definition at line 50 of file AIETargetShared.cpp.

References tileDMAInstStr().

tileDMAInstStr() [1/3]

std::string xilinx::AIE::tileDMAInstStr	(	int	col,
		int	row,
		int	bdNum )

Definition at line 45 of file AIETargetShared.cpp.

References tileDMAInstStr().

tileDMAInstStr() [2/3]

std::string xilinx::AIE::tileDMAInstStr	(	llvm::StringRef	col,
		llvm::StringRef	row,
		llvm::StringRef	bdNum )

Referenced by tileDMAInstRefStr(), and tileDMAInstStr().

tileDMAInstStr() [3/3]

std::string xilinx::AIE::tileDMAInstStr	(	StringRef	col,
		StringRef	row,
		StringRef	bdNum )

Definition at line 38 of file AIETargetShared.cpp.

tileLocStr() [1/3]

std::string xilinx::AIE::tileLocStr	(	int	col,
		int	row )

Definition at line 34 of file AIETargetShared.cpp.

References tileLocStr().

tileLocStr() [2/3]

std::string xilinx::AIE::tileLocStr	(	llvm::StringRef	col,
		llvm::StringRef	row )

Referenced by tileLocStr().

tileLocStr() [3/3]

std::string xilinx::AIE::tileLocStr	(	StringRef	col,
		StringRef	row )

Definition at line 27 of file AIETargetShared.cpp.

tileMemoryLimits()

TileMemoryLimits xilinx::AIE::tileMemoryLimits ( const AIETargetModel & targetModel, AIETileType tileType )

inline

Definition at line 30 of file AIEBufferAllocation.h.

References xilinx::AIE::AIETargetModel::getComputeTileLoadStoreBusWidth(), xilinx::AIE::AIETargetModel::getComputeTileMaxVectorAlignBits(), xilinx::AIE::AIETargetModel::getLocalMemorySize(), xilinx::AIE::AIETargetModel::getMemTileLoadStoreBusWidth(), and xilinx::AIE::AIETargetModel::getMemTileSize().

traceRoutedStreams()

std::vector< RoutedStream > xilinx::AIE::traceRoutedStreams

(

DeviceOp

device

)

Follows every stream from its source tile port through the configured switchboxes, using tile geometry for the links between them.

A packet stream is traced once per id its source sends, as read off the BDs and runtime transfers that program the source; with none known, once per rule of the first switchbox it enters.

Definition at line 415 of file AIEStreamDependencyAnalysis.cpp.

Referenced by xilinx::AIE::StreamConflicts::StreamConflicts().

turnEndpoints()

SmallVector< ObjectFifoDmaEndpointOp > xilinx::AIE::turnEndpoints

(

ObjectFifoDmaEndpointOp

end

)

Definition at line 1183 of file AIEDialect.cpp.

turnPasses()

int64_t xilinx::AIE::turnPasses

(

llvm::ArrayRef< std::pair< int64_t, int64_t > >

ends

)

txnDeviceGen()

uint8_t xilinx::AIE::txnDeviceGen ( const AIETargetModel & tm )

inline

Device generation ID written into the TXN header (aie_runtime::TxnDeviceInfo::devGen).

Both the static binary emitter and the generated-C++ builder read it from here, so a new device family is one edit.

Definition at line 1306 of file AIETargetModel.h.

verifyAssignedPacket()

mlir::LogicalResult xilinx::AIE::verifyAssignedPacket	(	mlir::Operation *	op,
		PacketInfoAttr	packet,
		llvm::StringRef	what = "packet" )

verifyBdLockPair()

mlir::LogicalResult xilinx::AIE::verifyBdLockPair	(	mlir::Block &	block,
		bool	outOfOrder,
		UseLockOp &	acquire,
		UseLockOp &	release )

Referenced by AIEDMATasksToNPUPass::gatherBdTemplateFields(), and AIEDMATasksToNPUPass::rewriteSingleDMAConfigureTaskOp().

verifyDMABDIteration()

LogicalResult xilinx::AIE::verifyDMABDIteration	(	DMABDOp	bd,
		AIETileType	tileType )

Definition at line 4158 of file AIEDialect.cpp.

References xilinx::AIE::AIETargetModel::getDmaBdIterBits(), xilinx::AIE::AIETargetModel::getDmaBdStepBits(), getTargetModel(), xilinx::AIE::AIETargetModel::hasProperty(), and xilinx::AIE::AIETargetModel::UsesBDIteration.

verifyDMABDOutOfOrderId()

LogicalResult xilinx::AIE::verifyDMABDOutOfOrderId	(	DMABDOp	bd,
		bool	packetEnabledByContext = false )

Definition at line 4138 of file AIEDialect.cpp.

References xilinx::AIE::AIETargetModel::getMaxOutOfOrderId(), getTargetModel(), xilinx::AIE::AIETargetModel::hasProperty(), and xilinx::AIE::AIETargetModel::SupportsOutOfOrderDMA.

verifyDMAChannelsResolved()

LogicalResult xilinx::AIE::verifyDMAChannelsResolved

(

DeviceOp

device

)

Definition at line 1583 of file AIEDialect.cpp.

Referenced by xilinx::AIE::AIERTControl::addInitConfig(), AIETranslateShimSolution(), and AIEAssignBufferDescriptorIDsPass::runOnOperation().

verifyLengthParameter()

mlir::LogicalResult xilinx::AIE::verifyLengthParameter	(	mlir::Operation *	op,
		std::optional< int64_t >	lengthUnit,
		mlir::BaseMemRefType	buffer,
		std::optional< int64_t >	lenElems,
		bool	contiguous,
		llvm::ArrayRef< int64_t >	innerSizes )

verifyLengthParameterTile()

mlir::LogicalResult xilinx::AIE::verifyLengthParameterTile	(	mlir::Operation *	op,
		const AIETargetModel &	targetModel,
		int	col,
		int	row )

Referenced by xilinx::AIEX::emitUpdateBdLengthFromParameter().

verifyOffsetSizeAndStrideOp()

mlir::LogicalResult xilinx::AIE::verifyOffsetSizeAndStrideOp

(

mlir::OffsetSizeAndStrideOpInterface

op

)

verifyOutOfOrderChannel()

mlir::LogicalResult xilinx::AIE::verifyOutOfOrderChannel	(	mlir::Operation *	op,
		DMAChannelDir	dir,
		bool	outOfOrder,
		llvm::ArrayRef< DMABDOp >	bds,
		bool	packetEnabledByContext = false )

Variable Documentation

kObjectFifoObjectSlotAttrName

llvm::StringLiteral xilinx::AIE::kObjectFifoObjectSlotAttrName

inlineconstexpr

Initial value:

=
    "aie.objectfifo.object_slot"

Discardable attribute set by --aie-objectfifo-lower-cores on the rank-0 memref.allocas that hold a core's objects of an objectFifo in rotation order.

The AIEObjectFifoUnroll pass promotes them to SSA on each core where every object then folds to its buffer. Otherwise they stay in memory, so that LLVM's SROA carries only the buffer pointer around the loop rather than the whole memref descriptor.

Definition at line 34 of file AIEPasses.h.

kObjectFifoUnrollHintAttrName

llvm::StringLiteral xilinx::AIE::kObjectFifoUnrollHintAttrName

inlineconstexpr

Initial value:

=
    "aie.unroll_hint"

Discardable attribute set by --aie-objectfifo-lower-cores on scf.for and forever scf.while loops containing ObjectFifo accesses – the loop unroll factor (the least common multiple of the depths of the objectFifos accessed within the loop) consumed by the AIEObjectFifoUnroll pass.

Definition at line 25 of file AIEPasses.h.