AIETraceToConfig.cpp

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//===- AIETraceToConfig.cpp -------------------------------------*- C++ -*-===//
//
// Copyright (C) 2025 Advanced Micro Devices, Inc.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Pass to lower aie.trace to aie.trace.config
//===----------------------------------------------------------------------===//
 
#include "aie/Dialect/AIE/IR/AIEDialect.h"
#include "aie/Dialect/AIE/Transforms/AIEPasses.h"
 
#include "mlir/IR/Attributes.h"
#include "mlir/Pass/Pass.h"
 
namespace xilinx::AIE {
#define GEN_PASS_DEF_AIETRACETOCONFIG
#define GEN_PASS_DEF_AIETRACEREGPACKWRITES
#include "aie/Dialect/AIE/Transforms/AIEPasses.h.inc"
} // namespace xilinx::AIE
 
using namespace mlir;
using namespace xilinx;
using namespace xilinx::AIE;
 
namespace {
 
struct AIETraceToConfigPass
    : xilinx::AIE::impl::AIETraceToConfigBase<AIETraceToConfigPass> {
  void runOnOperation() override {
    DeviceOp device = getOperation();
    OpBuilder builder(device);
    const auto &targetModel = device.getTargetModel();
 
    // Collect all trace operations
    SmallVector<TraceOp> traces;
    device.walk([&](TraceOp trace) { traces.push_back(trace); });
 
    for (auto trace : traces) {
      // Create config symbol name
      std::string configName = (trace.getSymName().str() + "_config");
      auto tile = cast<TileOp>(trace.getTile().getDefiningOp());
      TileID tileID = tile.getTileID();
 
      // Find packet type (if any)
      TracePacketType packetType = TracePacketType::Core; // default
      for (auto &op : trace.getBody().getOps()) {
        if (auto packetOp = dyn_cast<TracePacketOp>(op)) {
          packetType = packetOp.getType();
          break;
        }
      }
 
      // Insert trace.config after trace declaration
      builder.setInsertionPointAfter(trace);
      auto configOp = TraceConfigOp::create(
          builder, trace.getLoc(), trace.getTile(),
          builder.getStringAttr(configName),
          TracePacketTypeAttr::get(builder.getContext(), packetType));
 
      // Build register writes inside config body
      Block *configBody = new Block();
      configOp.getBody().push_back(configBody);
      OpBuilder configBuilder = OpBuilder::atBlockEnd(configBody);
 
      bool isMem = (packetType == TracePacketType::Mem);
 
      // Process combo/edge events FIRST (before other trace config)
      // This ensures COMBO_EVENT_*/EDGE_DETECTION_EVENT_* are configured
      // before they can be referenced in trace.event operations
 
      // 0a. Emit combo event configurations
      for (auto &op : trace.getBody().getOps()) {
        if (auto comboOp = dyn_cast<TraceComboEventOp>(op)) {
          uint32_t slot = comboOp.getSlot();
 
          // Get input events - use getEventName() helper
          std::string eventAName = comboOp.getEventA().getEventName();
          std::string eventBName = comboOp.getEventB().getEventName();
          ComboLogic logic = comboOp.getLogic();
 
          // If enum, use enum value directly; otherwise lookup by name
          std::optional<uint32_t> eventANum, eventBNum;
 
          if (auto enumValA = comboOp.getEventA().getEnumValue()) {
            eventANum = static_cast<uint32_t>(*enumValA);
          } else {
            eventANum = targetModel.lookupEvent(eventAName, tileID, isMem);
          }
 
          if (auto enumValB = comboOp.getEventB().getEnumValue()) {
            eventBNum = static_cast<uint32_t>(*enumValB);
          } else {
            eventBNum = targetModel.lookupEvent(eventBName, tileID, isMem);
          }
 
          if (!eventANum) {
            comboOp.emitError("unknown trace event '") << eventAName << "'";
            return signalPassFailure();
          }
          if (!eventBNum) {
            comboOp.emitError("unknown trace event '") << eventBName << "'";
            return signalPassFailure();
          }
 
          // Map slot to input event fields
          StringRef eventAField, eventBField, controlField;
          if (slot == 0) {
            eventAField = "eventA";
            eventBField = "eventB";
            controlField = "combo0";
          } else if (slot == 1) {
            eventAField = "eventC";
            eventBField = "eventD";
            controlField = "combo1";
          } else if (slot == 2) {
            // Combo2 is hierarchical - reuses eventA/B fields but represents
            // combo0/combo1
            eventAField = "eventA";
            eventBField = "eventB";
            controlField = "combo2";
          }
 
          // Emit Combo_event_inputs register fields
          TraceRegOp::create(configBuilder, comboOp.getLoc(),
                             builder.getStringAttr("Combo_event_inputs"),
                             builder.getStringAttr(eventAField),
                             comboOp.getEventA(),
                             /*mask=*/nullptr,
                             builder.getStringAttr(
                                 "combo" + std::to_string(slot) + " eventA"));
 
          TraceRegOp::create(configBuilder, comboOp.getLoc(),
                             builder.getStringAttr("Combo_event_inputs"),
                             builder.getStringAttr(eventBField),
                             comboOp.getEventB(),
                             /*mask=*/nullptr,
                             builder.getStringAttr(
                                 "combo" + std::to_string(slot) + " eventB"));
 
          // Emit Combo_event_control register field
          TraceRegOp::create(
              configBuilder, comboOp.getLoc(),
              builder.getStringAttr("Combo_event_control"),
              builder.getStringAttr(controlField),
              builder.getI32IntegerAttr(static_cast<uint32_t>(logic)),
              /*mask=*/nullptr,
              builder.getStringAttr("combo" + std::to_string(slot) + " logic"));
        }
      }
 
      // 0b. Emit edge detection configurations
      for (auto &op : trace.getBody().getOps()) {
        if (auto edgeOp = dyn_cast<TraceEdgeEventOp>(op)) {
          uint32_t slot = edgeOp.getSlot();
          std::string eventName = edgeOp.getEvent().getEventName();
          EdgeTrigger trigger = edgeOp.getTrigger();
 
          // If enum, use enum value directly; otherwise lookup by name
          std::optional<uint32_t> eventNum;
 
          if (auto enumVal = edgeOp.getEvent().getEnumValue()) {
            eventNum = static_cast<uint32_t>(*enumVal);
          } else {
            eventNum = targetModel.lookupEvent(eventName, tileID, isMem);
          }
 
          if (!eventNum) {
            edgeOp.emitError("unknown trace event '") << eventName << "'";
            return signalPassFailure();
          }
 
          // Map slot to field names
          StringRef eventField =
              (slot == 0) ? "Edge_Detection_Event_0" : "Edge_Detection_Event_1";
          StringRef risingField = (slot == 0)
                                      ? "Edge_Detection_0_Trigger_Rising"
                                      : "Edge_Detection_1_Trigger_Rising";
          StringRef fallingField = (slot == 0)
                                       ? "Edge_Detection_0_Trigger_Falling"
                                       : "Edge_Detection_1_Trigger_Falling";
 
          // Source event
          TraceRegOp::create(
              configBuilder, edgeOp.getLoc(),
              builder.getStringAttr("Edge_Detection_event_control"),
              builder.getStringAttr(eventField), edgeOp.getEvent(),
              /*mask=*/nullptr,
              builder.getStringAttr("edge" + std::to_string(slot) + " source"));
 
          // Trigger mode
          bool rising =
              (trigger == EdgeTrigger::RISING || trigger == EdgeTrigger::BOTH);
          bool falling =
              (trigger == EdgeTrigger::FALLING || trigger == EdgeTrigger::BOTH);
 
          TraceRegOp::create(
              configBuilder, edgeOp.getLoc(),
              builder.getStringAttr("Edge_Detection_event_control"),
              builder.getStringAttr(risingField),
              builder.getI32IntegerAttr(rising ? 1 : 0),
              /*mask=*/nullptr,
              builder.getStringAttr("edge" + std::to_string(slot) + " rising"));
 
          TraceRegOp::create(
              configBuilder, edgeOp.getLoc(),
              builder.getStringAttr("Edge_Detection_event_control"),
              builder.getStringAttr(fallingField),
              builder.getI32IntegerAttr(falling ? 1 : 0),
              /*mask=*/nullptr,
              builder.getStringAttr("edge" + std::to_string(slot) +
                                    " falling"));
        }
      }
 
      // 1. Emit Trace_Control0 fields
      // Check for start/stop events
      for (auto &op : trace.getBody().getOps()) {
        if (auto startOp = dyn_cast<TraceStartEventOp>(op)) {
          uint32_t startEvent = 0;
          if (auto broadcast = startOp.getBroadcast()) {
            uint32_t broadcastNum = *broadcast;
            // Resolve broadcast channel to hardware event ID
            std::string eventName;
            if (tile.isShimTile()) {
              eventName = "BROADCAST_A_" + std::to_string(broadcastNum);
            } else {
              eventName = "BROADCAST_" + std::to_string(broadcastNum);
            }
            auto eventNum = targetModel.lookupEvent(eventName, tileID, isMem);
            if (eventNum) {
              startEvent = *eventNum;
            } else {
              startOp.emitError("unknown broadcast event '")
                  << eventName << "'";
              return signalPassFailure();
            }
          } else if (auto eventAttr = startOp.getEvent()) {
            // Use getEventName() helper and check for enum
            std::string eventName = eventAttr->getEventName();
 
            std::optional<uint32_t> eventNum;
            if (auto enumVal = eventAttr->getEnumValue()) {
              eventNum = static_cast<uint32_t>(*enumVal);
            } else {
              eventNum = targetModel.lookupEvent(eventName, tileID, isMem);
            }
 
            if (eventNum) {
              startEvent = *eventNum;
            } else {
              startOp.emitError("unknown trace event '") << eventName << "'";
              return signalPassFailure();
            }
          }
 
          TraceRegOp::create(configBuilder, trace.getLoc(),
                             builder.getStringAttr("Trace_Control0"),
                             builder.getStringAttr("Trace_Start_Event"),
                             builder.getI32IntegerAttr(startEvent),
                             /*mask=*/nullptr,
                             builder.getStringAttr("start event"));
        }
 
        if (auto stopOp = dyn_cast<TraceStopEventOp>(op)) {
          uint32_t stopEvent = 0;
          if (auto broadcast = stopOp.getBroadcast()) {
            uint32_t broadcastNum = *broadcast;
            // Resolve broadcast channel to hardware event ID
            std::string eventName;
            if (tile.isShimTile()) {
              eventName = "BROADCAST_A_" + std::to_string(broadcastNum);
            } else {
              eventName = "BROADCAST_" + std::to_string(broadcastNum);
            }
            auto eventNum = targetModel.lookupEvent(eventName, tileID, isMem);
            if (eventNum) {
              stopEvent = *eventNum;
            } else {
              stopOp.emitError("unknown broadcast event '") << eventName << "'";
              return signalPassFailure();
            }
          } else if (auto eventAttr = stopOp.getEvent()) {
            // Use getEventName() helper and check for enum
            std::string eventName = eventAttr->getEventName();
 
            std::optional<uint32_t> eventNum;
            if (auto enumVal = eventAttr->getEnumValue()) {
              eventNum = static_cast<uint32_t>(*enumVal);
            } else {
              eventNum = targetModel.lookupEvent(eventName, tileID, isMem);
            }
 
            if (eventNum) {
              stopEvent = *eventNum;
            } else {
              stopOp.emitError("unknown trace event '") << eventName << "'";
              return signalPassFailure();
            }
          }
 
          TraceRegOp::create(configBuilder, trace.getLoc(),
                             builder.getStringAttr("Trace_Control0"),
                             builder.getStringAttr("Trace_Stop_Event"),
                             builder.getI32IntegerAttr(stopEvent),
                             /*mask=*/nullptr,
                             builder.getStringAttr("stop event"));
        }
 
        // Emit mode if present.
        // Only core traces expose Trace_Control0.Mode in the register DB.
        // Memory, memory_tile, and shim modules do not have the Mode field.
        bool isCore = (packetType == TracePacketType::Core);
        if (auto modeOp = dyn_cast<TraceModeOp>(op); modeOp && isCore) {
          TraceRegOp::create(configBuilder, trace.getLoc(),
                             builder.getStringAttr("Trace_Control0"),
                             builder.getStringAttr("Mode"),
                             builder.getI32IntegerAttr(
                                 static_cast<uint32_t>(modeOp.getMode())),
                             /*mask=*/nullptr,
                             builder.getStringAttr("trace mode"));
        }
 
        // Emit packet config if present. -aie-insert-trace-flows runs
        // before this pass and materializes the id, so getId() is set
        // here.
        if (auto packetOp = dyn_cast<TracePacketOp>(op)) {
          auto packetId = packetOp.getId();
          assert(packetId.has_value() &&
                 "TracePacketOp id should be assigned by "
                 "-aie-insert-trace-flows");
          TraceRegOp::create(
              configBuilder, trace.getLoc(),
              builder.getStringAttr("Trace_Control1"),
              builder.getStringAttr("ID"), builder.getI32IntegerAttr(*packetId),
              /*mask=*/nullptr, builder.getStringAttr("packet ID"));
 
          TraceRegOp::create(configBuilder, trace.getLoc(),
                             builder.getStringAttr("Trace_Control1"),
                             builder.getStringAttr("Packet_Type"),
                             builder.getI32IntegerAttr(
                                 static_cast<uint32_t>(packetOp.getType())),
                             /*mask=*/nullptr,
                             builder.getStringAttr("packet type"));
        }
      }
 
      // 2. Emit port configurations (Stream_Switch_Event_Port_Selection_0/1)
      for (auto &op : trace.getBody().getOps()) {
        if (auto portOp = dyn_cast<TracePortOp>(op)) {
          uint32_t slot = portOp.getSlot();
 
          // Determine which register based on slot
          StringRef registerName = (slot < 4)
                                       ? "Stream_Switch_Event_Port_Selection_0"
                                       : "Stream_Switch_Event_Port_Selection_1";
 
          // Generate field names
          std::string idFieldName = "Port_" + std::to_string(slot) + "_ID";
          std::string masterSlaveFieldName =
              "Port_" + std::to_string(slot) + "_Master_Slave";
 
          // Generate port value string "PORT:CHANNEL"
          std::string portValue = stringifyWireBundle(portOp.getPort()).str() +
                                  ":" + std::to_string(portOp.getChannel());
 
          // Convert DMAChannelDir to master flag: S2MM=master(1), MM2S=slave(0)
          int masterSlaveValue =
              (portOp.getDirection() == DMAChannelDir::S2MM) ? 1 : 0;
 
          // Emit Port_N_ID field
          TraceRegOp::create(
              configBuilder, portOp.getLoc(),
              builder.getStringAttr(registerName),
              builder.getStringAttr(idFieldName),
              builder.getStringAttr(portValue), // "NORTH:1" format
              /*mask=*/nullptr,
              builder.getStringAttr("port " + std::to_string(slot) + " ID"));
 
          // Emit Port_N_Master_Slave field
          TraceRegOp::create(configBuilder, portOp.getLoc(),
                             builder.getStringAttr(registerName),
                             builder.getStringAttr(masterSlaveFieldName),
                             builder.getI32IntegerAttr(masterSlaveValue),
                             /*mask=*/nullptr,
                             builder.getStringAttr("port " +
                                                   std::to_string(slot) +
                                                   " master/slave"));
        }
      }
 
      // 3. Emit event slots (Trace_Event0 / Trace_Event1)
      SmallVector<TraceEventOp> events;
      for (auto &op : trace.getBody().getOps()) {
        if (auto eventOp = dyn_cast<TraceEventOp>(op)) {
          events.push_back(eventOp);
        }
      }
 
      for (size_t i = 0; i < events.size() && i < 8; ++i) {
        std::string eventName = events[i].getEvent().getEventName();
 
        // If enum, use enum value directly; otherwise lookup by name
        std::optional<uint32_t> eventNum;
 
        if (auto enumVal = events[i].getEvent().getEnumValue()) {
          eventNum = static_cast<uint32_t>(*enumVal);
        } else {
          eventNum = targetModel.lookupEvent(eventName, tileID, isMem);
        }
 
        if (!eventNum) {
          events[i].emitError("unknown trace event '") << eventName << "'";
          return signalPassFailure();
        }
 
        // Determine which register and field
        StringRef registerName = (i < 4) ? "Trace_Event0" : "Trace_Event1";
        std::string fieldName = "Trace_Event" + std::to_string(i);
 
        // Emit register write with event number as integer
        TraceRegOp::create(
            configBuilder, trace.getLoc(), builder.getStringAttr(registerName),
            builder.getStringAttr(fieldName),
            events[i].getEvent(), // builder.getI32IntegerAttr(*eventNum),
            /*mask=*/nullptr, builder.getStringAttr(eventName));
      }
 
      // Add terminator
      EndOp::create(configBuilder, trace.getLoc());
 
      // Update all trace.start_config references
      device.walk([&](TraceStartConfigOp startConfig) {
        if (startConfig.getTraceConfig() == trace.getSymName()) {
          startConfig.setTraceConfigAttr(
              SymbolRefAttr::get(builder.getContext(), configName));
        }
      });
 
      // Remove original trace op
      trace.erase();
    }
  }
};
 
} // namespace
 
std::unique_ptr<OperationPass<DeviceOp>>
xilinx::AIE::createAIETraceToConfigPass() {
  return std::make_unique<AIETraceToConfigPass>();
}
 
//===----------------------------------------------------------------------===//
// AIETraceRegPackWritesPass - Pack multiple register field writes
//===----------------------------------------------------------------------===//
 
namespace {
 
struct AIETraceRegPackWritesPass
    : xilinx::AIE::impl::AIETraceRegPackWritesBase<AIETraceRegPackWritesPass> {
  void runOnOperation() override {
    DeviceOp device = getOperation();
    const auto &targetModel = device.getTargetModel();
 
    // Process each trace config
    device.walk([&](TraceConfigOp configOp) {
      // Determine module based on tile type and packet type
      auto tile = cast<TileOp>(configOp.getTile().getDefiningOp());
 
      // Get packet type to determine if this is memory or core trace
      bool isMem = false;
      if (auto packetType = configOp.getPacketType()) {
        isMem = (*packetType == TracePacketType::Mem);
      }
 
      // Phase 1: Convert field+value to mask+shifted_value
      SmallVector<TraceRegOp> regsToConvert;
      for (auto &op : configOp.getBody().front()) {
        if (auto regOp = dyn_cast<TraceRegOp>(op)) {
          if (regOp.getField() && !regOp.getMask()) {
            regsToConvert.push_back(regOp);
          }
        }
      }
 
      OpBuilder builder(&configOp.getBody().front(),
                        configOp.getBody().front().begin());
 
      TileID tileID = tile.getTileID();
      for (auto regOp : regsToConvert) {
        // Look up register and field information
        const RegisterInfo *regInfo =
            targetModel.lookupRegister(regOp.getRegName(), tileID, isMem);
 
        if (!regInfo) {
          regOp.emitError("Register not found in database: ")
              << regOp.getRegName();
          return signalPassFailure();
        }
 
        const BitFieldInfo *fieldInfo = regInfo->getField(*regOp.getField());
        if (!fieldInfo) {
          regOp.emitError("Field not found in register: ")
              << *regOp.getField() << " in " << regOp.getRegName();
          return signalPassFailure();
        }
 
        // Get the value - handle both integers and port strings
        uint32_t value = 0;
        Attribute valAttr = regOp.getValue();
        if (auto traceEventAttr = dyn_cast<TraceEventAttr>(valAttr)) {
          if (auto enumVal = traceEventAttr.getEnumValue()) {
            value = static_cast<uint32_t>(*enumVal);
            valAttr = builder.getI32IntegerAttr(value);
          } else {
            std::string eventName = traceEventAttr.getEventName();
            std::optional<uint32_t> eventNum =
                targetModel.lookupEvent(eventName, tileID, isMem);
            if (!eventNum) {
              regOp.emitError("unknown trace event '") << eventName << "'";
              return signalPassFailure();
            }
            value = *eventNum;
            valAttr = builder.getI32IntegerAttr(value);
          }
        }
        if (auto intAttr = dyn_cast<IntegerAttr>(valAttr)) {
          // Integer value
          value = intAttr.getInt();
        } else if (auto strAttr = dyn_cast<StringAttr>(valAttr)) {
          // String value - check if it's a port specification
          StringRef valueStr = strAttr.getValue();
 
          // Determine master/slave from field name
          // If field name contains "Master_Slave", this is not a port ID field
          // Port ID fields are named "Port_N_ID"
          bool isMasterSlaveField =
              fieldInfo->name.find("Master_Slave") != std::string::npos;
 
          if (!isMasterSlaveField && valueStr.contains(':')) {
            // This looks like "PORT:CHANNEL" format
            // We need master/slave info - look for corresponding Master_Slave
            // field
            bool master = false; // Default to slave
 
            // Derive the port slot prefix from the current field name, e.g.:
            //   "Port_1_ID" -> "Port_1"
            StringRef fieldName(fieldInfo->name);
            StringRef portSlotPrefix;
            if (fieldName.starts_with("Port_")) {
              size_t idSuffixPos = fieldName.find("_ID");
              if (idSuffixPos != std::string::npos)
                portSlotPrefix = fieldName.take_front(idSuffixPos);
            }
            // Search for companion Master_Slave field in same register and,
            // when possible, for the same port slot.
            for (auto &siblingOp : configOp.getBody().front()) {
              if (auto siblingReg = dyn_cast<TraceRegOp>(siblingOp)) {
                if (siblingReg.getRegName() != regOp.getRegName() ||
                    !siblingReg.getField())
                  continue;
                StringRef siblingFieldName = *siblingReg.getField();
                // If we could determine a slot prefix (e.g. "Port_1"), require
                // the sibling to match that slot and contain "Master_Slave".
                if (!portSlotPrefix.empty()) {
                  if (!siblingFieldName.starts_with(portSlotPrefix) ||
                      !siblingFieldName.contains("Master_Slave"))
                    continue;
                } else {
                  // Fallback: match any Master_Slave field in this register.
                  if (!siblingFieldName.contains("Master_Slave"))
                    continue;
                }
                // Found companion field - extract master flag
                if (auto siblingInt =
                        dyn_cast<IntegerAttr>(siblingReg.getValue())) {
                  master = (siblingInt.getInt() != 0);
                }
                break;
              }
            }
 
            // Resolve port value
            auto portIndex =
                targetModel.resolvePortValue(valueStr, tileID, master);
            if (!portIndex) {
              regOp.emitError("Failed to resolve port value: ") << valueStr;
              return signalPassFailure();
            }
            value = *portIndex;
          } else {
            regOp.emitError("Unsupported string value: ") << valueStr;
            return signalPassFailure();
          }
        } else {
          regOp.emitError("Unsupported value type in pack pass");
          return signalPassFailure();
        }
 
        // Compute mask and shifted value
        auto mask = targetModel.getFieldMask(*fieldInfo);
        if (!mask) {
          regOp.emitError("Invalid field bit range for register write: ")
              << regOp.getRegName() << "." << fieldInfo->name << " ["
              << fieldInfo->bit_start << ":" << fieldInfo->bit_end
              << "], width=" << fieldInfo->getWidth();
          return signalPassFailure();
        }
        auto shiftedValue = targetModel.encodeFieldValue(*fieldInfo, value);
        if (!shiftedValue) {
          regOp.emitError("Value ")
              << value << " does not fit in field " << regOp.getRegName() << "."
              << fieldInfo->name << " (width " << fieldInfo->getWidth() << ")";
          return signalPassFailure();
        }
        // Create new operation with mask
        builder.setInsertionPoint(regOp);
        TraceRegOp::create(builder, regOp.getLoc(), regOp.getRegNameAttr(),
                           nullptr, // no field
                           builder.getI32IntegerAttr(*shiftedValue),
                           builder.getI32IntegerAttr(*mask),
                           regOp.getCommentAttr());
 
        // Remove old operation
        regOp.erase();
      }
 
      // Phase 2: Merge writes to same register with non-overlapping masks
      bool changed = true;
      while (changed) {
        changed = false;
 
        // Collect all register writes
        SmallVector<TraceRegOp> regWrites;
        for (TraceRegOp op : configOp.getBody().front().getOps<TraceRegOp>()) {
          if (op.getMask()) {
            regWrites.push_back(op);
          }
        }
 
        // Try to merge pairs
        for (size_t i = 0; i < regWrites.size() && !changed; ++i) {
          for (size_t j = i + 1; j < regWrites.size() && !changed; ++j) {
            TraceRegOp reg1 = regWrites[i];
            TraceRegOp reg2 = regWrites[j];
 
            // Must be same register
            if (reg1.getRegName() != reg2.getRegName())
              continue;
 
            auto mask1Attr = reg1.getMask();
            auto mask2Attr = reg2.getMask();
            if (!mask1Attr || !mask2Attr)
              continue;
 
            uint32_t mask1 = *mask1Attr;
            uint32_t mask2 = *mask2Attr;
 
            // Check for overlap
            if (mask1 & mask2) {
              reg1.emitError("Overlapping masks for register ")
                  << reg1.getRegName() << ": mask1=" << mask1
                  << " mask2=" << mask2;
              return signalPassFailure();
            }
 
            // Merge the two writes
            auto value1Attr = dyn_cast<IntegerAttr>(reg1.getValue());
            auto value2Attr = dyn_cast<IntegerAttr>(reg2.getValue());
            if (!value1Attr || !value2Attr) {
              reg1.emitError(
                  "Expected integer values for packed register writes");
              return signalPassFailure();
            }
            uint32_t value1 = value1Attr.getInt();
            uint32_t value2 = value2Attr.getInt();
            uint32_t mergedValue = value1 | value2;
            uint32_t mergedMask = mask1 | mask2;
 
            // Create merged operation
            builder.setInsertionPoint(reg1);
            std::string comment;
            if (reg1.getComment())
              comment += reg1.getComment()->str();
            if (reg2.getComment()) {
              if (!comment.empty())
                comment += " + ";
              comment += reg2.getComment()->str();
            }
 
            TraceRegOp::create(
                builder, reg1.getLoc(), reg1.getRegNameAttr(), nullptr,
                builder.getI32IntegerAttr(mergedValue),
                builder.getI32IntegerAttr(mergedMask),
                comment.empty() ? nullptr : builder.getStringAttr(comment));
 
            // Remove both old operations
            reg1.erase();
            reg2.erase();
            changed = true;
          }
        }
      }
    });
  }
};
 
} // namespace
 
std::unique_ptr<OperationPass<DeviceOp>>
xilinx::AIE::createAIETraceRegPackWritesPass() {
  return std::make_unique<AIETraceRegPackWritesPass>();
}