xilinx::AIE::TileMemoryLimits Struct Reference

A memtile is reached by DMA rather than by core vector load and store, so its bus width also covers the vector-alignment requirement. More...

#include "aie/Dialect/AIE/Transforms/AIEBufferAllocation.h"

Collaboration diagram for xilinx::AIE::TileMemoryLimits:

Public Attributes
int64_t	maxDataMemorySize
uint32_t	tileAlignBitWidth
uint32_t	maxVecAlignBits

Detailed Description

A memtile is reached by DMA rather than by core vector load and store, so its bus width also covers the vector-alignment requirement.

Definition at line 25 of file AIEBufferAllocation.h.

Member Data Documentation

maxDataMemorySize

int64_t xilinx::AIE::TileMemoryLimits::maxDataMemorySize

Definition at line 26 of file AIEBufferAllocation.h.

maxVecAlignBits

uint32_t xilinx::AIE::TileMemoryLimits::maxVecAlignBits

Definition at line 28 of file AIEBufferAllocation.h.

tileAlignBitWidth

uint32_t xilinx::AIE::TileMemoryLimits::tileAlignBitWidth

Definition at line 27 of file AIEBufferAllocation.h.

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The documentation for this struct was generated from the following file:

• include/aie/Dialect/AIE/Transforms/AIEBufferAllocation.h