#include "aie/Dialect/AIE/IR/AIETargetModel.h"

Inheritance diagram for xilinx::AIE::AIETargetModel:

Public Types
enum	TargetModelKind { TK_AIE1_VC1902 , TK_AIE1_Last , TK_AIE2_VE2302 , TK_AIE2_VE2802 , TK_AIE2_NPU1_1Col , TK_AIE2_NPU1_2Col , TK_AIE2_NPU1_3Col , TK_AIE2_NPU1_4Col , TK_AIE2_NPU1_Last , TK_AIE2_NPU2 = TK_AIE2_NPU1_Last , TK_AIE2_NPU2_1Col , TK_AIE2_NPU2_2Col , TK_AIE2_NPU2_3Col , TK_AIE2_NPU2_4Col , TK_AIE2_NPU2_5Col , TK_AIE2_NPU2_6Col , TK_AIE2_NPU2_7Col , TK_AIE2_NPU2_Last , TK_AIE2PS_VE3858 = TK_AIE2_NPU2_Last , TK_AIE2PS_Last , TK_AIE2_Last = TK_AIE2PS_Last }
enum	ModelProperty { UsesSemaphoreLocks = 1U << 0 , IsNPU = 1U << 1 , IsVirtualized = 1U << 2 , UsesMultiDimensionalBDs = 1U << 3 , UsesBDIteration = 1U << 4 , SupportsOutOfOrderDMA = 1U << 5 }
enum class	SharedMemory { None , First , Second , Either }
	Which of two tiles' memory modules both of them can address. More...

Public Member Functions
TargetModelKind	getKind () const
	AIETargetModel (TargetModelKind k)
virtual	~AIETargetModel ()
virtual AIEArch	getTargetArch () const =0
	Return the target architecture.
virtual uint32_t	getAddressGenGranularity () const =0
	Return the data bus width of the device.
virtual int	columns () const =0
	Return the number of columns in the device.
virtual int	physicalColumns () const
	Width of the physical array this (possibly virtualized) device is carved from.
virtual int	firstPlaceableColumn () const
	First physical column at which a partition may be anchored.
std::vector< int >	partitionStartColumns (int numCols) const
	Every physical column offset at which a numCols-wide partition still fits.
virtual int	rows () const =0
	Return the number of rows in the device.
virtual uint32_t	getNumControllersPerColumn () const
	Number of microcontrollers (uC) per column.
virtual uint32_t	getNumControllers () const
	Total number of microcontrollers (uC) in the device.
virtual AIETileType	getTileType (int col, int row) const =0
	Return the tile type for the given tile coordinates.
bool	isCoreTile (int col, int row) const
	Return true if the given tile is a Core tile.
bool	isMemTile (int col, int row) const
	Return true if the given tile is a Mem tile.
bool	isShimNOCTile (int col, int row) const
	Return true if the given tile is a ShimNOC tile.
bool	isShimPLTile (int col, int row) const
	Return true if the given tile is a ShimPL tile.
bool	isShimNOCorPLTile (int col, int row) const
	Return true if the given tile is either a ShimNOC or ShimPL tile.
virtual bool	isValidTile (TileID src) const
	Return true if the given tile ID is valid.
virtual std::optional< TileID >	getMemWest (TileID src) const =0
	Return the tile ID of the memory to the west of the given tile, if it exists.
virtual std::optional< TileID >	getMemEast (TileID src) const =0
	Return the tile ID of the memory to the east of the given tile, if it exists.
virtual std::optional< TileID >	getMemNorth (TileID src) const =0
	Return the tile ID of the memory to the north of the given tile, if it exists.
virtual std::optional< TileID >	getMemSouth (TileID src) const =0
	Return the tile ID of the memory to the south of the given tile, if it exists.
bool	isInternal (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is the internal memory of dst.
bool	isWest (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is West of dst.
bool	isEast (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is East of dst.
bool	isNorth (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is North of dst.
bool	isSouth (int srcCol, int srcRow, int dstCol, int dstRow) const
	Return true if src is South of dst.
virtual bool	isMemWest (int srcCol, int srcRow, int dstCol, int dstRow) const =0
	Return true if src has a memory tile which is West of dst.
virtual bool	isMemEast (int srcCol, int srcRow, int dstCol, int dstRow) const =0
	Return true if src has a memory tile which is East of dst.
virtual bool	isMemNorth (int srcCol, int srcRow, int dstCol, int dstRow) const =0
	Return true if src has a memory tile which is North of dst.
virtual bool	isMemSouth (int srcCol, int srcRow, int dstCol, int dstRow) const =0
	Return true if src has a memory tile which is South of dst.
virtual bool	isLegalMemAffinity (int coreCol, int coreRow, int memCol, int memRow) const =0
	Return true if core can access the memory in mem.
SharedMemory	getSharedMemory (TileID a, TileID b) const
	Return the memory module a and b can both reach, if any.
virtual uint32_t	getMemInternalBaseAddress (TileID src) const =0
	Return the base address in the local address map for a core.
virtual uint32_t	getMemSouthBaseAddress () const =0
	Return the base address in the local address map for a core.
virtual uint32_t	getMemWestBaseAddress () const =0
	Return the base address in the local address map for a core.
virtual uint32_t	getMemNorthBaseAddress () const =0
	Return the base address in the local address map for a core.
virtual uint32_t	getMemEastBaseAddress () const =0
	Return the base address in the local address map for a core.
std::optional< uint32_t >	getLockLocalBaseIndex (int localCol, int localRow, int lockCol, int lockRow) const
	Return the lock base index (or offset) in the local tile when accessing a neighbor's lock or an empty optional if an invalid neighbor is given Takes into account differences between Memory and Core tiles.
std::optional< uint32_t >	getMemLocalBaseAddress (int localCol, int localRow, int memCol, int memRow) const
	Return the memory base address (or offset) in the local tile when accessing a neighbor's memory or an empty optional if an invalid neighbor is given Takes into account differences between Memory and Core tiles.
virtual uint32_t	getLocalMemorySize () const =0
	Return the size (in bytes) of the local data memory of a core.
virtual uint32_t	getProgramMemorySize () const =0
	Return the size (in bytes) of a core's program memory.
virtual uint32_t	getCoreDataAddressSpaceSize () const =0
	Return the size (in bytes) of the address space a core can issue data accesses into.
virtual uint32_t	getDefaultCoreStackSize () const
	Return the default stack reservation (in bytes) for a core that does not state one.
uint32_t	getCoreStackAlignment () const
	Stack-pointer alignment in bytes, matching Peano's AIE frame lowering: AIE1/AIE2 require 32B; AIE2P/AIE2PS require 64B, not their 32B data bus.
virtual uint32_t	getComputeTileLoadStoreBusWidth () const =0
	Return the data bus width (in bits) for load/store operations of a compute core.
virtual uint32_t	getComputeTileMaxVectorAlignBits () const
	Return the alignment (in bits) required by the widest vector load/store a compute core can issue.
virtual uint32_t	getMemTileLoadStoreBusWidth () const
	Return the data bus width (in bits) for load/store operations of a memory tile.
virtual uint32_t	getAccumulatorCascadeSize () const =0
	Return the size (in bits) of the accumulator/cascade.
virtual uint32_t	getNumLocks (AIETileType tileType) const =0
	Return the number of lock objects for a given tile type.
uint32_t	getNumLocks (int col, int row) const
	Return the number of lock objects for a tile at the given coordinates.
virtual uint32_t	getMaxLockValue () const =0
	Return the maximum value that can be stored in a lock register.
virtual std::optional< uint32_t >	getLocalLockAddress (uint32_t lockId, TileID tile) const =0
virtual uint32_t	getNumBDs (AIETileType tileType) const =0
	Return the number of buffer descriptors for a given tile type.
virtual uint32_t	getBDMaxDims (AIETileType tileType) const =0
	Return the maximum number of addressing dimensions (wraps/strides) a single buffer descriptor supports for a given tile type.
virtual uint64_t	getDmaBdMaxLen (AIETileType tileType) const =0
	Return the maximum transfer length, measured in address-generation granules (see getAddressGenGranularity(), 32-bit words on AIE2), that fits in the buffer_length field of a DMA buffer descriptor for the given tile type.
virtual uint32_t	getDmaBdWrapBits (AIETileType tileType) const =0
	Return the bit width of the wrap (size) field in a DMA buffer descriptor for the given tile type.
virtual uint32_t	getDmaBdStepBits (AIETileType tileType) const =0
	Return the bit width of the step (stride) field in a DMA buffer descriptor for the given tile type.
virtual uint32_t	getDmaBdIterBits (AIETileType tileType) const =0
	Return the bit width of the iteration (repeat) wrap/stride fields in a DMA buffer descriptor for the given tile type.
virtual std::optional< uint32_t >	getStreamSwitchPortIndex (int col, int row, WireBundle bundle, uint32_t channel, bool master) const =0
	Get stream switch port index for a given port specification Return port index for Stream_Switch_Event_Port_Selection register, or nullopt if invalid.
uint32_t	getNumBDs (int col, int row) const
	Return the number of buffer descriptors supported by the DMA in the given tile.
uint32_t	getBDMaxDims (int col, int row) const
	Return the maximum number of BD addressing dimensions for the tile at (col, row).
uint64_t	getDmaBdMaxLen (int col, int row) const
uint32_t	getDmaBdWrapBits (int col, int row) const
uint32_t	getDmaBdStepBits (int col, int row) const
uint32_t	getDmaBdIterBits (int col, int row) const
uint32_t	getNumBDsForChannel (int col, int row, int channel) const
	Return the number of buffer descriptors accessible on channel channel for the tile at (col, row).
std::pair< uint32_t, uint32_t >	getBdIdRangeForChannel (int col, int row, int channel) const
	Return the half-open range [first, last) of buffer descriptor ids that channel channel of the tile at (col, row) can submit.
virtual bool	isBdChannelAccessible (int col, int row, uint32_t bd_id, int channel) const =0
	Return true iff buffer descriptor bd_id on tile (col, row) can be submitted on channel channel.
virtual const DmaBdLayout *	getDmaBdLayout (AIETileType tileType) const
	Return the register layout of a buffer descriptor on the given tile type, or null if the target has none modeled for it.
const DmaBdLayout *	getDmaBdLayout (int col, int row) const
virtual uint64_t	getDmaBdAddress (int col, int row, uint32_t bd_id, int channel=-1, AIE::DMAChannelDir direction=AIE::DMAChannelDir::MM2S) const =0
	Return the array address of the dma buffer descriptor for the given col, row, buffer descriptor id, channel and direction.
virtual uint32_t	getDmaBdAddressOffset (int col, int row) const =0
	Return the offset of the base address field within the shim dma buffer descriptor.
virtual uint32_t	getDmaControlAddress (int col, int row, int channel, AIE::DMAChannelDir direction) const =0
	Return the array address of the dma task queue register for the given col, row, channel and direction.
virtual std::optional< uint32_t >	getDmaStatusAddress (int, int, int, AIE::DMAChannelDir) const
	Return the address of the DMA status register for a channel, or nullopt when this target's layout has not been verified.
virtual uint32_t	getDmaTaskQueueSizeMask () const
	Return the mask selecting the live task-queue occupancy field within the getDmaStatusAddress() register (0 when unsupported).
virtual uint32_t	getDmaChannelIdleMask () const
	Return the bits of the getDmaStatusAddress() register that are all clear exactly when the channel has finished every task pushed to it: nothing queued, nothing running, nothing stalled (0 when unsupported).
uint32_t	getLocalDmaControlAddress (int col, int row, int channel, AIE::DMAChannelDir direction) const
	Return the DMA task-queue register address relative to its tile.
virtual uint32_t	getNumMemTileRows () const =0
virtual uint32_t	getMemTileSize () const =0
	Return the size (in bytes) of a MemTile.
virtual uint32_t	getNumBanks (int col, int row) const =0
	Return the number of memory banks of a given tile.
virtual uint32_t	getMaxChannelNumForAdjacentMemTile (int col, int row) const =0
virtual uint32_t	getNumDestSwitchboxConnections (int col, int row, WireBundle bundle) const =0
	Return the number of destinations of connections inside a switchbox.
virtual uint32_t	getNumSourceSwitchboxConnections (int col, int row, WireBundle bundle) const =0
	Return the number of sources of connections inside a switchbox.
virtual uint32_t	getNumDestShimMuxConnections (int col, int row, WireBundle bundle) const =0
	Return the number of destinations of connections inside a shimmux.
virtual uint32_t	getNumSourceShimMuxConnections (int col, int row, WireBundle bundle) const =0
	Return the number of sources of connections inside a shimmux.
virtual uint32_t	getNumSlaveSlots () const =0
	Return the number of packet-rule slots per stream-switch slave port.
virtual uint32_t	getNumArbiters () const =0
	Return the number of arbiters per stream switch.
virtual uint32_t	getNumMselsPerArbiter () const =0
	Return the number of master select values per stream-switch arbiter.
virtual uint32_t	getMaxPacketId () const =0
	Return the largest packet id the stream switch can route.
virtual uint32_t	getMaxOutOfOrderId () const =0
	Return the largest out-of-order BD id (unsupported = 0).
virtual uint32_t	getMaxRepeatCount () const =0
	Return the largest DMA task repeat count (unsupported = 0).
virtual uint32_t	getDmaTaskQueueDepth () const =0
	Return how many DMA tasks a single channel's task queue holds (unsupported = 0).
uint32_t	getDmaTaskQueueDepth (int, int, int, AIE::DMAChannelDir) const
	Return the task-queue depth for one channel.
virtual bool	isLegalTileConnection (int col, int row, WireBundle srcBundle, int srcChan, WireBundle dstBundle, int dstChan) const =0
void	validate () const
uint32_t	getModelProperties () const
void	addModelProperty (uint32_t prop)
bool	hasProperty (ModelProperty Prop) const
virtual uint32_t	getColumnShift () const =0
virtual uint32_t	getRowShift () const =0
virtual std::vector< std::pair< uint32_t, uint32_t > >	getShimBurstEncodingsAndLengths () const =0
virtual uint32_t	getDefaultAxCache () const
virtual bool	isSupportedBlockFormat (std::string const &format) const
virtual bool	isMemTilePadValueSupported () const
const RegisterInfo *	lookupRegister (llvm::StringRef name, TileID tile, bool isMem=false) const
	Register Database API - provides access to register and event information for trace configuration and low-level register access.
std::optional< uint32_t >	lookupEvent (llvm::StringRef name, TileID tile, bool isMem=false) const
	Lookup event number by name and tile.
std::optional< uint32_t >	encodeFieldValue (const BitFieldInfo &field, uint32_t value) const
	Encode a field value with proper bit shifting.
std::optional< uint32_t >	getFieldMask (const BitFieldInfo &field) const
	Compute a 32-bit mask for a register field.
llvm::DenseMap< TileID, int >	getTileToControllerIdMap (bool columnWiseUniqueIDs=true) const
	Return a mapping from tile coordinates to controller IDs.
std::optional< uint32_t >	resolvePortValue (llvm::StringRef value, TileID tile, bool master) const
	Resolve stream switch port specification to port index.

Protected Member Functions
virtual std::unique_ptr< RegisterDatabase >	loadRegisterDatabase () const
	Subclasses override to provide architecture-specific database loading.
const RegisterDatabase *	getRegisterDatabase () const
	Get the register database, loading it lazily on first access.

Detailed Description

Definition at line 85 of file AIETargetModel.h.

Member Enumeration Documentation

◆ ModelProperty

enum xilinx::AIE::AIETargetModel::ModelProperty

Enumerator
UsesSemaphoreLocks
IsNPU
IsVirtualized
UsesMultiDimensionalBDs
UsesBDIteration
SupportsOutOfOrderDMA

Definition at line 113 of file AIETargetModel.h.

◆ SharedMemory

enum class xilinx::AIE::AIETargetModel::SharedMemory

strong

Which of two tiles' memory modules both of them can address.

Enumerator
None	Neither tile can address the other's memory module.
First	Only the first tile's module.
Second	Only the second tile's module.
Either	Either will do.

Definition at line 293 of file AIETargetModel.h.

◆ TargetModelKind

enum xilinx::AIE::AIETargetModel::TargetModelKind

Enumerator
TK_AIE1_VC1902
TK_AIE1_Last
TK_AIE2_VE2302
TK_AIE2_VE2802
TK_AIE2_NPU1_1Col
TK_AIE2_NPU1_2Col
TK_AIE2_NPU1_3Col
TK_AIE2_NPU1_4Col
TK_AIE2_NPU1_Last
TK_AIE2_NPU2
TK_AIE2_NPU2_1Col
TK_AIE2_NPU2_2Col
TK_AIE2_NPU2_3Col
TK_AIE2_NPU2_4Col
TK_AIE2_NPU2_5Col
TK_AIE2_NPU2_6Col
TK_AIE2_NPU2_7Col
TK_AIE2_NPU2_Last
TK_AIE2PS_VE3858
TK_AIE2PS_Last
TK_AIE2_Last

Definition at line 88 of file AIETargetModel.h.

Constructor & Destructor Documentation

◆ AIETargetModel()

xilinx::AIE::AIETargetModel::AIETargetModel ( TargetModelKind k )

inline

Definition at line 152 of file AIETargetModel.h.

Referenced by xilinx::AIE::AIE1TargetModel::AIE1TargetModel(), xilinx::AIE::AIE2TargetModel::AIE2TargetModel(), xilinx::AIE::AIE1TargetModel::classof(), and xilinx::AIE::AIE2TargetModel::classof().

◆ ~AIETargetModel()

xilinx::AIE::AIETargetModel::~AIETargetModel ( )

virtualdefault

Member Function Documentation

◆ addModelProperty()

void xilinx::AIE::AIETargetModel::addModelProperty ( uint32_t prop )

inline

Definition at line 642 of file AIETargetModel.h.

Referenced by xilinx::AIE::AIE2PSTargetModel::AIE2PSTargetModel(), xilinx::AIE::AIE2TargetModel::AIE2TargetModel(), xilinx::AIE::BaseNPU1TargetModel::BaseNPU1TargetModel(), xilinx::AIE::BaseNPU2TargetModel::BaseNPU2TargetModel(), xilinx::AIE::VirtualizedNPU1TargetModel::VirtualizedNPU1TargetModel(), and xilinx::AIE::VirtualizedNPU2TargetModel::VirtualizedNPU2TargetModel().

◆ columns()

virtual int xilinx::AIE::AIETargetModel::columns ( ) const

pure virtual

Return the number of columns in the device.

Implemented in xilinx::AIE::NPU2TargetModel, xilinx::AIE::VC1902TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, xilinx::AIE::VE3858TargetModel, xilinx::AIE::VirtualizedNPU1TargetModel, and xilinx::AIE::VirtualizedNPU2TargetModel.

Referenced by xilinx::AIE::AIERTControl::AIERTControl(), xilinx::AIE::forEachMemAffinityNeighbor(), getNumControllers(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), getRowToShimChanMap(), getTileToControllerIdMap(), xilinx::AIE::Placer::initialize(), isValidTile(), physicalColumns(), and validate().

◆ encodeFieldValue()

std::optional< uint32_t > xilinx::AIE::AIETargetModel::encodeFieldValue	(	const BitFieldInfo &	field,
		uint32_t	value ) const

Encode a field value with proper bit shifting.

Return nullopt if value does not fit in the field's bit width.

Definition at line 78 of file AIETargetModel.cpp.

References getRegisterDatabase().

Referenced by AIEDMATasksToNPUPass::emitOutOfOrderChannelEnable().

◆ firstPlaceableColumn()

virtual int xilinx::AIE::AIETargetModel::firstPlaceableColumn ( ) const

inlinevirtual

First physical column at which a partition may be anchored.

Definition at line 171 of file AIETargetModel.h.

Referenced by partitionStartColumns().

◆ getAccumulatorCascadeSize()

virtual uint32_t xilinx::AIE::AIETargetModel::getAccumulatorCascadeSize ( ) const

pure virtual

Return the size (in bits) of the accumulator/cascade.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getAddressGenGranularity()

virtual uint32_t xilinx::AIE::AIETargetModel::getAddressGenGranularity ( ) const

pure virtual

Return the data bus width of the device.

Implemented in xilinx::AIE::AIE2TargetModel, and xilinx::AIE::VC1902TargetModel.

Referenced by aieDmaBdFits(), xilinx::AIEX::getHardwareStridesWraps(), and AIEDMATasksToNPUPass::rewriteSingleBD().

◆ getBdIdRangeForChannel()

std::pair< uint32_t, uint32_t > xilinx::AIE::AIETargetModel::getBdIdRangeForChannel	(	int	col,
		int	row,
		int	channel ) const

inline

Return the half-open range [first, last) of buffer descriptor ids that channel channel of the tile at (col, row) can submit.

Definition at line 504 of file AIETargetModel.h.

References getNumBDs(), and isBdChannelAccessible().

◆ getBDMaxDims() [1/2]

virtual uint32_t xilinx::AIE::AIETargetModel::getBDMaxDims ( AIETileType tileType ) const

pure virtual

Return the maximum number of addressing dimensions (wraps/strides) a single buffer descriptor supports for a given tile type.

This is the hardware ND access-pattern limit; it does not count the separate shim iteration/repeat dimension that runtime-sequence BD tasks hoist the leading tap dimension into.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getBDMaxDims().

◆ getBDMaxDims() [2/2]

uint32_t xilinx::AIE::AIETargetModel::getBDMaxDims	(	int	col,
		int	row ) const

inline

Return the maximum number of BD addressing dimensions for the tile at (col, row).

Definition at line 471 of file AIETargetModel.h.

References getBDMaxDims(), and getTileType().

◆ getColumnShift()

virtual uint32_t xilinx::AIE::AIETargetModel::getColumnShift ( ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getComputeTileLoadStoreBusWidth()

virtual uint32_t xilinx::AIE::AIETargetModel::getComputeTileLoadStoreBusWidth ( ) const

pure virtual

Return the data bus width (in bits) for load/store operations of a compute core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getComputeTileMaxVectorAlignBits(), and xilinx::AIE::tileMemoryLimits().

◆ getComputeTileMaxVectorAlignBits()

virtual uint32_t xilinx::AIE::AIETargetModel::getComputeTileMaxVectorAlignBits ( ) const

inlinevirtual

Return the alignment (in bits) required by the widest vector load/store a compute core can issue.

This is NOT the load/store bus width. From AIE2P on, a full-width (512-bit) vector access requires 512-bit alignment even though the bus is 256 bits wide. Mirrors vector_ldst_align in aie_api (aie_api/detail/ld_st.hpp), which is the contract kernels compile against: AIE1 (AIE_ARCH 10): 16B AIE2 (AIE_ARCH 20): 32B AIE2P/AIE2PS (AIE_ARCH 21/22): 64B A buffer a core may access with a full-width vector must be aligned to this, or the access silently touches the wrong memory.

Reimplemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2PSTargetModel, xilinx::AIE::AIE2TargetModel, and xilinx::AIE::BaseNPU2TargetModel.

Definition at line 392 of file AIETargetModel.h.

References getComputeTileLoadStoreBusWidth().

Referenced by xilinx::AIE::tileMemoryLimits().

◆ getCoreDataAddressSpaceSize()

virtual uint32_t xilinx::AIE::AIETargetModel::getCoreDataAddressSpaceSize ( ) const

pure virtual

Return the size (in bytes) of the address space a core can issue data accesses into.

The neighbour memory windows sit at the bottom of it; the span above them reaches no memory and is reserved so nothing is placed there.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getCoreStackAlignment()

uint32_t xilinx::AIE::AIETargetModel::getCoreStackAlignment ( ) const

inline

Stack-pointer alignment in bytes, matching Peano's AIE frame lowering: AIE1/AIE2 require 32B; AIE2P/AIE2PS require 64B, not their 32B data bus.

Definition at line 371 of file AIETargetModel.h.

References getTargetArch().

◆ getDefaultAxCache()

virtual uint32_t xilinx::AIE::AIETargetModel::getDefaultAxCache ( ) const

inlinevirtual

Definition at line 668 of file AIETargetModel.h.

◆ getDefaultCoreStackSize()

virtual uint32_t xilinx::AIE::AIETargetModel::getDefaultCoreStackSize ( ) const

inlinevirtual

Return the default stack reservation (in bytes) for a core that does not state one.

It is also the floor when aiecc sizes the stack from its measurement. The linker script places the stack directly below the objectFIFO buffers with no clearance, so a design whose frames exceed its reservation corrupts them instead of faulting.

Definition at line 367 of file AIETargetModel.h.

◆ getDmaBdAddress()

virtual uint64_t xilinx::AIE::AIETargetModel::getDmaBdAddress	(	int	col,
		int	row,
		uint32_t	bd_id,
		int	channel = -1,
		AIE::DMAChannelDir	direction = AIE::DMAChannelDir::MM2S ) const

pure virtual

Return the array address of the dma buffer descriptor for the given col, row, buffer descriptor id, channel and direction.

Not all architecture variants will use channel and direction so these have default values.

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2PSTargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIEX::emitUpdateBdLengthFromParameter(), and xilinx::AIEX::getBdRegisterBase().

◆ getDmaBdAddressOffset()

virtual uint32_t xilinx::AIE::AIETargetModel::getDmaBdAddressOffset	(	int	col,
		int	row ) const

pure virtual

Return the offset of the base address field within the shim dma buffer descriptor.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getDmaBdIterBits() [1/2]

virtual uint32_t xilinx::AIE::AIETargetModel::getDmaBdIterBits ( AIETileType tileType ) const

pure virtual

Return the bit width of the iteration (repeat) wrap/stride fields in a DMA buffer descriptor for the given tile type.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getDmaBdIterBits(), and xilinx::AIE::verifyDMABDIteration().

◆ getDmaBdIterBits() [2/2]

uint32_t xilinx::AIE::AIETargetModel::getDmaBdIterBits	(	int	col,
		int	row ) const

inline

Definition at line 487 of file AIETargetModel.h.

References getDmaBdIterBits(), and getTileType().

◆ getDmaBdLayout() [1/2]

virtual const DmaBdLayout * xilinx::AIE::AIETargetModel::getDmaBdLayout ( AIETileType tileType ) const

inlinevirtual

Return the register layout of a buffer descriptor on the given tile type, or null if the target has none modeled for it.

Reimplemented in xilinx::AIE::AIE2TargetModel.

Definition at line 523 of file AIETargetModel.h.

Referenced by xilinx::AIEX::buildBdWords(), xilinx::AIEX::emitUpdateBdLengthFromParameter(), and getDmaBdLayout().

◆ getDmaBdLayout() [2/2]

const DmaBdLayout * xilinx::AIE::AIETargetModel::getDmaBdLayout	(	int	col,
		int	row ) const

inline

Definition at line 527 of file AIETargetModel.h.

References getDmaBdLayout(), and getTileType().

◆ getDmaBdMaxLen() [1/2]

virtual uint64_t xilinx::AIE::AIETargetModel::getDmaBdMaxLen ( AIETileType tileType ) const

pure virtual

Return the maximum transfer length, measured in address-generation granules (see getAddressGenGranularity(), 32-bit words on AIE2), that fits in the buffer_length field of a DMA buffer descriptor for the given tile type.

The field width is tile-type specific (e.g. on AIE2 the shim field is 32 bits, the mem-tile field 17 bits and the core-tile field 14 bits).

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by aieDmaBdFits(), and getDmaBdMaxLen().

◆ getDmaBdMaxLen() [2/2]

uint64_t xilinx::AIE::AIETargetModel::getDmaBdMaxLen	(	int	col,
		int	row ) const

inline

Definition at line 475 of file AIETargetModel.h.

References getDmaBdMaxLen(), and getTileType().

◆ getDmaBdStepBits() [1/2]

virtual uint32_t xilinx::AIE::AIETargetModel::getDmaBdStepBits ( AIETileType tileType ) const

pure virtual

Return the bit width of the step (stride) field in a DMA buffer descriptor for the given tile type.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getDmaBdStepBits(), and xilinx::AIE::verifyDMABDIteration().

◆ getDmaBdStepBits() [2/2]

uint32_t xilinx::AIE::AIETargetModel::getDmaBdStepBits	(	int	col,
		int	row ) const

inline

Definition at line 483 of file AIETargetModel.h.

References getDmaBdStepBits(), and getTileType().

◆ getDmaBdWrapBits() [1/2]

virtual uint32_t xilinx::AIE::AIETargetModel::getDmaBdWrapBits ( AIETileType tileType ) const

pure virtual

Return the bit width of the wrap (size) field in a DMA buffer descriptor for the given tile type.

Used to compute the maximum legal wrap value per dimension.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getDmaBdWrapBits().

◆ getDmaBdWrapBits() [2/2]

uint32_t xilinx::AIE::AIETargetModel::getDmaBdWrapBits	(	int	col,
		int	row ) const

inline

Definition at line 479 of file AIETargetModel.h.

References getDmaBdWrapBits(), and getTileType().

◆ getDmaChannelIdleMask()

virtual uint32_t xilinx::AIE::AIETargetModel::getDmaChannelIdleMask ( ) const

inlinevirtual

Return the bits of the getDmaStatusAddress() register that are all clear exactly when the channel has finished every task pushed to it: nothing queued, nothing running, nothing stalled (0 when unsupported).

Reimplemented in xilinx::AIE::AIE2TargetModel.

Definition at line 567 of file AIETargetModel.h.

Referenced by xilinx::AIEX::guardSequenceQueueDepth().

◆ getDmaControlAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getDmaControlAddress	(	int	col,
		int	row,
		int	channel,
		AIE::DMAChannelDir	direction ) const

pure virtual

Return the array address of the dma task queue register for the given col, row, channel and direction.

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2PSTargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getLocalDmaControlAddress().

◆ getDmaStatusAddress()

virtual std::optional< uint32_t > xilinx::AIE::AIETargetModel::getDmaStatusAddress	(	int	,
		int	,
		int	,
		AIE::DMAChannelDir	) const

inlinevirtual

Return the address of the DMA status register for a channel, or nullopt when this target's layout has not been verified.

The register carries the live task-queue occupancy in getDmaTaskQueueSizeMask(), which is the only way to observe queue space: the queue does not backpressure, so a push onto a full queue is dropped rather than stalled.

Reimplemented in xilinx::AIE::AIE2PSTargetModel, and xilinx::AIE::AIE2TargetModel.

Definition at line 554 of file AIETargetModel.h.

Referenced by xilinx::AIEX::guardSequenceQueueDepth(), and xilinx::AIEX::queueSpacePoll().

◆ getDmaTaskQueueDepth() [1/2]

virtual uint32_t xilinx::AIE::AIETargetModel::getDmaTaskQueueDepth ( ) const

pure virtual

Return how many DMA tasks a single channel's task queue holds (unsupported = 0).

Pushing to a full queue drops the push and sets the channel's sticky Task_Queue_Overflow bit, stranding whoever waits on that transfer. Flat rather than per-tile-type because aie-rt's XAie_DmaGetMaxQueueSize (XAIE_DMA_MAX_QUEUE_SIZE) returns the same depth for every tile type and architecture.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getDmaTaskQueueDepth(), and xilinx::AIEX::guardSequenceQueueDepth().

◆ getDmaTaskQueueDepth() [2/2]

uint32_t xilinx::AIE::AIETargetModel::getDmaTaskQueueDepth	(	int	,
		int	,
		int	,
		AIE::DMAChannelDir	) const

inline

Return the task-queue depth for one channel.

The queue is a per-channel resource in hardware, but no shipping target gives channels different depths, so this forwards to the flat accessor; carrying the parameters spares call sites churn if one ever does.

Definition at line 628 of file AIETargetModel.h.

References getDmaTaskQueueDepth().

◆ getDmaTaskQueueSizeMask()

virtual uint32_t xilinx::AIE::AIETargetModel::getDmaTaskQueueSizeMask ( ) const

inlinevirtual

Return the mask selecting the live task-queue occupancy field within the getDmaStatusAddress() register (0 when unsupported).

The field does not count the task the channel is running.

Reimplemented in xilinx::AIE::AIE2TargetModel.

Definition at line 562 of file AIETargetModel.h.

Referenced by xilinx::AIEX::guardSequenceQueueDepth(), and xilinx::AIEX::queueSpacePoll().

◆ getFieldMask()

std::optional< uint32_t > xilinx::AIE::AIETargetModel::getFieldMask ( const BitFieldInfo & field ) const

Compute a 32-bit mask for a register field.

Return nullopt if the field does not fit in a 32-bit register.

Definition at line 87 of file AIETargetModel.cpp.

References xilinx::AIE::BitFieldInfo::bit_end, xilinx::AIE::BitFieldInfo::bit_start, and xilinx::AIE::BitFieldInfo::getWidth().

Referenced by AIEDMATasksToNPUPass::emitOutOfOrderChannelEnable().

◆ getKind()

TargetModelKind xilinx::AIE::AIETargetModel::getKind ( ) const

inline

Definition at line 150 of file AIETargetModel.h.

◆ getLocalDmaControlAddress()

uint32_t xilinx::AIE::AIETargetModel::getLocalDmaControlAddress	(	int	col,
		int	row,
		int	channel,
		AIE::DMAChannelDir	direction ) const

inline

Return the DMA task-queue register address relative to its tile.

Definition at line 570 of file AIETargetModel.h.

References getDmaControlAddress(), and getRowShift().

Referenced by AIEDMATasksToNPUPass::emitOutOfOrderChannelEnable(), and DmaChannelResetToMaskWrite32Pattern::matchAndRewrite().

◆ getLocalLockAddress()

virtual std::optional< uint32_t > xilinx::AIE::AIETargetModel::getLocalLockAddress	(	uint32_t	lockId,
		TileID	tile ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by SetLockToWrite32Pattern::matchAndRewrite().

◆ getLocalMemorySize()

virtual uint32_t xilinx::AIE::AIETargetModel::getLocalMemorySize ( ) const

pure virtual

Return the size (in bytes) of the local data memory of a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::tileMemoryLimits().

◆ getLockLocalBaseIndex()

std::optional< uint32_t > xilinx::AIE::AIETargetModel::getLockLocalBaseIndex	(	int	localCol,
		int	localRow,
		int	lockCol,
		int	lockRow ) const

Return the lock base index (or offset) in the local tile when accessing a neighbor's lock or an empty optional if an invalid neighbor is given Takes into account differences between Memory and Core tiles.

Definition at line 1692 of file AIETargetModel.cpp.

References getNumLocks(), isCoreTile(), isEast(), isInternal(), isMemEast(), isMemNorth(), isMemSouth(), isMemTile(), isMemWest(), and isWest().

Referenced by AIEDMATasksToNPUPass::gatherBdTemplateFields().

◆ getMaxChannelNumForAdjacentMemTile()

virtual uint32_t xilinx::AIE::AIETargetModel::getMaxChannelNumForAdjacentMemTile	(	int	col,
		int	row ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getMaxLockValue()

virtual uint32_t xilinx::AIE::AIETargetModel::getMaxLockValue ( ) const

pure virtual

Return the maximum value that can be stored in a lock register.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by AIEDMATasksToNPUPass::gatherBdTemplateFields().

◆ getMaxOutOfOrderId()

virtual uint32_t xilinx::AIE::AIETargetModel::getMaxOutOfOrderId ( ) const

pure virtual

Return the largest out-of-order BD id (unsupported = 0).

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::verifyDMABDOutOfOrderId().

◆ getMaxPacketId()

virtual uint32_t xilinx::AIE::AIETargetModel::getMaxPacketId ( ) const

pure virtual

Return the largest packet id the stream switch can route.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getMaxRepeatCount()

virtual uint32_t xilinx::AIE::AIETargetModel::getMaxRepeatCount ( ) const

pure virtual

Return the largest DMA task repeat count (unsupported = 0).

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getMemEast()

virtual std::optional< TileID > xilinx::AIE::AIETargetModel::getMemEast ( TileID src ) const

pure virtual

Return the tile ID of the memory to the east of the given tile, if it exists.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getMemEastBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemEastBaseAddress ( ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getMemLocalBaseAddress().

◆ getMemInternalBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemInternalBaseAddress ( TileID src ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getMemLocalBaseAddress()

std::optional< uint32_t > xilinx::AIE::AIETargetModel::getMemLocalBaseAddress	(	int	localCol,
		int	localRow,
		int	memCol,
		int	memRow ) const

Return the memory base address (or offset) in the local tile when accessing a neighbor's memory or an empty optional if an invalid neighbor is given Takes into account differences between Memory and Core tiles.

Definition at line 1718 of file AIETargetModel.cpp.

References getMemEastBaseAddress(), getMemNorthBaseAddress(), getMemSouthBaseAddress(), getMemTileSize(), getMemWestBaseAddress(), isCoreTile(), isEast(), isInternal(), isMemEast(), isMemNorth(), isMemSouth(), isMemTile(), isMemWest(), and isWest().

◆ getMemNorth()

virtual std::optional< TileID > xilinx::AIE::AIETargetModel::getMemNorth ( TileID src ) const

pure virtual

Return the tile ID of the memory to the north of the given tile, if it exists.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getMemNorthBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemNorthBaseAddress ( ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getMemLocalBaseAddress().

◆ getMemSouth()

virtual std::optional< TileID > xilinx::AIE::AIETargetModel::getMemSouth ( TileID src ) const

pure virtual

Return the tile ID of the memory to the south of the given tile, if it exists.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getMemSouthBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemSouthBaseAddress ( ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getMemLocalBaseAddress().

◆ getMemTileLoadStoreBusWidth()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemTileLoadStoreBusWidth ( ) const

inlinevirtual

Return the data bus width (in bits) for load/store operations of a memory tile.

Definition at line 400 of file AIETargetModel.h.

Referenced by xilinx::AIE::tileMemoryLimits().

◆ getMemTileSize()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemTileSize ( ) const

pure virtual

Return the size (in bytes) of a MemTile.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getMemLocalBaseAddress(), and xilinx::AIE::tileMemoryLimits().

◆ getMemWest()

virtual std::optional< TileID > xilinx::AIE::AIETargetModel::getMemWest ( TileID src ) const

pure virtual

Return the tile ID of the memory to the west of the given tile, if it exists.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getMemWestBaseAddress()

virtual uint32_t xilinx::AIE::AIETargetModel::getMemWestBaseAddress ( ) const

pure virtual

Return the base address in the local address map for a core.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getMemLocalBaseAddress().

◆ getModelProperties()

uint32_t xilinx::AIE::AIETargetModel::getModelProperties ( ) const

inline

Definition at line 641 of file AIETargetModel.h.

Referenced by hasProperty().

◆ getNumArbiters()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumArbiters ( ) const

pure virtual

Return the number of arbiters per stream switch.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getNumBanks()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumBanks	(	int	col,
		int	row ) const

pure virtual

Return the number of memory banks of a given tile.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getNumBDs() [1/2]

virtual uint32_t xilinx::AIE::AIETargetModel::getNumBDs ( AIETileType tileType ) const

pure virtual

Return the number of buffer descriptors for a given tile type.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getBdIdRangeForChannel(), getNumBDs(), and getNumBDsForChannel().

◆ getNumBDs() [2/2]

uint32_t xilinx::AIE::AIETargetModel::getNumBDs	(	int	col,
		int	row ) const

inline

Return the number of buffer descriptors supported by the DMA in the given tile.

Definition at line 465 of file AIETargetModel.h.

References getNumBDs(), and getTileType().

◆ getNumBDsForChannel()

uint32_t xilinx::AIE::AIETargetModel::getNumBDsForChannel	(	int	col,
		int	row,
		int	channel ) const

inline

Return the number of buffer descriptors accessible on channel channel for the tile at (col, row).

For tiles with no per-channel BD partitioning this equals getNumBDs(col, row).

Definition at line 494 of file AIETargetModel.h.

References getNumBDs(), and isBdChannelAccessible().

Referenced by AIEAssignBufferDescriptorIDsPass::runOnOperation().

◆ getNumControllers()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumControllers ( ) const

inlinevirtual

Total number of microcontrollers (uC) in the device.

Defaults to columns() * getNumControllersPerColumn(); architectures with a single device-level uC (e.g. AIE2/AIE2P NPUs) override this directly instead, since their controller count doesn't scale with column count.

Reimplemented in xilinx::AIE::BaseNPU1TargetModel, and xilinx::AIE::BaseNPU2TargetModel.

Definition at line 192 of file AIETargetModel.h.

References columns(), and getNumControllersPerColumn().

◆ getNumControllersPerColumn()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumControllersPerColumn ( ) const

inlinevirtual

Number of microcontrollers (uC) per column.

Reimplemented in xilinx::AIE::AIE2PSTargetModel.

Definition at line 185 of file AIETargetModel.h.

Referenced by getNumControllers().

◆ getNumDestShimMuxConnections()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumDestShimMuxConnections	(	int	col,
		int	row,
		WireBundle	bundle ) const

pure virtual

Return the number of destinations of connections inside a shimmux.

These are the targets of connect operations in the switchbox.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::getDMACapacity(), and xilinx::AIE::Pathfinder::initialize().

◆ getNumDestSwitchboxConnections()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumDestSwitchboxConnections	(	int	col,
		int	row,
		WireBundle	bundle ) const

pure virtual

Return the number of destinations of connections inside a switchbox.

These are the targets of connect operations in the switchbox.

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2PSTargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::getDMACapacity(), xilinx::AIE::Pathfinder::initialize(), and validate().

◆ getNumLocks() [1/2]

virtual uint32_t xilinx::AIE::AIETargetModel::getNumLocks ( AIETileType tileType ) const

pure virtual

Return the number of lock objects for a given tile type.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getLockLocalBaseIndex(), getNumLocks(), and AIEAssignLockIDsPass::runOnOperation().

◆ getNumLocks() [2/2]

uint32_t xilinx::AIE::AIETargetModel::getNumLocks	(	int	col,
		int	row ) const

inline

Return the number of lock objects for a tile at the given coordinates.

Definition at line 414 of file AIETargetModel.h.

References getNumLocks(), and getTileType().

◆ getNumMemTileRows()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumMemTileRows ( ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::BaseNPU1TargetModel, xilinx::AIE::BaseNPU2TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, and xilinx::AIE::VE3858TargetModel.

Referenced by validate().

◆ getNumMselsPerArbiter()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumMselsPerArbiter ( ) const

pure virtual

Return the number of master select values per stream-switch arbiter.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getNumSlaveSlots()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumSlaveSlots ( ) const

pure virtual

Return the number of packet-rule slots per stream-switch slave port.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getNumSourceShimMuxConnections()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumSourceShimMuxConnections	(	int	col,
		int	row,
		WireBundle	bundle ) const

pure virtual

Return the number of sources of connections inside a shimmux.

These are the origins of connect operations in the switchbox.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::getDMACapacity(), getRowToShimChanMap(), and xilinx::AIE::Pathfinder::initialize().

◆ getNumSourceSwitchboxConnections()

virtual uint32_t xilinx::AIE::AIETargetModel::getNumSourceSwitchboxConnections	(	int	col,
		int	row,
		WireBundle	bundle ) const

pure virtual

Return the number of sources of connections inside a switchbox.

These are the origins of connect operations in the switchbox.

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2PSTargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::getDMACapacity(), xilinx::AIE::Pathfinder::initialize(), and validate().

◆ getProgramMemorySize()

virtual uint32_t xilinx::AIE::AIETargetModel::getProgramMemorySize ( ) const

pure virtual

Return the size (in bytes) of a core's program memory.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

◆ getRegisterDatabase()

const RegisterDatabase * xilinx::AIE::AIETargetModel::getRegisterDatabase ( ) const

protected

Get the register database, loading it lazily on first access.

Throws fatal error if database is required but unavailable.

Definition at line 54 of file AIETargetModel.cpp.

References loadRegisterDatabase().

Referenced by encodeFieldValue(), lookupEvent(), and lookupRegister().

◆ getRowShift()

virtual uint32_t xilinx::AIE::AIETargetModel::getRowShift ( ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getLocalDmaControlAddress().

◆ getSharedMemory()

SharedMemory xilinx::AIE::AIETargetModel::getSharedMemory	(	TileID	a,
		TileID	b ) const

inline

Return the memory module a and b can both reach, if any.

Definition at line 305 of file AIETargetModel.h.

References Either, First, isLegalMemAffinity(), isMemTile(), isShimNOCorPLTile(), None, and Second.

Referenced by xilinx::AIE::sharedMemory().

◆ getShimBurstEncodingsAndLengths()

virtual std::vector< std::pair< uint32_t, uint32_t > > xilinx::AIE::AIETargetModel::getShimBurstEncodingsAndLengths ( ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2PSTargetModel, xilinx::AIE::AIE2TargetModel, and xilinx::AIE::BaseNPU2TargetModel.

◆ getStreamSwitchPortIndex()

virtual std::optional< uint32_t > xilinx::AIE::AIETargetModel::getStreamSwitchPortIndex	(	int	col,
		int	row,
		WireBundle	bundle,
		uint32_t	channel,
		bool	master ) const

pure virtual

Get stream switch port index for a given port specification Return port index for Stream_Switch_Event_Port_Selection register, or nullopt if invalid.

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2PSTargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by resolvePortValue().

◆ getTargetArch()

virtual AIEArch xilinx::AIE::AIETargetModel::getTargetArch ( ) const

pure virtual

Return the target architecture.

Implemented in xilinx::AIE::AIE1TargetModel, xilinx::AIE::AIE2PSTargetModel, xilinx::AIE::AIE2TargetModel, and xilinx::AIE::BaseNPU2TargetModel.

Referenced by xilinx::AIE::AIERTControl::AIERTControl(), and getCoreStackAlignment().

◆ getTileToControllerIdMap()

DenseMap< TileID, int > xilinx::AIE::AIETargetModel::getTileToControllerIdMap ( bool columnWiseUniqueIDs = true ) const

Return a mapping from tile coordinates to controller IDs.

When columnWiseUniqueIDs is true (default), IDs are unique within each column. Otherwise they are globally unique across the device.

Definition at line 101 of file AIETargetModel.cpp.

References columns(), and rows().

Referenced by getTileToControllerIdMap().

◆ getTileType()

virtual AIETileType xilinx::AIE::AIETargetModel::getTileType	(	int	col,
		int	row ) const

pure virtual

Return the tile type for the given tile coordinates.

CoreTile: tiles with a Core, TileDMA, tile memory, and stream connections.
MemTile: tiles with TileDMA, tile memory, and stream connections, but no core.
ShimNOCTile: tiles with ShimDMA and connection to the memory-mapped NOC.
ShimPLTile: tiles with connections to the PL, no ShimDMA.

Implemented in xilinx::AIE::BaseNPU2TargetModel, xilinx::AIE::VC1902TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, xilinx::AIE::VE3858TargetModel, and xilinx::AIE::VirtualizedNPU1TargetModel.

Referenced by xilinx::AIE::forEachMemAffinityNeighbor(), getBDMaxDims(), getDmaBdIterBits(), getDmaBdLayout(), getDmaBdMaxLen(), getDmaBdStepBits(), getDmaBdWrapBits(), xilinx::AIE::AIE2TargetModel::getNumBanks(), getNumBDs(), getNumLocks(), xilinx::AIE::Placer::initialize(), xilinx::AIE::AIE2TargetModel::isBdChannelAccessible(), isCoreTile(), isMemTile(), isShimNOCorPLTile(), isShimNOCTile(), and isShimPLTile().

◆ hasProperty()

bool xilinx::AIE::AIETargetModel::hasProperty ( ModelProperty Prop ) const

inline

Definition at line 644 of file AIETargetModel.h.

References getModelProperties().

Referenced by xilinx::AIE::AIERTControl::AIERTControl(), xilinx::AIE::verifyDMABDIteration(), and xilinx::AIE::verifyDMABDOutOfOrderId().

◆ isBdChannelAccessible()

virtual bool xilinx::AIE::AIETargetModel::isBdChannelAccessible	(	int	col,
		int	row,
		uint32_t	bd_id,
		int	channel ) const

pure virtual

Return true iff buffer descriptor bd_id on tile (col, row) can be submitted on channel channel.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getBdIdRangeForChannel(), getNumBDsForChannel(), and AIEAssignBufferDescriptorIDsPass::runOnOperation().

◆ isCoreTile()

bool xilinx::AIE::AIETargetModel::isCoreTile	(	int	col,
		int	row ) const

inline

Return true if the given tile is a Core tile.

Definition at line 206 of file AIETargetModel.h.

References getTileType().

Referenced by xilinx::AIE::AIE1TargetModel::getDmaBdAddress(), xilinx::AIE::AIE2TargetModel::getDmaBdAddress(), xilinx::AIE::AIE1TargetModel::getDmaBdAddressOffset(), xilinx::AIE::AIE2TargetModel::getDmaBdAddressOffset(), xilinx::AIE::AIE1TargetModel::getDmaControlAddress(), xilinx::AIE::AIE2TargetModel::getDmaControlAddress(), xilinx::AIE::AIE2TargetModel::getDmaStatusAddress(), xilinx::AIE::AIE2TargetModel::getLocalLockAddress(), getLockLocalBaseIndex(), getMemLocalBaseAddress(), xilinx::AIE::AIE1TargetModel::getStreamSwitchPortIndex(), xilinx::AIE::AIE2TargetModel::getStreamSwitchPortIndex(), xilinx::AIE::AIE1TargetModel::isLegalTileConnection(), xilinx::AIE::AIE2TargetModel::isLegalTileConnection(), AIEDMATasksToNPUPass::rewriteSingleBD(), and validate().

◆ isEast()

bool xilinx::AIE::AIETargetModel::isEast	(	int	srcCol,
		int	srcRow,
		int	dstCol,
		int	dstRow ) const

inline

Return true if src is East of dst.

Definition at line 261 of file AIETargetModel.h.

Referenced by getLockLocalBaseIndex(), getMemLocalBaseAddress(), xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE2TargetModel::isLegalMemAffinity(), and xilinx::AIE::AIE1TargetModel::isMemEast().

◆ isInternal()

bool xilinx::AIE::AIETargetModel::isInternal	(	int	srcCol,
		int	srcRow,
		int	dstCol,
		int	dstRow ) const

inline

Return true if src is the internal memory of dst.

Definition at line 251 of file AIETargetModel.h.

Referenced by getLockLocalBaseIndex(), getMemLocalBaseAddress(), xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE2TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE1TargetModel::isMemEast(), xilinx::AIE::AIE2TargetModel::isMemEast(), and xilinx::AIE::AIE1TargetModel::isMemWest().

◆ isLegalMemAffinity()

virtual bool xilinx::AIE::AIETargetModel::isLegalMemAffinity	(	int	coreCol,
		int	coreRow,
		int	memCol,
		int	memRow ) const

pure virtual

Return true if core can access the memory in mem.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getSharedMemory(), and xilinx::AIE::isSharedComputeMemory().

◆ isLegalTileConnection()

virtual bool xilinx::AIE::AIETargetModel::isLegalTileConnection	(	int	col,
		int	row,
		WireBundle	srcBundle,
		int	srcChan,
		WireBundle	dstBundle,
		int	dstChan ) const

pure virtual

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by xilinx::AIE::Pathfinder::initialize().

◆ isMemEast()

virtual bool xilinx::AIE::AIETargetModel::isMemEast	(	int	srcCol,
		int	srcRow,
		int	dstCol,
		int	dstRow ) const

pure virtual

Return true if src has a memory tile which is East of dst.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getLockLocalBaseIndex(), and getMemLocalBaseAddress().

◆ isMemNorth()

virtual bool xilinx::AIE::AIETargetModel::isMemNorth	(	int	srcCol,
		int	srcRow,
		int	dstCol,
		int	dstRow ) const

pure virtual

Return true if src has a memory tile which is North of dst.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getLockLocalBaseIndex(), and getMemLocalBaseAddress().

◆ isMemSouth()

virtual bool xilinx::AIE::AIETargetModel::isMemSouth	(	int	srcCol,
		int	srcRow,
		int	dstCol,
		int	dstRow ) const

pure virtual

Return true if src has a memory tile which is South of dst.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getLockLocalBaseIndex(), and getMemLocalBaseAddress().

◆ isMemTile()

bool xilinx::AIE::AIETargetModel::isMemTile	(	int	col,
		int	row ) const

inline

Return true if the given tile is a Mem tile.

Definition at line 211 of file AIETargetModel.h.

References getTileType().

◆ isMemTilePadValueSupported()

virtual bool xilinx::AIE::AIETargetModel::isMemTilePadValueSupported ( ) const

inlinevirtual

Reimplemented in xilinx::AIE::BaseNPU2TargetModel.

Definition at line 675 of file AIETargetModel.h.

◆ isMemWest()

virtual bool xilinx::AIE::AIETargetModel::isMemWest	(	int	srcCol,
		int	srcRow,
		int	dstCol,
		int	dstRow ) const

pure virtual

Return true if src has a memory tile which is West of dst.

Implemented in xilinx::AIE::AIE1TargetModel, and xilinx::AIE::AIE2TargetModel.

Referenced by getLockLocalBaseIndex(), and getMemLocalBaseAddress().

◆ isNorth()

bool xilinx::AIE::AIETargetModel::isNorth	(	int	srcCol,
		int	srcRow,
		int	dstCol,
		int	dstRow ) const

inline

Return true if src is North of dst.

Definition at line 266 of file AIETargetModel.h.

Referenced by xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE1TargetModel::isMemNorth(), and xilinx::AIE::AIE2TargetModel::isMemNorth().

◆ isShimNOCorPLTile()

bool xilinx::AIE::AIETargetModel::isShimNOCorPLTile	(	int	col,
		int	row ) const

inline

Return true if the given tile is either a ShimNOC or ShimPL tile.

Definition at line 226 of file AIETargetModel.h.

References getTileType().

Referenced by xilinx::AIE::AIE2TargetModel::getLocalLockAddress(), xilinx::AIE::AIE1TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestShimMuxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceShimMuxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceShimMuxConnections(), getSharedMemory(), xilinx::AIE::AIE1TargetModel::getStreamSwitchPortIndex(), xilinx::AIE::Pathfinder::initialize(), xilinx::AIE::AIE1TargetModel::isLegalTileConnection(), and xilinx::AIE::AIE2TargetModel::isLegalTileConnection().

◆ isShimNOCTile()

bool xilinx::AIE::AIETargetModel::isShimNOCTile	(	int	col,
		int	row ) const

inline

Return true if the given tile is a ShimNOC tile.

Definition at line 216 of file AIETargetModel.h.

References getTileType().

◆ isShimPLTile()

bool xilinx::AIE::AIETargetModel::isShimPLTile	(	int	col,
		int	row ) const

inline

Return true if the given tile is a ShimPL tile.

Definition at line 221 of file AIETargetModel.h.

References getTileType().

Referenced by xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), and validate().

◆ isSouth()

bool xilinx::AIE::AIETargetModel::isSouth	(	int	srcCol,
		int	srcRow,
		int	dstCol,
		int	dstRow ) const

inline

Return true if src is South of dst.

Definition at line 271 of file AIETargetModel.h.

Referenced by xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE1TargetModel::isMemSouth(), and xilinx::AIE::AIE2TargetModel::isMemSouth().

◆ isSupportedBlockFormat()

bool xilinx::AIE::AIETargetModel::isSupportedBlockFormat ( std::string const & format ) const

virtual

Reimplemented in xilinx::AIE::BaseNPU2TargetModel.

Definition at line 1743 of file AIETargetModel.cpp.

Referenced by BfpToIntegerConverter::BfpToIntegerConverter().

◆ isValidTile()

virtual bool xilinx::AIE::AIETargetModel::isValidTile ( TileID src ) const

inlinevirtual

Return true if the given tile ID is valid.

Definition at line 232 of file AIETargetModel.h.

References columns(), and rows().

Referenced by xilinx::AIE::getConnectingWireEndpoint(), xilinx::AIE::AIE1TargetModel::getMemEast(), xilinx::AIE::AIE2TargetModel::getMemEast(), xilinx::AIE::AIE1TargetModel::getMemNorth(), xilinx::AIE::AIE2TargetModel::getMemNorth(), xilinx::AIE::AIE1TargetModel::getMemSouth(), xilinx::AIE::AIE2TargetModel::getMemSouth(), xilinx::AIE::AIE1TargetModel::getMemWest(), and xilinx::AIE::AIE2TargetModel::getMemWest().

◆ isWest()

bool xilinx::AIE::AIETargetModel::isWest	(	int	srcCol,
		int	srcRow,
		int	dstCol,
		int	dstRow ) const

inline

Return true if src is West of dst.

Definition at line 256 of file AIETargetModel.h.

Referenced by getLockLocalBaseIndex(), getMemLocalBaseAddress(), xilinx::AIE::AIE1TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE2TargetModel::isLegalMemAffinity(), xilinx::AIE::AIE1TargetModel::isMemWest(), and xilinx::AIE::AIE2TargetModel::isMemWest().

◆ loadRegisterDatabase()

std::unique_ptr< RegisterDatabase > xilinx::AIE::AIETargetModel::loadRegisterDatabase ( ) const

protectedvirtual

Subclasses override to provide architecture-specific database loading.

Returns nullptr if register database is not available for this architecture.

Reimplemented in xilinx::AIE::AIE2TargetModel.

Definition at line 49 of file AIETargetModel.cpp.

Referenced by getRegisterDatabase().

◆ lookupEvent()

std::optional< uint32_t > xilinx::AIE::AIETargetModel::lookupEvent	(	llvm::StringRef	name,
		TileID	tile,
		bool	isMem = false ) const

Lookup event number by name and tile.

Return Event number if found, nullopt otherwise

Definition at line 68 of file AIETargetModel.cpp.

References getRegisterDatabase().

◆ lookupRegister()

const RegisterInfo * xilinx::AIE::AIETargetModel::lookupRegister	(	llvm::StringRef	name,
		TileID	tile,
		bool	isMem = false ) const

Register Database API - provides access to register and event information for trace configuration and low-level register access.

Lookup register information by name and tile. Return pointer to register info, or nullptr if not found

Definition at line 59 of file AIETargetModel.cpp.

References getRegisterDatabase().

Referenced by AIEDMATasksToNPUPass::emitOutOfOrderChannelEnable().

◆ partitionStartColumns()

std::vector< int > xilinx::AIE::AIETargetModel::partitionStartColumns ( int numCols ) const

inline

Every physical column offset at which a numCols-wide partition still fits.

Definition at line 174 of file AIETargetModel.h.

References firstPlaceableColumn(), and physicalColumns().

◆ physicalColumns()

virtual int xilinx::AIE::AIETargetModel::physicalColumns ( ) const

inlinevirtual

Width of the physical array this (possibly virtualized) device is carved from.

This defaults to columns(), which is correct for devices that are the whole array.

Reimplemented in xilinx::AIE::BaseNPU1TargetModel, and xilinx::AIE::BaseNPU2TargetModel.

Definition at line 168 of file AIETargetModel.h.

References columns().

Referenced by partitionStartColumns().

◆ resolvePortValue()

std::optional< uint32_t > xilinx::AIE::AIETargetModel::resolvePortValue	(	llvm::StringRef	value,
		TileID	tile,
		bool	master ) const

Resolve stream switch port specification to port index.

Return Port index for stream switch register, or nullopt if invalid

Definition at line 143 of file AIETargetModel.cpp.

References getStreamSwitchPortIndex().

◆ rows()

virtual int xilinx::AIE::AIETargetModel::rows ( ) const

pure virtual

Return the number of rows in the device.

Implemented in xilinx::AIE::BaseNPU1TargetModel, xilinx::AIE::BaseNPU2TargetModel, xilinx::AIE::VC1902TargetModel, xilinx::AIE::VE2302TargetModel, xilinx::AIE::VE2802TargetModel, and xilinx::AIE::VE3858TargetModel.

Referenced by xilinx::AIE::AIERTControl::AIERTControl(), xilinx::AIE::forEachMemAffinityNeighbor(), xilinx::AIE::AIE1TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumDestSwitchboxConnections(), xilinx::AIE::AIE1TargetModel::getNumSourceSwitchboxConnections(), xilinx::AIE::AIE2TargetModel::getNumSourceSwitchboxConnections(), getRowToShimChanMap(), getTileToControllerIdMap(), xilinx::AIE::Placer::initialize(), isValidTile(), and validate().

◆ validate()

void xilinx::AIE::AIETargetModel::validate ( ) const

Definition at line 1633 of file AIETargetModel.cpp.

References columns(), getNumDestSwitchboxConnections(), getNumMemTileRows(), getNumSourceSwitchboxConnections(), isCoreTile(), isMemTile(), isShimNOCTile(), isShimPLTile(), and rows().

The documentation for this class was generated from the following files:

include/aie/Dialect/AIE/IR/AIETargetModel.h
lib/Dialect/AIE/IR/AIETargetModel.cpp

Public Types

Public Member Functions

Protected Member Functions

Detailed Description

Member Enumeration Documentation

◆ ModelProperty

◆ SharedMemory

◆ TargetModelKind

Constructor & Destructor Documentation

◆ AIETargetModel()

◆ ~AIETargetModel()

Member Function Documentation

◆ addModelProperty()

◆ columns()

◆ encodeFieldValue()

◆ firstPlaceableColumn()

◆ getAccumulatorCascadeSize()

◆ getAddressGenGranularity()

◆ getBdIdRangeForChannel()

◆ getBDMaxDims() [1/2]

◆ getBDMaxDims() [2/2]

◆ getColumnShift()

◆ getComputeTileLoadStoreBusWidth()

◆ getComputeTileMaxVectorAlignBits()

◆ getCoreDataAddressSpaceSize()

◆ getCoreStackAlignment()

◆ getDefaultAxCache()

◆ getDefaultCoreStackSize()

◆ getDmaBdAddress()

◆ getDmaBdAddressOffset()

◆ getDmaBdIterBits() [1/2]

◆ getDmaBdIterBits() [2/2]

◆ getDmaBdLayout() [1/2]

◆ getDmaBdLayout() [2/2]

◆ getDmaBdMaxLen() [1/2]

◆ getDmaBdMaxLen() [2/2]

◆ getDmaBdStepBits() [1/2]

◆ getDmaBdStepBits() [2/2]

◆ getDmaBdWrapBits() [1/2]

◆ getDmaBdWrapBits() [2/2]

◆ getDmaChannelIdleMask()

◆ getDmaControlAddress()

◆ getDmaStatusAddress()

◆ getDmaTaskQueueDepth() [1/2]

◆ getDmaTaskQueueDepth() [2/2]

◆ getDmaTaskQueueSizeMask()

◆ getFieldMask()

◆ getKind()

◆ getLocalDmaControlAddress()

◆ getLocalLockAddress()

◆ getLocalMemorySize()

◆ getLockLocalBaseIndex()

◆ getMaxChannelNumForAdjacentMemTile()

◆ getMaxLockValue()

◆ getMaxOutOfOrderId()

◆ getMaxPacketId()

◆ getMaxRepeatCount()

◆ getMemEast()

◆ getMemEastBaseAddress()

◆ getMemInternalBaseAddress()

◆ getMemLocalBaseAddress()

◆ getMemNorth()

◆ getMemNorthBaseAddress()

◆ getMemSouth()

◆ getMemSouthBaseAddress()

◆ getMemTileLoadStoreBusWidth()

◆ getMemTileSize()

◆ getMemWest()

◆ getMemWestBaseAddress()

◆ getModelProperties()

◆ getNumArbiters()

◆ getNumBanks()

◆ getNumBDs() [1/2]

◆ getNumBDs() [2/2]

◆ getNumBDsForChannel()

◆ getNumControllers()

◆ getNumControllersPerColumn()

◆ getNumDestShimMuxConnections()

◆ getNumDestSwitchboxConnections()

◆ getNumLocks() [1/2]