xilinx::AIE::AIETargetModel Member List

This is the complete list of members for xilinx::AIE::AIETargetModel, including all inherited members.

addModelProperty(uint32_t prop)	xilinx::AIE::AIETargetModel	inline
AIETargetModel(TargetModelKind k)	xilinx::AIE::AIETargetModel	inline
columns() const =0	xilinx::AIE::AIETargetModel	pure virtual
encodeFieldValue(const BitFieldInfo &field, uint32_t value) const	xilinx::AIE::AIETargetModel
firstPlaceableColumn() const	xilinx::AIE::AIETargetModel	inlinevirtual
getAccumulatorCascadeSize() const =0	xilinx::AIE::AIETargetModel	pure virtual
getAddressGenGranularity() const =0	xilinx::AIE::AIETargetModel	pure virtual
getBdIdRangeForChannel(int col, int row, int channel) const	xilinx::AIE::AIETargetModel	inline
getBDMaxDims(AIETileType tileType) const =0	xilinx::AIE::AIETargetModel	pure virtual
getBDMaxDims(int col, int row) const	xilinx::AIE::AIETargetModel	inline
getColumnShift() const =0	xilinx::AIE::AIETargetModel	pure virtual
getComputeTileLoadStoreBusWidth() const =0	xilinx::AIE::AIETargetModel	pure virtual
getComputeTileMaxVectorAlignBits() const	xilinx::AIE::AIETargetModel	inlinevirtual
getCoreDataAddressSpaceSize() const =0	xilinx::AIE::AIETargetModel	pure virtual
getCoreStackAlignment() const	xilinx::AIE::AIETargetModel	inline
getDefaultAxCache() const	xilinx::AIE::AIETargetModel	inlinevirtual
getDefaultCoreStackSize() const	xilinx::AIE::AIETargetModel	inlinevirtual
getDmaBdAddress(int col, int row, uint32_t bd_id, int channel=-1, AIE::DMAChannelDir direction=AIE::DMAChannelDir::MM2S) const =0	xilinx::AIE::AIETargetModel	pure virtual
getDmaBdAddressOffset(int col, int row) const =0	xilinx::AIE::AIETargetModel	pure virtual
getDmaBdIterBits(AIETileType tileType) const =0	xilinx::AIE::AIETargetModel	pure virtual
getDmaBdIterBits(int col, int row) const	xilinx::AIE::AIETargetModel	inline
getDmaBdLayout(AIETileType tileType) const	xilinx::AIE::AIETargetModel	inlinevirtual
getDmaBdLayout(int col, int row) const	xilinx::AIE::AIETargetModel	inline
getDmaBdMaxLen(AIETileType tileType) const =0	xilinx::AIE::AIETargetModel	pure virtual
getDmaBdMaxLen(int col, int row) const	xilinx::AIE::AIETargetModel	inline
getDmaBdStepBits(AIETileType tileType) const =0	xilinx::AIE::AIETargetModel	pure virtual
getDmaBdStepBits(int col, int row) const	xilinx::AIE::AIETargetModel	inline
getDmaBdWrapBits(AIETileType tileType) const =0	xilinx::AIE::AIETargetModel	pure virtual
getDmaBdWrapBits(int col, int row) const	xilinx::AIE::AIETargetModel	inline
getDmaChannelIdleMask() const	xilinx::AIE::AIETargetModel	inlinevirtual
getDmaControlAddress(int col, int row, int channel, AIE::DMAChannelDir direction) const =0	xilinx::AIE::AIETargetModel	pure virtual
getDmaStatusAddress(int, int, int, AIE::DMAChannelDir) const	xilinx::AIE::AIETargetModel	inlinevirtual
getDmaTaskQueueDepth() const =0	xilinx::AIE::AIETargetModel	pure virtual
getDmaTaskQueueDepth(int, int, int, AIE::DMAChannelDir) const	xilinx::AIE::AIETargetModel	inline
getDmaTaskQueueSizeMask() const	xilinx::AIE::AIETargetModel	inlinevirtual
getFieldMask(const BitFieldInfo &field) const	xilinx::AIE::AIETargetModel
getKind() const	xilinx::AIE::AIETargetModel	inline
getLocalDmaControlAddress(int col, int row, int channel, AIE::DMAChannelDir direction) const	xilinx::AIE::AIETargetModel	inline
getLocalLockAddress(uint32_t lockId, TileID tile) const =0	xilinx::AIE::AIETargetModel	pure virtual
getLocalMemorySize() const =0	xilinx::AIE::AIETargetModel	pure virtual
getLockLocalBaseIndex(int localCol, int localRow, int lockCol, int lockRow) const	xilinx::AIE::AIETargetModel
getMaxChannelNumForAdjacentMemTile(int col, int row) const =0	xilinx::AIE::AIETargetModel	pure virtual
getMaxLockValue() const =0	xilinx::AIE::AIETargetModel	pure virtual
getMaxOutOfOrderId() const =0	xilinx::AIE::AIETargetModel	pure virtual
getMaxPacketId() const =0	xilinx::AIE::AIETargetModel	pure virtual
getMaxRepeatCount() const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemEast(TileID src) const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemEastBaseAddress() const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemInternalBaseAddress(TileID src) const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemLocalBaseAddress(int localCol, int localRow, int memCol, int memRow) const	xilinx::AIE::AIETargetModel
getMemNorth(TileID src) const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemNorthBaseAddress() const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemSouth(TileID src) const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemSouthBaseAddress() const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemTileLoadStoreBusWidth() const	xilinx::AIE::AIETargetModel	inlinevirtual
getMemTileSize() const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemWest(TileID src) const =0	xilinx::AIE::AIETargetModel	pure virtual
getMemWestBaseAddress() const =0	xilinx::AIE::AIETargetModel	pure virtual
getModelProperties() const	xilinx::AIE::AIETargetModel	inline
getNumArbiters() const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumBanks(int col, int row) const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumBDs(AIETileType tileType) const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumBDs(int col, int row) const	xilinx::AIE::AIETargetModel	inline
getNumBDsForChannel(int col, int row, int channel) const	xilinx::AIE::AIETargetModel	inline
getNumControllers() const	xilinx::AIE::AIETargetModel	inlinevirtual
getNumControllersPerColumn() const	xilinx::AIE::AIETargetModel	inlinevirtual
getNumDestShimMuxConnections(int col, int row, WireBundle bundle) const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumDestSwitchboxConnections(int col, int row, WireBundle bundle) const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumLocks(AIETileType tileType) const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumLocks(int col, int row) const	xilinx::AIE::AIETargetModel	inline
getNumMemTileRows() const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumMselsPerArbiter() const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumSlaveSlots() const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumSourceShimMuxConnections(int col, int row, WireBundle bundle) const =0	xilinx::AIE::AIETargetModel	pure virtual
getNumSourceSwitchboxConnections(int col, int row, WireBundle bundle) const =0	xilinx::AIE::AIETargetModel	pure virtual
getProgramMemorySize() const =0	xilinx::AIE::AIETargetModel	pure virtual
getRegisterDatabase() const	xilinx::AIE::AIETargetModel	protected
getRowShift() const =0	xilinx::AIE::AIETargetModel	pure virtual
getSharedMemory(TileID a, TileID b) const	xilinx::AIE::AIETargetModel	inline
getShimBurstEncodingsAndLengths() const =0	xilinx::AIE::AIETargetModel	pure virtual
getStreamSwitchPortIndex(int col, int row, WireBundle bundle, uint32_t channel, bool master) const =0	xilinx::AIE::AIETargetModel	pure virtual
getTargetArch() const =0	xilinx::AIE::AIETargetModel	pure virtual
getTileToControllerIdMap(bool columnWiseUniqueIDs=true) const	xilinx::AIE::AIETargetModel
getTileType(int col, int row) const =0	xilinx::AIE::AIETargetModel	pure virtual
hasProperty(ModelProperty Prop) const	xilinx::AIE::AIETargetModel	inline
isBdChannelAccessible(int col, int row, uint32_t bd_id, int channel) const =0	xilinx::AIE::AIETargetModel	pure virtual
isCoreTile(int col, int row) const	xilinx::AIE::AIETargetModel	inline
isEast(int srcCol, int srcRow, int dstCol, int dstRow) const	xilinx::AIE::AIETargetModel	inline
isInternal(int srcCol, int srcRow, int dstCol, int dstRow) const	xilinx::AIE::AIETargetModel	inline
isLegalMemAffinity(int coreCol, int coreRow, int memCol, int memRow) const =0	xilinx::AIE::AIETargetModel	pure virtual
isLegalTileConnection(int col, int row, WireBundle srcBundle, int srcChan, WireBundle dstBundle, int dstChan) const =0	xilinx::AIE::AIETargetModel	pure virtual
isMemEast(int srcCol, int srcRow, int dstCol, int dstRow) const =0	xilinx::AIE::AIETargetModel	pure virtual
isMemNorth(int srcCol, int srcRow, int dstCol, int dstRow) const =0	xilinx::AIE::AIETargetModel	pure virtual
isMemSouth(int srcCol, int srcRow, int dstCol, int dstRow) const =0	xilinx::AIE::AIETargetModel	pure virtual
isMemTile(int col, int row) const	xilinx::AIE::AIETargetModel	inline
isMemTilePadValueSupported() const	xilinx::AIE::AIETargetModel	inlinevirtual
isMemWest(int srcCol, int srcRow, int dstCol, int dstRow) const =0	xilinx::AIE::AIETargetModel	pure virtual
isNorth(int srcCol, int srcRow, int dstCol, int dstRow) const	xilinx::AIE::AIETargetModel	inline
IsNPU enum value	xilinx::AIE::AIETargetModel
isShimNOCorPLTile(int col, int row) const	xilinx::AIE::AIETargetModel	inline
isShimNOCTile(int col, int row) const	xilinx::AIE::AIETargetModel	inline
isShimPLTile(int col, int row) const	xilinx::AIE::AIETargetModel	inline
isSouth(int srcCol, int srcRow, int dstCol, int dstRow) const	xilinx::AIE::AIETargetModel	inline
isSupportedBlockFormat(std::string const &format) const	xilinx::AIE::AIETargetModel	virtual
isValidTile(TileID src) const	xilinx::AIE::AIETargetModel	inlinevirtual
IsVirtualized enum value	xilinx::AIE::AIETargetModel
isWest(int srcCol, int srcRow, int dstCol, int dstRow) const	xilinx::AIE::AIETargetModel	inline
loadRegisterDatabase() const	xilinx::AIE::AIETargetModel	protectedvirtual
lookupEvent(llvm::StringRef name, TileID tile, bool isMem=false) const	xilinx::AIE::AIETargetModel
lookupRegister(llvm::StringRef name, TileID tile, bool isMem=false) const	xilinx::AIE::AIETargetModel
ModelProperty enum name	xilinx::AIE::AIETargetModel
partitionStartColumns(int numCols) const	xilinx::AIE::AIETargetModel	inline
physicalColumns() const	xilinx::AIE::AIETargetModel	inlinevirtual
resolvePortValue(llvm::StringRef value, TileID tile, bool master) const	xilinx::AIE::AIETargetModel
rows() const =0	xilinx::AIE::AIETargetModel	pure virtual
SharedMemory enum name	xilinx::AIE::AIETargetModel
SupportsOutOfOrderDMA enum value	xilinx::AIE::AIETargetModel
TargetModelKind enum name	xilinx::AIE::AIETargetModel
TK_AIE1_Last enum value	xilinx::AIE::AIETargetModel
TK_AIE1_VC1902 enum value	xilinx::AIE::AIETargetModel
TK_AIE2_Last enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU1_1Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU1_2Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU1_3Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU1_4Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU1_Last enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU2 enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU2_1Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU2_2Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU2_3Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU2_4Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU2_5Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU2_6Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU2_7Col enum value	xilinx::AIE::AIETargetModel
TK_AIE2_NPU2_Last enum value	xilinx::AIE::AIETargetModel
TK_AIE2_VE2302 enum value	xilinx::AIE::AIETargetModel
TK_AIE2_VE2802 enum value	xilinx::AIE::AIETargetModel
TK_AIE2PS_Last enum value	xilinx::AIE::AIETargetModel
TK_AIE2PS_VE3858 enum value	xilinx::AIE::AIETargetModel
UsesBDIteration enum value	xilinx::AIE::AIETargetModel
UsesMultiDimensionalBDs enum value	xilinx::AIE::AIETargetModel
UsesSemaphoreLocks enum value	xilinx::AIE::AIETargetModel
validate() const	xilinx::AIE::AIETargetModel
~AIETargetModel()	xilinx::AIE::AIETargetModel	virtual