| addModelProperty(uint32_t prop) | xilinx::AIE::AIETargetModel | inline |
| AIE1TargetModel(TargetModelKind k) | xilinx::AIE::AIE1TargetModel | inline |
| AIETargetModel(TargetModelKind k) | xilinx::AIE::AIETargetModel | inline |
| classof(const AIETargetModel *model) | xilinx::AIE::AIE1TargetModel | inlinestatic |
| columns() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| encodeFieldValue(const BitFieldInfo &field, uint32_t value) const | xilinx::AIE::AIETargetModel | |
| firstPlaceableColumn() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getAccumulatorCascadeSize() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getAddressGenGranularity() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| getBdIdRangeForChannel(int col, int row, int channel) const | xilinx::AIE::AIETargetModel | inline |
| getBDMaxDims(AIETileType tileType) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| xilinx::AIE::AIETargetModel::getBDMaxDims(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| getColumnShift() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getComputeTileLoadStoreBusWidth() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getComputeTileMaxVectorAlignBits() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getCoreDataAddressSpaceSize() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getCoreStackAlignment() const | xilinx::AIE::AIETargetModel | inline |
| getDefaultAxCache() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getDefaultCoreStackSize() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getDmaBdAddress(int col, int row, uint32_t bd_id, int channel, AIE::DMAChannelDir direction) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getDmaBdAddressOffset(int col, int row) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getDmaBdIterBits(AIETileType tileType) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| xilinx::AIE::AIETargetModel::getDmaBdIterBits(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| getDmaBdLayout(AIETileType tileType) const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getDmaBdLayout(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| getDmaBdMaxLen(AIETileType tileType) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| xilinx::AIE::AIETargetModel::getDmaBdMaxLen(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| getDmaBdStepBits(AIETileType tileType) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| xilinx::AIE::AIETargetModel::getDmaBdStepBits(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| getDmaBdWrapBits(AIETileType tileType) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| xilinx::AIE::AIETargetModel::getDmaBdWrapBits(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| getDmaChannelIdleMask() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getDmaControlAddress(int col, int row, int channel, AIE::DMAChannelDir direction) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getDmaStatusAddress(int, int, int, AIE::DMAChannelDir) const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getDmaTaskQueueDepth() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| xilinx::AIE::AIETargetModel::getDmaTaskQueueDepth(int, int, int, AIE::DMAChannelDir) const | xilinx::AIE::AIETargetModel | inline |
| getDmaTaskQueueSizeMask() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getFieldMask(const BitFieldInfo &field) const | xilinx::AIE::AIETargetModel | |
| getKind() const | xilinx::AIE::AIETargetModel | inline |
| getLocalDmaControlAddress(int col, int row, int channel, AIE::DMAChannelDir direction) const | xilinx::AIE::AIETargetModel | inline |
| getLocalLockAddress(uint32_t lockId, TileID tile) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getLocalMemorySize() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getLockLocalBaseIndex(int localCol, int localRow, int lockCol, int lockRow) const | xilinx::AIE::AIETargetModel | |
| getMaxChannelNumForAdjacentMemTile(int col, int row) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMaxLockValue() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMaxOutOfOrderId() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMaxPacketId() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMaxRepeatCount() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMemEast(TileID src) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getMemEastBaseAddress() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMemInternalBaseAddress(TileID src) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMemLocalBaseAddress(int localCol, int localRow, int memCol, int memRow) const | xilinx::AIE::AIETargetModel | |
| getMemNorth(TileID src) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getMemNorthBaseAddress() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMemSouth(TileID src) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getMemSouthBaseAddress() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMemTileLoadStoreBusWidth() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getMemTileSize() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getMemWest(TileID src) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getMemWestBaseAddress() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getModelProperties() const | xilinx::AIE::AIETargetModel | inline |
| getNumArbiters() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getNumBanks(int col, int row) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getNumBDs(AIETileType tileType) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| xilinx::AIE::AIETargetModel::getNumBDs(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| getNumBDsForChannel(int col, int row, int channel) const | xilinx::AIE::AIETargetModel | inline |
| getNumControllers() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getNumControllersPerColumn() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| getNumDestShimMuxConnections(int col, int row, WireBundle bundle) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getNumDestSwitchboxConnections(int col, int row, WireBundle bundle) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getNumLocks(AIETileType tileType) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getNumLocks(int col, int row) const | xilinx::AIE::AIE1TargetModel | inline |
| getNumMemTileRows() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getNumMselsPerArbiter() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getNumSlaveSlots() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getNumSourceShimMuxConnections(int col, int row, WireBundle bundle) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getNumSourceSwitchboxConnections(int col, int row, WireBundle bundle) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getProgramMemorySize() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getRegisterDatabase() const | xilinx::AIE::AIETargetModel | protected |
| getRowShift() const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| getSharedMemory(TileID a, TileID b) const | xilinx::AIE::AIETargetModel | inline |
| getShimBurstEncodingsAndLengths() const override | xilinx::AIE::AIE1TargetModel | virtual |
| getStreamSwitchPortIndex(int col, int row, WireBundle bundle, uint32_t port_num, bool master) const override | xilinx::AIE::AIE1TargetModel | virtual |
| getTargetArch() const override | xilinx::AIE::AIE1TargetModel | virtual |
| getTileToControllerIdMap(bool columnWiseUniqueIDs=true) const | xilinx::AIE::AIETargetModel | |
| getTileType(int col, int row) const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| hasProperty(ModelProperty Prop) const | xilinx::AIE::AIETargetModel | inline |
| isBdChannelAccessible(int col, int row, uint32_t bd_id, int channel) const override | xilinx::AIE::AIE1TargetModel | inlinevirtual |
| isCoreTile(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| isEast(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| isInternal(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| isLegalMemAffinity(int coreCol, int coreRow, int memCol, int memRow) const override | xilinx::AIE::AIE1TargetModel | virtual |
| isLegalTileConnection(int col, int row, WireBundle srcBundle, int srcChan, WireBundle dstBundle, int dstChan) const override | xilinx::AIE::AIE1TargetModel | virtual |
| isMemEast(int srcCol, int srcRow, int dstCol, int dstRow) const override | xilinx::AIE::AIE1TargetModel | virtual |
| isMemNorth(int srcCol, int srcRow, int dstCol, int dstRow) const override | xilinx::AIE::AIE1TargetModel | virtual |
| isMemSouth(int srcCol, int srcRow, int dstCol, int dstRow) const override | xilinx::AIE::AIE1TargetModel | virtual |
| isMemTile(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| isMemTilePadValueSupported() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| isMemWest(int srcCol, int srcRow, int dstCol, int dstRow) const override | xilinx::AIE::AIE1TargetModel | virtual |
| isNorth(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| IsNPU enum value | xilinx::AIE::AIETargetModel | |
| isShimNOCorPLTile(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| isShimNOCTile(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| isShimPLTile(int col, int row) const | xilinx::AIE::AIETargetModel | inline |
| isSouth(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| isSupportedBlockFormat(std::string const &format) const | xilinx::AIE::AIETargetModel | virtual |
| isValidTile(TileID src) const | xilinx::AIE::AIETargetModel | inlinevirtual |
| IsVirtualized enum value | xilinx::AIE::AIETargetModel | |
| isWest(int srcCol, int srcRow, int dstCol, int dstRow) const | xilinx::AIE::AIETargetModel | inline |
| loadRegisterDatabase() const | xilinx::AIE::AIETargetModel | protectedvirtual |
| lookupEvent(llvm::StringRef name, TileID tile, bool isMem=false) const | xilinx::AIE::AIETargetModel | |
| lookupRegister(llvm::StringRef name, TileID tile, bool isMem=false) const | xilinx::AIE::AIETargetModel | |
| ModelProperty enum name | xilinx::AIE::AIETargetModel | |
| partitionStartColumns(int numCols) const | xilinx::AIE::AIETargetModel | inline |
| physicalColumns() const | xilinx::AIE::AIETargetModel | inlinevirtual |
| resolvePortValue(llvm::StringRef value, TileID tile, bool master) const | xilinx::AIE::AIETargetModel | |
| rows() const =0 | xilinx::AIE::AIETargetModel | pure virtual |
| SharedMemory enum name | xilinx::AIE::AIETargetModel | |
| SupportsOutOfOrderDMA enum value | xilinx::AIE::AIETargetModel | |
| TargetModelKind enum name | xilinx::AIE::AIETargetModel | |
| TK_AIE1_Last enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE1_VC1902 enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_Last enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_1Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_2Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_3Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_4Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU1_Last enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2 enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_1Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_2Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_3Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_4Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_5Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_6Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_7Col enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_NPU2_Last enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_VE2302 enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2_VE2802 enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2PS_Last enum value | xilinx::AIE::AIETargetModel | |
| TK_AIE2PS_VE3858 enum value | xilinx::AIE::AIETargetModel | |
| UsesBDIteration enum value | xilinx::AIE::AIETargetModel | |
| UsesMultiDimensionalBDs enum value | xilinx::AIE::AIETargetModel | |
| UsesSemaphoreLocks enum value | xilinx::AIE::AIETargetModel | |
| validate() const | xilinx::AIE::AIETargetModel | |
| ~AIETargetModel() | xilinx::AIE::AIETargetModel | virtual |
1.15.0