Interrupt Issue

General Debug Checklist

  • Check the Interrupt Enable bit in the PCIe Configuration Space.

    • If you are using MSI, the MSI Control register has this Enable bit.

    • If you are using MSI-X, the MSI-X Control register has this Enable bit.

    • If you are using Legacy Interrupt, there is no enable, but check the Interrupt Disable bit in the Command Register within the PCI Configuration Space, and Interrupt Pin and the Interrupt Line register of the PCI Configuration Space. Ensure that cfg_interrupt_int is held until cfg_interrupt_done/fail is received.

      • Certain IP only need this signal asserted for a clock cycle, and some require it to be held steady until the IP responds with a done or fail indicator.

      • Some are also one hot encoded, so check the Product Guide for a given IP.

Documents and Debug Collaterals

Description

URL

Xilinx PCI Express Interrupt Debugging Guide

https://www.xilinx.com/support/answers/58495.html

UltraScale/UltraScale+ PCI Express Integrated Block - Interrupt debug guide

https://www.xilinx.com/support/answers/72702.html