PCIe Debug K-Map

PCIe Debug (General)

• PCIe Collaterals
  • PCIe LFARs (Long Form Answer Records)
  • PCIe Debug Tips and Techniques Blogs
  • PCIe Release Notes
  • PCIe Application Notes
  • PCIe Videos
  • PCIe White Papers
• PCIe Common Issues
  • Enumeration shows no PCIe device (lspci)
  • Missing DMA read data for certain read requests
  • Missing payload in TLP
  • Unsupported Requests/Completion Timeout
  • Receiver Overflow
• PCIe General Debug Techniques
  • First thing to check
  • How to check the LTSSM status?
  • How to check the endpoint was successfully detected and enumerated ?
  • How to enumerate the endpoint when FPGA is configured after enumeration?
  • How to debug link training issues?
  • Generating IP Block Design from the Example Design
• Link Training Issue
  • Common Link Training Issue Reasons
  • General Debug Questions
    • Regression
    • System Configuration
    • Regression
    • Clocking
    • Design Implementation
    • Failing Behavior
    • Debug Capability
    • SI Debug Info
  • General Debug Checklist
  • Documents and Debug Collaterals
  • Useful Links
• Simulation Issue
  • General Debug Checklist
  • Versal ACAP CPM5 Simulation Example Design
  • Documents and Debug Collaterals
  • Useful Links
• Interrupt Issue
  • General Debug Checklist
  • Documents and Debug Collaterals
  • Useful Links

Versal ACAP

• Versal ACAP CPM Mode for PCI Express
  • General Debug Checklist
  • Issues and Debug Tips/Questions
  • Documents and Debug Collaterals
  • Useful Links
  • Versal Adaptive SoC CPM Example Designs
• Versal ACAP Integrated Block for PCI Express
  • General Debug Checklist
  • General FAQs
  • Debug Gotchas
  • Documents and Debug Collaterals
  • Useful Links
  • Specific Issues

UltraScale+

• UltraScale+ Devices Integrated Block for PCIExpress
  • General Debug Checklist
  • General FAQs
  • Debug Gotchas
  • Issues/Debug Tips/Questions
  • Documents and Debug Collaterals
  • Useful Links

XDMA/Bridge Subsystem

• DMA/Bridge Subsystem for PCI Express (XDMA IP/Driver)
  • General Debug Checklist
  • General FAQs
  • XDMA Performance Debug
  • Debug Gotchas
  • Issues/Debug Tips/Questions
  • Documents and Debug Collaterals
  • Useful Links
• DMA/Bridge Subsystem for PCI Express (Bridge IP Endpoint)
  • Debug Gotchas
  • General Debug Checklist
  • Issues/Debug Tips/Questions
  • Documents and Debug Collaterals
  • Useful Links
  • Specific Issues

QDMA

• QDMA Subsystem for PCIExpress (IP/Driver)
  • QDMA Debug Flow
  • Debug Gotchas
  • General FAQs
  • Documents and Debug Collaterals
  • Important Design Considerations from PG302
  • Important Design Considerations from PG344
• QDMA Conceptual Topics
  • Deciphering the PIDX Update Mechanism in a QDMA Subsystem for CPM5
• QDMA Debug Topics
  • General Debug Checklist
  • Debugging QDMA Performance Issues
  • QDMA Driver Debug Resources
  • axis_c2h_status_drop is Asserted
  • Packets being dropped in Simple Bypass Mode
  • CMPT Packet is not sent
  • qdma_hw_error_handler( ): Detected Invalid PIDX update error

Embedded PCI Express

• Documentation & Debugging Resources
  • General Debug Checklist
  • Issues/Debug Tips/Questions
  • Documents and Debug Collaterals
  • Useful Links
• Versal CPM4 PCIe Root Port Design (Linux)
  • Hardware Design Creation
  • Petalinux Image Generation
  • Device Tree Structure
  • ECAM Mapping and Addressing
  • Tactical Patch Requirement
  • System Testability and Setup
  • Supporting Documentation
  • Debugging