General Debug Checklist

• Check the status of top-level interface signals

  • Top-Level Interface Signals

• Check the DMA status ports

  • Channel 0-3 Status Ports

• Review ‘Example H2C Flow’

  • Example H2C Flow

• Review ‘Example C2H Flow’

  • Example C2H Flow

• Review the driver flow

  • Initial Setup For H2C and C2H Transfers

  • DMA H2C Transfer Summary

  • DMA C2H Transfer Summary

• For issues related to AXI-Stream designs, capture the following interfaces in Vivado ILA

  • H2C Channel 0-3 AXI4-Stream Interface Signals

  • C2H Channel 0-3 AXI4-Stream Interface Signals

• For issues related to AXI-Memory Mapped designs, capture the following interfaces in Vivado ILA

  • AXI4 Memory Mapped Read Address Interface Signals

  • AXI4 Memory Mapped Read Interface Signals

  • AXI4 Memory Mapped Write Address Interface Signals

  • AXI4 Memory Mapped Write Interface Signals

  • AXI4 Memory Mapped Write Response Interface Signals

• To track read/write to DMA internal registers, capture the following interfaces in Vivado ILA

  • Config AXI4-Lite Memory Mapped Write Master Interface Signals

  • Config AXI4-Lite Memory Mapped Read Master Interface Signals

  • Config AXI4-Lite Memory Mapped Write Slave Interface Signals

  • Config AXI4-Lite Memory Mapped Read Slave Interface Signals

• For issues related to DMA Bypass, capture the following interface in Vivado ILA

  • AXI4 Memory Mapped Master Bypass Read Address Interface Signals

  • AXI4 Memory Mapped Master Bypass Read Interface Signals

  • AXI4 Memory Mapped Master Bypass Write Address Interface Signals

  • AXI4 Memory Mapped Master Bypass Write Interface Signals

  • AXI4 Memory Mapped Master Bypass Write Response Interface Signals

• For issues related to Descriptor Bypass Port, capture the following interfaces in Vivado ILA

  • H2C 0-3 Descriptor Bypass Port

  • C2H 0-3 Descriptor Bypass Ports

General FAQs

• The channel register space is defined as 0x00 - H2C Channel Identifier 0x04 - H2C Channel Control etc. in PG195. How to find out address of these registers for different channels?

  • Refer to ‘PCIe to DMA Address Format’ table in PG195. For e.g. address for ‘H2C Channel Control’ register in Channel-1 will be: 0x00000104

    • Bit 7:0 - Byte Offset

    • Bit 11:8 - Channel ID[3:0]

    • Bit 15:12 - Submodule within the DMA ( 0 for H2C channel and 1 for C2H Channel)

    • Bit 31:16 - Reserved

• Is XDMA Driver supported on ARM Processor?

  • No, it is not supported.

• What is the difference between xdma0_bypass_h2c_0, xdma0_bypass_c2h_0 and xdma0_bypass?

  • xdma0_bypass_h2c* and xdma0_bypass_c2h_* devices are for internal use only so should be ignored.

• Is it possible to combine different devices such as xdma0_c2h_0, xdma0_c2h_1, xdma0_c2h_2, xdma0_c2h_3 as a single device and select the individual channel through a parameter?

  • No, that is not possible. Each channel has its device and the driver is setup that way to be used.