General Debug Checklist

General FAQs

  • The channel register space is defined as 0x00 - H2C Channel Identifier 0x04 - H2C Channel Control etc. in PG195. How to find out address of these registers for different channels?
    • Refer to ‘PCIe to DMA Address Format’ table in PG195. For e.g. address for ‘H2C Channel Control’ register in Channel-1 will be: 0x00000104
      • Bit 7:0 - Byte Offset

      • Bit 11:8 - Channel ID[3:0]

      • Bit 15:12 - Submodule within the DMA ( 0 for H2C channel and 1 for C2H Channel)

      • Bit 31:16 - Reserved

  • Is XDMA Driver supported on ARM Processor?
    • No, it is not supported.

  • What is the difference between xdma0_bypass_h2c_0, xdma0_bypass_c2h_0 and xdma0_bypass?
    • xdma0_bypass_h2c* and xdma0_bypass_c2h_* devices are for internal use only so should be ignored.

  • Is it possible to combine different devices such as xdma0_c2h_0, xdma0_c2h_1, xdma0_c2h_2, xdma0_c2h_3 as a single device and select the individual channel through a parameter?
    • No, that is not possible. Each channel has its device and the driver is setup that way to be used.