Top-Level Interface Signals

../../_images/top_level_interface_signals.png

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H2C Channel 0-3 AXI4-Stream Interface Signals

C2H Channel 0-3 AXI4-Stream Interface Signals

../../_images/c2h_channel_0_3_axi4_stream_interface_signals.png

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AXI4 Memory Mapped Read Address Interface Signals

../../_images/axi4_memory_mapped_read_address_interface_signals.png

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AXI4 Memory Mapped Read Interface Signals

../../_images/axi4_memory_mapped_read_interface_signals.png

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AXI4 Memory Mapped Write Address Interface Signals

../../_images/axi4_memory_mapped_write_address_interface_signals.png

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AXI4 Memory Mapped Write Interface Signals

../../_images/axi4_memory_mapped_write_interface_signals.png

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AXI4 Memory Mapped Write Response Interface Signals

../../_images/axi4_memory_mapped_write_response_interface_signals.png

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AXI4 Memory Mapped Master Bypass Read Address Interface Signals

../../_images/axi4_memory_mapped_master_bypass_read_address_interface_signals.png

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AXI4 Memory Mapped Master Bypass Read Interface Signals

../../_images/axi4_memory_mapped_master_bypass_read_interface_signals.png

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AXI4 Memory Mapped Master Bypass Write Address Interface Signals

../../_images/axi4_memory_mapped_master_bypass_write_address_interface_signals.png

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AXI4 Memory Mapped Master Bypass Write Interface Signals

../../_images/axi4_memory_mapped_master_bypass_write_interface_signals.png

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AXI4 Memory Mapped Master Bypass Write Response Interface Signals

../../_images/axi4_memory_mapped_master_bypass_write_response_interface_signals.png

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Config AXI4-Lite Memory Mapped Write Master Interface Signals

../../_images/config_axi4_lite_memory_mapped_write_master_interface_signals.png

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Config AXI4-Lite Memory Mapped Read Master Interface Signals

../../_images/config_axi4_lite_memory_mapped_read_master_interface_signals.png

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Config AXI4-Lite Memory Mapped Write Slave Interface Signals

../../_images/config_axi4_lite_memory_mapped_write_slave_interface_signals.png

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Config AXI4-Lite Memory Mapped Read Slave Interface Signals

../../_images/config_axi4_lite_memory_mapped_read_slave_interface_signals.png

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Interrupt Interface

../../_images/interrupt_interface.png

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Channel 0-3 Status Ports

../../_images/channel_0_3_status_ports.png

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Configuration Extend Interface Port Descriptions

../../_images/configuration_extend_interface_port_descriptions.png

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Configuration Management Interface Ports

../../_images/configuration_management_interface_ports.png

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H2C 0-3 Descriptor Bypass Port

../../_images/h2c_0_3_descriptor_bypass_port.png

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C2H 0-3 Descriptor Bypass Ports

../../_images/c2h_0_3_descriptor_bypass_ports.png

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Example H2C Flow

../../_images/example_h2c_flow.png

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Example C2H Flow

../../_images/example_c2h_flow.png

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Initial Setup For H2C and C2H Transfers

../../_images/initial_setup_for_h2c_and_c2h_transfers.png

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DMA H2C Transfer Summary

../../_images/dma_h2c_transfer_summary.png

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DMA C2H Transfer Summary

../../_images/dma_c2h_transfer_summary.png

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