PCIe General Debug Techniques

First thing to check

  • If possible, check whether the issue could be reproduced with the generated example design in Gen1x1 configuration.

  • In the case of a user design, check with Gen1x1 configuration if the IP is configured for a higher speed and lane width.

How to enumerate the endpoint when FPGA is configured after enumeration?

See https://www.xilinx.com/support/answers/37406.html

Generating IP Block Design from the Example Design

The below instructions provide a technique to isolate the Versal PL PCIe IP IPI block design from a full design. In Versal ACAP devices, it introduces the concept of Split IP where the full PL PCIe IP is an integrated IPI block consisting of various components that make up the IP. For more details on the Split IP concept, see the blog in the link below:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/Understanding-the-new-PL-PCIE-IP-Generation-flow-for-Versal-ACAP/ba-p/1215986

If you have a design and wish to extract only the PL PCIe block design, you can follow the steps below.

  1. Create project (e.g. project_1 as project name) and generate QDMA IP from the IP catalog

  2. Configure the QDMA IP as an endpoint

  3. Right click on the IP and generate the example design

  4. In the example design, there will be two block designs generated. Close the block design ending with “_rp”

  5. Export block design with the name ending with “_ep” as .tcl file. To do this, click “File -> Export -> Export Block Design” as shown in the snapshot below.

docs/PCIe_Debug_General_Techniques/images/generating_IPI_block_design.png

  1. The generated .tcl file could be sourced in a new project to create only the QDMA IPI block design.