Versal Adaptive SoC CPM Example Designs

Note

The example design links below are from the Vivado 2023.2 release. Clicking on a link will redirect you to the GitHub repository. Please select the latest Vivado version from the upper-left column to access the most recent version of the example design files.

• 1 - Versal Adaptive SoC CPM5 QDMA Simulation Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma

  • https://adaptivesupport.amd.com/s/article/000036469?language=en_US

• 2 - Versal Adaptive SoC CPM4 QDMA Simulation Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma

  • https://adaptivesupport.amd.com/s/article/000036469?language=en_US

• 3 - Versal Adaptive SoC CPM5 BMD Simulation Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd

  • https://adaptivesupport.amd.com/s/article/Understanding-the-Vivado-CED-Example-Design-Versal-Adaptive-SoC-CPM5-PCIE-BMD-Simulation-Design?language=en_US

• 4 - Versal Adaptive SoC CPM4 BMD Simulation Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd

  • https://adaptivesupport.amd.com/s/article/Understanding-the-Vivado-CED-Example-Design-Versal-Adaptive-SoC-CPM5-PCIE-BMD-Simulation-Design?language=en_US

• 5 - Versal Adaptive SoC CPM - Using PCIe Link for Debug

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug

  • Ref: https://adaptivesupport.amd.com/s/article/1203707?language=en_US

• 6 - Versal Adaptive SoC CPM Tandem PCIe Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe

  • https://adaptivesupport.amd.com/s/article/000034563?language=en_US

• 7 - Versal Adaptive SoC CPM4/CPM5 AXI Bridge Root Complex Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design

• 8 - Versal Adaptive SoC CPM4 QDMA Gen4x8 MM/ST Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma

  • https://adaptivesupport.amd.com/s/article/000033892?language=en_US

• 9 - Versal Adaptive SoC CPM4 QDMA Gen4x8 Performance Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma_perf

  • https://adaptivesupport.amd.com/s/article/Understanding-the-Versal-CPM5-QDMA-Gen4x8-ST-Only-Performance-Design-CED-Example-in-Vivado-2023-2?language=en_US

• 10 - Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen4x8 MM/ST Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_dual_ctrl

• 11 - Versal Adaptive SoC CPM5 QDMA Gen5x8 MM Only Performance Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_g5x8_mm_perf

• 12 - Versal Adaptive SoC CPM5 QDMA Gen4x8 MM/ST Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_mm_st

  • https://adaptivesupport.amd.com/s/article/000034687?language=en_US

• 13 - Versal Adaptive SoC CPM5 QDMA Gen4x8 ST Only Performance Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_st_only

  • https://adaptivesupport.amd.com/s/article/Understanding-the-Versal-CPM5-QDMA-Gen4x8-ST-Only-Performance-Design-CED-Example-in-Vivado-2023-2?language=en_US

• 14 - Versal Adaptive SoC CPM5 PCIE PIO Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio

  • https://support.xilinx.com/s/article/000035901?language=en_US

• 15 - Versal Adaptive SoC CPM4 PCIE PIO Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio

  • https://support.xilinx.com/s/article/000035901?language=en_US

• 16 - Versal Adaptive SoC CPM5 PCIE BMD EndPoint Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep

• 17 - Versal Adaptive SoC CPM4 PCIE BMD EndPoint Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep

• 18 - Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen5x8 Performance Example Design (Part Based)

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_dual_perf

• 19 - Versal Adaptive SoC CPM5 QDMA Gen5x8 ST Performance Example Design (Part Based)

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_st_perf