Versal Adaptive SoC CPM Example Designs

• 1 - Versal Adaptive SoC CPM5 QDMA Simulation Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm5_qdma

• 2 - Versal Adaptive SoC CPM4 QDMA Simulation Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Simulation_Design/cpm4_qdma

• 3 - Versal Adaptive SoC CPM5 BMD Simulation Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm5_bmd

• 4 - Versal Adaptive SoC CPM4 BMD Simulation Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Simulation_Design/cpm4_bmd

• 5 - Versal Adaptive SoC CPM - Using PCIe Link for Debug

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIe_Debug

• 6 - Versal Adaptive SoC CPM Tandem PCIe Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Tandem_PCIe

• 7 - Versal Adaptive SoC CPM4/CPM5 AXI Bridge Root Complex Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_Bridge_RP_Design

• 8 - Versal Adaptive SoC CPM4 QDMA Gen4x8 MM/ST Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma

• 9 - Versal Adaptive SoC CPM4 QDMA Gen4x8 Performance Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm4_qdma_perf

• 10 - Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen4x8 MM/ST Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_dual_ctrl

• 11 - Versal Adaptive SoC CPM5 QDMA Gen5x8 MM Only Performance Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_g5x8_mm_perf

• 12 - Versal Adaptive SoC CPM5 QDMA Gen4x8 MM/ST Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_mm_st

• 13 - Versal Adaptive SoC CPM5 QDMA Gen4x8 ST Only Performance Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design/cpm5_qdma_st_only

• 14 - Versal Adaptive SoC CPM5 PCIE PIO Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm5_pcie_pio

    • https://support.xilinx.com/s/article/000035901?language=en_US

• 15 - Versal Adaptive SoC CPM4 PCIE PIO Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_PIO_EP_Design/cpm4_pcie_pio

    • https://support.xilinx.com/s/article/000035901?language=en_US

• 16 - Versal Adaptive SoC CPM5 PCIE BMD EndPoint Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm5_bmd_ep

• 17 - Versal Adaptive SoC CPM4 PCIE BMD EndPoint Example Design

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_PCIE_BMD_EP_Design/cpm4_bmd_ep

• 18 - Versal Adaptive SoC CPM5 QDMA Dual Ctrl Gen5x8 Performance Example Design (Part Based)

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_dual_perf

• 19 - Versal Adaptive SoC CPM5 QDMA Gen5x8 ST Performance Example Design (Part Based)

  • https://github.com/Xilinx/XilinxCEDStore/tree/2023.2/ced/Xilinx/IPI/Versal_CPM_QDMA_EP_Design_PartBased/cpm5_qdma_g5x8_st_perf