General Debug Checklist

General FAQs

  • The Versal ACAP Integrated Block for PCI Express now comes with BMD example design with the generation of the IP. Is it possible to generate PIO example design instead?
    • Yes, the PIO example design can be generated. To do so, enter the command below at the Vivado Tcl console prompt after theVersal ACAP Integrated Block for PCIe® IP is generated

    • set_property config.bmd_pio_mode false [get_ips pcie_versal_0]

  • Can I use CPM4 pin MIO38 to reset PL PCIe?
    • Yes this is possible. Before opening the example design, set the following Tcl property to sue the reset on MIO38 pin: * set_property CONFIG.insert_cips {true} [get_ips pcie_versal_0]

  • In UltraScale+ and previous devices, direct assignment of GTs are not possible in the user constraints. Does similar limitation still exist with Versal devices?
    • In Versal, the GT locations assignment can be done in the user constraints, while changing GT locations in GT customization IP is not available.

  • The PL PCIE IP Generation flow in Versal ACAP devices is different from previous devices such as UltraScale and UltraScale+. What are the major changes that went into PL based PCIe IP in Versal ACAP devices?