Checklist Template

Table of content

Duplicate this page for each xbtest packages release.

Package information

Fill the following tables:

xbtest information

Release number

<TBC>

Description (what’s new)

<TBC>

Platform Information

Development platform (XSA)

<TBC>

Deployment platform (shell, CMC, SC)

<TBC>

System information

Fill the following table:

System information

OS

<TBC>

Architecture

<TBC>

Server type

<TBC>

AUX cable

<TBC>

Card S/N

<TBC>

XRT version

<TBC>

Measured download time

<TBC>

Requirement - Platform high level features

Refer to Requirement - Platform high level features instruction page to complete this section.

Platform and card requirements

Update the following according to your platform:

Platform and card requirements

FPGA part

<TBC>

PCIe speed and width

<TBC>

DMA type

<TBC>

DDR: speed, size and quantity

<TBC>

HBM: size, quantity and power rail

<TBC>

Host memory support

<TBC>

P2P support

<TBC>

GTs: type, quad, SLR location

<TBC>

Power rails requirements

Remove/add rows according to the actual power rails available in your platform. 3v3_pex, 12v_pex, 12v_aux and vccint rows have been given as example/placeholder, but a generic template is also present for any other type of power rail.

Power rail

Card limit (W)

Note

12v_pex

<TBC>

<TBC>

3v3_pex

<TBC>

<TBC>

12v_aux

<TBC>

<TBC>

vccint

<TBC>

<TBC>

<TBC>

<TBC>

<TBC>

Calibration - Power CU - Results

Refer to Calibration - Power CU instruction page to complete this section.

Remove/add rows according to the actual power rails available in your platform. 3v3_pex, 12v_pex, 12v_aux and vccint rows have been given as example/placeholder, but a generic template is also present for any other type of power rail.

Description

Results

Attach here your xbtest logs (ZIP file)

power_calibration.zip

Power, temperature & toggle rate graph
<TBC>

Maximum toggle rate reached (%)

<TBC>

Power consumption balance achieved:

  • Yes/no and justification (why are some rails not close to their critical current limit?)

<TBC>

3v3_pex current (A)

Measurement

<TBC>

Critical limit

<TBC>

12v_pex current (A)

Measurement

<TBC>

Critical limit

<TBC>

12v_aux current (A)

Measurement

<TBC>

Critical limit

<TBC>

vccint current (A)

Measurement

<TBC>

Critical limit

<TBC>

<TBC> current (A)

Measurement

<TBC>

Critical limit

<TBC>

Calibration - Memory CU power

Refer to Calibration - Memory CU power instruction page to complete this section.

Remove/add tables according to the actual on-board memory available in your platform. DDR and HBM tables have been given as example/placeholder, but a generic template is also present for any other type of memory (e.g. PS_DDR, PL_DDR …).

If there is enough power for a memory, add only the graph and ZIP files to the table.

Memory

Description

simultaneous_wr_rd

only_rd

only_wr

DDR

Is there enough power for memory?

<TBC>

<TBC>

<TBC>

Power rail name

<TBC>

<TBC>

<TBC>

Power throttle limit (W)

<TBC>

<TBC>

<TBC>

20% below power throttle limit (W)

<TBC>

<TBC>

<TBC>

CU rate (%) @ 20% below limit

<TBC>

<TBC>

<TBC>

Power graph
<TBC>
<TBC>
<TBC>

BW graph
<TBC>
<TBC>
<TBC>

Latency graphs
<TBC>
<TBC>
<TBC>
<TBC>

Attach here your xbtest logs (ZIP file)

simultaneous_wr_rd_rate_ramp_ddr.zip

only_rd_rate_ramp_ddr.zip

only_wr_rate_ramp_ddr.zip

Memory

Description

simultaneous_wr_rd

only_rd

only_wr

HBM

Is there enough power for memory?

<TBC>

<TBC>

<TBC>

Power rail name

<TBC>

<TBC>

<TBC>

Power throttle limit (W)

<TBC>

<TBC>

<TBC>

20% below power throttle limit (W)

<TBC>

<TBC>

<TBC>

CU rate (%) @ 20% below limit

<TBC>

<TBC>

<TBC>

Power graph
<TBC>
<TBC>
<TBC>

BW graph
<TBC>
<TBC>
<TBC>

Latency graphs
<TBC>
<TBC>
<TBC>
<TBC>

Attach here your xbtest logs (ZIP file)

simultaneous_wr_rd_rate_ramp_hbm.zip

only_rd_rate_ramp_hbm.zip

only_wr_rate_ramp_hbm.zip

Memory

Description

simultaneous_wr_rd

only_rd

only_wr

<TBC>

Is there enough power for memory?

<TBC>

<TBC>

<TBC>

Power rail name

<TBC>

<TBC>

<TBC>

Power throttle limit (W)

<TBC>

<TBC>

<TBC>

20% below power throttle limit (W)

<TBC>

<TBC>

<TBC>

CU rate (%) @ 20% below limit

<TBC>

<TBC>

<TBC>

Power graph

<TBC>

<TBC>

<TBC>

BW graph

<TBC>

<TBC>

<TBC>

Latency graphs

<TBC>

<TBC>

<TBC>

Attach here your xbtest logs (ZIP file)

<TBC>

<TBC>

<TBC>

Calibration - Memory bandwidth and latency

Refer to Calibration - Memory bandwidth and latency instruction page to complete this section.

Remove/add tables according to the actual on-board memory available in your platform. DDR and HBM tables have been given as example/placeholder, but a generic template is also present for any other type of memory (e.g. PS_DDR, PL_DDR …).

Note

  • N/A: not applicable

  • 1(1,2,3)

    The outstanding write/read is the maximum number of outstanding reads just before the read pipeline is full, giving the best BW and latency results.

Memory

Description

simultaneous_wr_rd

only_rd

only_wr

DDR

QoS / power reduction rate

Write rate = <TBC> %; read rate = <TBC> %

<TBC>

simultaneous_wr_rd_qos_rate_ramp_ddr.zip

Only if used, else N/A

Read rate = <TBC> %

Only if used, else N/A

Write rate = <TBC> %

Only if used, else N/A

Best write BW (MBps)

<TBC>

N/A

<TBC>

Best write latency (ns)

<TBC>

N/A

<TBC>

Best read BW (MBps)

<TBC>

<TBC>

N/A

Best read latency (ns)

<TBC>

<TBC>

N/A

Outstanding write/read 1

Write = <TBC> / read = <TBC>

Due to QoS rate reduction, this may not possible to select value as the BW and latency are +/- constant. In such case do not define any value in platform definition JSON file and set N/A in this table cell.

<TBC>

<TBC>

BW/latency graphs (do one for read and one for write)
<TBC>
<TBC>
<TBC>
<TBC>

Attach here your xbtest logs (ZIP file)

simultaneous_wr_rd_outstanding_ramp_ddr.zip

only_rd_outstanding_ramp_ddr.zip

only_wr_outstanding_ramp_ddr.zip

Memory

Description

simultaneous_wr_rd

only_rd

only_wr

HBM

QoS / power reduction rate

wr_rate <TBC>; rd_rate <TBC>

<TBC>

simultaneous_wr_rd_qos_rate_ramp_hbm.zip

Only if used, else N/A

rd_rate <TBC>

Only if used, else N/A

wr_rate <TBC>

Only if used, else N/A

Best write BW (MBps)

<TBC>

N/A

<TBC>

Best write latency (ns)

<TBC>

N/A

<TBC>

Best read BW (MBps)

<TBC>

<TBC>

N/A

Best read latency (ns)

<TBC>

<TBC>

N/A

Outstanding write/read 1

<TBC>

Due to QoS rate reduction, this may not possible to select value as the BW and latency are +/- constant. In such case do not define any value in platform definition JSON file and set N/A in this table cell.

<TBC>

<TBC>

BW/latency graphs (do one for read and one for write)
<TBC>
<TBC>
<TBC>
<TBC>

Attach here your xbtest logs (ZIP file)

simultaneous_wr_rd_outstanding_ramp_hbm.zip

only_rd_outstanding_ramp_hbm.zip

only_wr_outstanding_ramp_hbm.zip

Memory

Description

simultaneous_wr_rd

only_rd

only_wr

<TBC>

QoS / power reduction rate

wr_rate <TBC>; rd_rate <TBC>

Only if used, else N/A

rd_rate <TBC>

Only if used, else N/A

wr_rate <TBC>

Only if used, else N/A

Best write BW (MBps)

<TBC>

N/A

<TBC>

Best write latency (ns)

<TBC>

N/A

<TBC>

Best read BW (MBps)

<TBC>

<TBC>

N/A

Best read latency (ns)

<TBC>

<TBC>

N/A

Outstanding write/read 1

<TBC>

Due to QoS rate reduction, this may not possible to select value as the BW and latency are +/- constant. In such case do not define any value in platform definition JSON file and set N/A in this table cell.

<TBC>

<TBC>

BW/latency graphs (do one for read and one for write)

<TBC>

<TBC>

<TBC>

Attach here your xbtest logs (ZIP file)

<TBC>

<TBC>

<TBC>

Checklist questionnaire

Refer to Platform definition JSON file instruction page to complete this section.

Runtime

Fill the following table:

Question

Answer / justification / problem tracker reference number

Have you updated the default download time?

  • FYI:

    • u250 xclbin (90Mb) downloads in 3.9 sec (PCIe 3x16).

    • HBM requires calibration which may take time.

<TBC>

Sensors

Fill the following table:

Question

Answer / justification / problem tracker reference number

Do you need to monitor more mechanical sources than the default one (fpga_fan_1)?

<TBC>

Do you need to monitor more thermal sources than the default one (fpga0)?

<TBC>

Do you need to monitor more electrical sources than the default ones (power_consumption, 12v_pex, 12v_aux, 3v3_pex and vccint)?

<TBC>

GT

Fill the following table:

Question

Answer / justification / problem tracker reference number

GT

<TBC>

<TBC>

Have you updated GT default settings to maximize signal integrity?

  • Run all GT pre-canned tests.

<TBC>

<TBC>

Memory

Fill the following table:

Question

Answer / justification / problem tracker reference number

Memory

DDR

HBM

HOST

<TBC>

Have you defined specific DMA bandwidths (dma_bw)?

  • This not applicable for host memory.

<TBC>

<TBC>

N/A

<TBC>

Have you defined optimum DMA settings (buffer_size and total_size) or are default settings enough?

  • Run dma pre-canned test.

<TBC>

<TBC>

N/A

<TBC>

Have you defined specific P2P CARD bandwidths (p2p_card_bw)?

  • This not applicable for host memory.

<TBC>

<TBC>

N/A

<TBC>

Have you defined optimum P2P CARD settings (buffer_size and total_size) or are default settings enough?

  • Run p2p_card pre-canned test.

<TBC>

<TBC>

N/A

<TBC>

Have you defined specific P2P NVME bandwidths (p2p_nvme_bw)?

  • This not applicable for host memory.

<TBC>

<TBC>

N/A

<TBC>

Have you defined optimum P2P NVME settings (buffer_size and total_size) or are default settings enough?

  • Run p2p_nvme pre-canned test.

<TBC>

<TBC>

N/A

<TBC>

Have you reduced the CU rate to avoid over-power (cu_rate)?

<TBC>

<TBC>

<TBC>

<TBC>

Have you defined cu_rate for simultaneous write/read bandwidth QoS?

<TBC>

<TBC>

<TBC>

<TBC>

Have you defined cu_bw?

  • For each test mode: only_wr, only_rd and simul_wr_rd

For host memory these values are depending on the PCIe speed.

<TBC>

<TBC>

<TBC>

<TBC>

Have you defined cu_latency?

  • For each test mode: only_wr, only_rd and simul_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

Have you defined cu_outstanding?

  • For each test mode: only_wr, only_rd and simul_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

Have you defined cu_burst_size?

  • For each test mode: only_wr, only_rd and simul_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

Pre-canned tests

Fill the following table:

Question

Answer / justification / problem tracker reference number

Have you tested all provided pre-canned tests?

  • If not: list the skipped one and the reason?

<TBC>

Have you modified the pre-canned test template?

  • If yes:

    • Why?

    • Was it not possible to make a platform definition update (and thus, available for any test as default)?

    • Update next section with your modifications.

<TBC>

Have you saved all pre-canned results?

  • Update package information section of your checklist.

<TBC>

Issues tracking

Fill the following table:

Question

Answer / justification / problem tracker reference number

Did you modify the platform definition limits and range after running the pre-canned tests?

  • If yes:

    • List the problem tracker reference number

<TBC>

Pre-canned tests results

Refer to Pre-canned tests instruction page to complete this section.

Pre-canned test modifications

Fill the following table:

Test name

Modification from original template

Justifications

<TBC>

<TBC>

<TBC>

dma pre-canned test

Attach here your xbtest logs (ZIP file):

  • dma.zip

Remove/add rows according to the actual on-board memory available in your platform. DDR and HBM rows have been given as example/placeholder, but a generic template is also present for any other type of memory (e.g. PS_DDR, PL_DDR …).

Memory

Write BW (MBps)

Read BW (MBps)

DDR

<TBC>

<TBC>

HBM

<TBC>

<TBC>

<TBC>

<TBC>

<TBC>

p2p_card pre-canned test

Attach here your xbtest logs (ZIP file):

  • p2p_card.zip

Remove/add rows according to the actual on-board memory available in your platform. DDR and HBM rows have been given as example/placeholder, but a generic template is also present for any other type of memory (e.g. PS_DDR, PL_DDR …).

Memory

Write BW (MBps)

Read BW (MBps)

DDR

<TBC>

<TBC>

HBM

<TBC>

<TBC>

<TBC>

<TBC>

<TBC>

p2p_nvme pre-canned test

Attach here your xbtest logs (ZIP file):

  • p2p_nvme.zip

Remove/add rows according to the actual on-board memory available in your platform. DDR and HBM rows have been given as example/placeholder, but a generic template is also present for any other type of memory (e.g. PS_DDR, PL_DDR …).

Memory

Card mode

Write BW (MBps)

Read BW (MBps)

DDR

source

<TBC>

<TBC>

DDR

target

<TBC>

<TBC>

HBM

source

<TBC>

<TBC>

HBM

target

<TBC>

<TBC>

<TBC>

source

<TBC>

<TBC>

<TBC>

target

<TBC>

<TBC>

memory pre-canned test

Attach here your xbtest logs (ZIP file):

  • memory.zip

Remove/add tables according to the actual on-board memory available in your platform. DDR and HBM tables have been given as example/placeholder, but a generic template is also present for any other type of memory (e.g. PS_DDR, PL_DDR …).

Memory

Test mode

Write BW (MBps)

Read BW (MBps)

Write Latency (ns)

Read Latency (ns)

DDR

alternate_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

only_wr

<TBC>

N/A

<TBC>

N/A

only_rd

N/A

<TBC>

N/A

<TBC>

simultaneous_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

Memory

Test mode

Write BW (MBps)

Read BW (MBps)

Write Latency (ns)

Read Latency (ns)

HBM

alternate_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

only_wr

<TBC>

N/A

<TBC>

N/A

only_rd

N/A

<TBC>

N/A

<TBC>

simultaneous_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

Memory

Test mode

Write BW (MBps)

Read BW (MBps)

Write Latency (ns)

Read Latency (ns)

<TBC>

alternate_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

only_wr

<TBC>

N/A

<TBC>

N/A

only_rd

N/A

<TBC>

N/A

<TBC>

simultaneous_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

memory_host pre-canned test

Attach here your xbtest logs (ZIP file):

  • memory_host.zip

Fill the following table:

Memory

Test mode

Write BW (MBps)

Read BW (MBps)

Write Latency (ns)

Read Latency (ns)

HOST

alternate_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>

only_wr

<TBC>

N/A

<TBC>

N/A

only_rd

N/A

<TBC>

N/A

<TBC>

simultaneous_wr_rd

<TBC>

<TBC>

<TBC>

<TBC>