System Performance Analysis

This guide describes the performance analysis toolbox which can be used for early exploration of hardware and software systems. The performance analysis toolbox can be used for early exploration of hardware and software systems. It informs you about the capabilities of the target platform with user configurable settings in a visual way. This guide highlights various features of the performance anslysis toolbox with examples for the Zynq® SoC series, including Zynq® UltraScale+™ MPSoC and Zynq-7000 SoC platforms, as well as how the Vitis software platform can assist you in maximizing the capabilities of these SoC products.After reading this guide, you should be able to:

• Use the System Performance Modeling (SPM) design to analyze a software application and model hardware traffic

• Understand the proficiency of the Zynq UltraScale+ MPSoC and Zynq-7000 SoC platforms.

• Recognize the uses and capabilities of the PS-PL interfaces.

• Leverage the memory hierarchy (including the L1 and L2 data caches and DDR) to achieve the best system performance.

• Model a design using SPM and follow up with performance validation of the actual design.

Specific examples are used to provide detailed results and analysis. This guide also describes how you can obtain similar results in the Vitis software platform. The goals of this guide are such that you can extrapolate these techniques to model and analyze your own designs.

The first four topics provide an overview of the SPA toolbox:

Tutorial	Description
Introduction	Outlines system performance and defines why it is important.
System Performance Modeling Project	Describes the contents of the SPM project.
Monitor Framework	Defines the monitoring infrastructure used by the Vitis software platform tool.
Getting Started with SPM	Provides the necessary steps to get up and running with the SPM design.

The next set of chapters provides in-depth exploration into using the SPM design:

Tutorial	Description
Evaluating Software Performance	Begins by running a software executable that comes with the SPM project.
Evaluating High-Performance Ports	Introduces traffic on the High- Performance (HP) ports while running the same software.
Evaluating DDR Controller Settings	Describes how to change DDR controller (DDRC) settings and analyze their impact on the HP port traffic.
Evaluating Memory Hierarchy and the ACP	Evaluates bandwidth and latency from the memory hierarchy, and then introduces traffic on the Accelerator Coherency Port (ACP) to investigate its impact on that performance.
Using SPA with a Custom Target	Defines some steps and requirements to instrumenting and monitoring your design.
End-To-End Performance Analysis	Describes the full cycle of performance analysis.
Performance Checklist	Summarizes the key performance recommendations mentioned throughout this guide.

Requirements

If you would like to reproduce any of the results shown and discussed in this guide, the requirements include the following:

• Software:

  • Vitis unified software platform

  • Optional: USB-UART drivers from Silicon Labs <http://www.silabs.com/Support%20Documents/Software/CP210x_VCP_Windows.zip>

• Hardware:

  • Xilinx evaluation boards for SPM projects, like ZCU102 <https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html> or ZC702 <https://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm>

  • Any Zynq UltraScale+ MPSoC or Zynq-7000 SoC based boards for Using SPA with a Custom Target.

  • AC power adapter for the evaluation boards

  • Xilinx programming cable; either platform cable or Digilent USB cable

  • UART cable for the evaluation board.