Internal Design of Convert CSC CSR¶
ConvertCSCCSR is an algorithm used to transform CSC format input to CSR format input or CSR format input to CSC format input. The algorithm is quite easy, but due to DDR limits, we cannot get one data per clock, so in our design, we use several caches with depth ajustable to get much better performance.
ConvertCSCCSR algorithm implementation:
for each edge (u, v) in graph // calculate du degree degree(v) += 1 offset2(v) += 1 begin = 0 for node u in graph end = offset1(u) for i in (begin, end) index = indice1(i) index2 = offset2[index] offset2[index] += 1 indice2[index2] = u begin = end
The input matrix should ensure that the following conditions hold:
- No duplicate edges
- compressed sparse column/row (CSC/CSR) format
The algorithm implemention is shown as the figure below:
Figure 1 : convert CSC CSR architecture on FPGA
As we can see from the figure:
- firstly call the Module calculate degree to generate the transfer offset array.
- by using the input offset and indice arrays and also the calculated new offset array, generate the new indice array
The hardware resource utilizations are listed in the following table.
Table 1 : Hardware resources for ConvertCSCCSR with cache
Figure 2 : Cache depth’s influence to ConvertCSCCSR acceleration