AMR RAVE - CIPS Configuration

For common CIPS concepts, see Common CIPS Configuration

This document describes RAVE (VE2302) CIPS configuration without CPM.

Overview

The RAVE CIPS configuration focuses on the Processing System (PS), Platform Management Controller (PMC), and peripheral setup. The VE2302 device does not include a CPM block, so there is no CPM_CONFIG section in the CIPS settings. PCIe functionality is instead provided by PL-based IP blocks.

VE2302 Device Configuration

The VE2302 is a Versal Edge-series device optimized for embedded applications. The CIPS configuration enables the essential processing blocks and peripherals while omitting features not present in Edge-series devices.

CIPS Blocks Configured:

  • RPU (Realtime Processing Unit) for firmware

  • PMC (Platform Management Controller) for boot/config

  • PS peripherals (I2C, SPI, UART, USB, eMMC)

  • NoC connections (RPU to NoC, PMC to NoC)

  • OSPI interface for boot flash

Not Present in VE2302:

  • CPM (Coherent PCIe Module) - Use PL PCIe IP instead

  • HBM - Edge devices do not include HBM

RPU Configuration

The RPU configuration matches the common AMR pattern with two Arm Cortex-R5F processors used for firmware execution. The RPU handles board management, inter-processor communication, flash management, and host communication through the PCIe interface.

RPU NoC Connection:

  • LPD_AXI_NOC_0: 128-bit @ 800MHz

  • Purpose: RPU access to LPDDR4 memory

  • Enable: PS_USE_NOC_LPD_AXI0 = 1

M_AXI_LPD Interface:

  • Status: Disabled in the RAVE base design (PS_USE_M_AXI_LPD = 0)

  • The LPD AXI clock (m_axi_lpd_aclk) is driven by pl0_ref_clk (100 MHz) for internal CIPS requirements, but no M_AXI_LPD port is exposed

PMC Configuration

The PMC manages boot and configuration with OSPI flash interface and NoC connectivity for memory access during initialization.

PMC NoC Connection:

  • PMC_NOC_AXI_0: 128-bit @ 400MHz (SLR0)

  • Purpose: PMC access to LPDDR4 during boot/config

  • Enable: PS_USE_PMC_NOC_AXI0 = 1

FPD CCI NoC Connections:

  • FPD_CCI_NOC_0 through FPD_CCI_NOC_3: 4 cache-coherent interconnect ports

  • Purpose: APU/CCI access to LPDDR4 and PL address space

  • Enable: PS_USE_FPD_CCI_NOC = 1, PS_USE_FPD_CCI_NOC0 = 1

OSPI Configuration:

  • Interface: PMC Bank 500

  • Flash: 128MB OSPI

  • Frequency: 200 MHz

  • Mode: Single (not stacked)

  • Boot Mode: Custom (QSPI/OSPI)

Peripheral Configuration

I2C Interfaces

LPD_I2C0:

  • MIO Pins: PS_MIO 10-11

  • Purpose: Board-ID EEPROM (0x57), sensors, PMICs

  • Enable: PS_I2C0_PERIPHERAL

PMC_I2C / LPD_I2C1:

  • Configuration varies by board

  • Purpose: Additional I2C devices

UART Interfaces

UART0:

  • MIO Pins: PMC_MIO 16-17 or PS_MIO 8-9

  • Purpose: Primary debug console

  • Enable: PS_UART0_PERIPHERAL

UART1:

  • MIO Pins: PMC_MIO 20-21 or PS_MIO 20-21

  • Purpose: Secondary debug/logging

  • Enable: PS_UART1_PERIPHERAL

SPI Interfaces

SPI (TPM):

  • MIO Pins: PMC Bank 501

  • Purpose: TPM 2.0 security module access

  • Enable: PMC SPI configuration

Board-specific Peripherals

Some board variants include additional peripherals:

USB 2.0 Host Controller:

  • Available on select variants

  • Purpose: Front panel USB port

  • Configuration: USB 2.0 host mode via Versal MIO

eMMC Storage:

  • Available on select variants

  • Purpose: On-device persistent storage

  • Configuration: PMC_SD0 in eMMC mode

Note: For variant-specific peripheral availability and MIO pin assignments, refer to the Sapphire RAVE1 EDGE+ and hardware design repository.

PL Reference Clocks

The CIPS generates two PL reference clocks (configured via board automation with pl_clocks {2}):

Clock Frequency Usage
pl0_ref_clk 100 MHz CIPS internal (m_axi_lpd_aclk), NoC aclk7
pl1_ref_clk 200 MHz DFX reconfigurable partition clock

Configuration:

  • PMC_CRP_PL0_REF_CTRL_FREQMHZ: 100

  • PMC_CRP_PL1_REF_CTRL_FREQMHZ: 200

PL Resets

pl0_resetn and pl1_resetn:

  • Count: 2 (configured via board automation with pl_resets {2})

  • pl0_resetn: Main PL reset (not directly used in base design connections)

  • pl1_resetn: Passed to DFX reconfigurable partition as pl_1_resetn

Interrupt Configuration

PL-PS Interrupts

LPD Interrupts:

  • CH0: Enabled (available for firmware use)

  • CH8: Enabled (available for firmware use)

  • Configuration: PS_IRQ_USAGE {{CH0 1} {CH8 1}}

  • Other channels (CH1-CH7, CH9-CH15): Not enabled

Inter-Processor Interrupts (IPI)

IPI Agent Assignment:

  • IPI 0-2: PMC, PSM (default system)

  • IPI 3-4: R5_0 (first R5 core)

  • IPI 5-6: R5_1 (second R5 core)

Enable configuration:

  • PS_GEN_IPI3_ENABLE: 1, PS_GEN_IPI3_MASTER: R5_0

  • PS_GEN_IPI4_ENABLE: 1, PS_GEN_IPI4_MASTER: R5_0

  • PS_GEN_IPI5_ENABLE: 1, PS_GEN_IPI5_MASTER: R5_1

  • PS_GEN_IPI6_ENABLE: 1, PS_GEN_IPI6_MASTER: R5_1

PCIe Reset Configuration

PCIe Reset Pins:

  • PMC_MIO_24: PCIe RST (fundamental reset)

  • PMC_MIO_25: PCIe WAKE_B (wake signal)

These MIO pins connect to the PL PCIe IP for reset and power management signaling.

Configuration:

  • PS_PCIE_RESET: Enable

  • PS_PCIE_EP_RESET1_IO: PMC_MIO_24

  • PMC_MIO_EN_FOR_PL_PCIE: Configuration for PL PCIe routing

MIO Pin Configuration

MIO pins are configured for the following functions:

PMC Bank 500:

  • OSPI flash interface

  • UART0/UART1 (debug consoles)

  • I2C interface

  • PCIe control signals (reset, wake)

  • Status LED

PMC Bank 501:

  • Power control signals

  • I2C1 interface

  • SPI interface (TPM 2.0)

LPD Bank 502:

  • Status LEDs (RPU controlled)

  • I2C0 interface (Board-ID EEPROM at 0x57)

  • ROM control signals

  • Voltage monitors

Note: For complete MIO pin assignments and signal details, refer to the hardware design repository.

Boot Configuration

The VE2302 boots from OSPI flash with the PMC managing the boot sequence:

Boot Mode Settings:

  • BOOT_MODE: Custom

  • Primary Boot: OSPI (PMC Bank 500)

  • Boot Mode Pins: Configured for QSPI/OSPI boot

Boot Sequence:

  1. PMC loads PDI from OSPI flash

  2. PMC initializes LPDDR4 memory controller

  3. PMC loads RPU firmware from PDI

  4. RPU firmware begins execution

  5. RPU initializes peripherals and establishes PCIe communication

Design Mode Settings

The RAVE CIPS uses board automation for initial configuration, then applies selective overrides:

apply_bd_automation -rule xilinx.com:bd_rule:cips -config {
    board_preset {Yes}
    boot_config {Custom}
    configure_noc {Add new AXI NoC}
    debug_config {JTAG}
    design_flow {Full System}
    mc_type {LPDDR}
    num_mc_ddr {None}
    num_mc_lpddr {1}
    pl_clocks {2}
    pl_resets {2}
}

After board automation, the script overrides specific PS_PMC_CONFIG parameters (PL clock frequencies, IRQ usage, FPD/LPD NoC enables, SMON configuration).

PCIe Aperture Configuration

The RAVE design uses PL-based PCIe (pcie_versal IP + XDMA), so PCIe apertures are configured through the NoC and XDMA address masking rather than CIPS CPM apertures.

PL-to-NoC PCIe Address Paths:

  • XDMA M_AXI (S06_AXI): DMA path to LPDDR4 (M00_INI) and PL INI (M04_INI)

  • XDMA M_AXI_LITE (S07_AXI via addr_mask): Remapped 0x0000_0000 → 0x1000_0000 (8 MB) for GCQ shared memory in LPDDR4

  • XDMA M_AXI_BYPASS (S08_AXI via addr_mask): Remapped to LPDDR4 high (0x0800_0000 → 0x0500_0000_0000, 128 MB) and to DFX PL region (0x0 → 0x202_0000_0000, 8 MB)

DFX Partition Aperture:

  • M_PCIE_PL_INI: {0x202_0000_0000 8M} — routes PCIe access to the reconfigurable partition

References