Dataflow compiler for QNN inference on FPGAs

This project is maintained by Xilinx



FINN is a machine learning framework by the Integrated Communications and AI Lab of AMD Research & Advanced Development. It provides an end-to-end flow for the exploration and implementation of quantized neural network inference solutions on FPGAs. FINN generates dataflow architectures as a physical representation of the implemented custom network in space. It is not a generic DNN acceleration solution but relies on co-design and design space exploration for quantization and parallelization tuning so as to optimize a solutions with respect to resource and performance requirements.
The FINN compiler is under active development on GitHub, and we welcome contributions from the community!


Customer Testimonials

“The FINN toolset is showing huge potential using it in upcoming SICK products. It is easy to use and with an extraordinary performance and very promising results. In the future, flexible implementations of ML in our products with FINN can be a great advantage and even replace static architectures as they are currently used. Thanks to the FINN team for the great cooperation.”