Dataflow compiler for QNN inference on FPGAs
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- FINN Examples
- Brevitas
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This project is maintained by Xilinx
Quickstart
Repo links
Depending on what you would like to do, we have different suggestions on where to get started:
- I want to try out prebuilt QNN accelerators on my FPGA board. Head over to finn-examples to try out some FPGA accelerators built with the FINN compiler.
- I want to train new quantized networks for FINN. Check out Brevitas, our PyTorch library for quantization-aware training.
- I want to work with the FPGA building blocks for neural networks directly Check out the HLS and RTL library of FINN.
- I want to understand how it all fits together. Check out the FINN compiler.
Introduction videos & articles
- Video tutorial @FPGA 2021
- FINN paper
- FINN-R paper - this is what the current tool-flow is mostly based on
- Brevitas tutorial @TVMCon2021: Video and Jupyter notebook
More in depth material
- FINN documentation
- Brevitas documentation
- FINN installation instructions
- Full stack tutorial for training an MLP with Brevitas + deploying with FINN
- Tutorial showing detailed compilation steps for a trained fully-connected network
- Building on the pervious tutorial, a tutorial showing detailed verification steps for a trained fully-connected network
- 2-part demonstrator as shown on youtube: Part 1 - Toolflow & Part 2 - Hardware Performance Demo