Dataflow compiler for QNN inference on FPGAs

This project is maintained by Xilinx

What is FINN?


FINN is an experimental framework from Xilinx Research Labs to explore deep neural network inference on FPGAs. It specifically targets quantized neural networks, with emphasis on generating dataflow-style architectures customized for each network. It is not intended to be a generic DNN accelerator like xDNN, but rather a tool for exploring the design space of DNN inference accelerators on FPGAs.


Who are we?

The FINN team consists of members of AMD Research under Ivo Bolsens (CTO) and members of CommsDC Solutions Engineering under Allen Chen (AECG-CommsDCSolnEng), working very closely with the Pynq team and Kristof Denolf and Jack Lo for integration with video processing.

The FINN Team (CTO)

From top left to bottom right: Yaman Umuroglu, Michaela Blott, Alessandro Pappalardo, Lucian Petrica, Nicholas Fraser, Thomas Preusser, Jakoba Petri-Koenig, Ken O’Brien

The FINN Team (CommsDC Solutions Engineering)

From top left to bottom right: Eamonn Dunbar, Kasper Feurer, Aziz Bahri, Fionn O’Donohoe, Mirza Mrahorovic