FINN workshop at FPL'26

13 Oct 2026 - Jakoba Petri-Koenig

We were delighted to host a FINN workshop at this year’s FPL conference in Ghent, Belgium. The workshop was held on September 10th, 2026 as part of the FPL conference program. It brought together developers, users and contributors of FINN, our open-source framework for FPGA-based AI acceleration, for an update on recent developments, community lightning talks, a poster session, a technical deep dive and a roundtable on the future of FINN and FPGA-based AI acceleration.

We had an amazing poster session with contributions from Academia and Industry.

We are excited to present the contributions to the poster session to the wider FINN open-source community in this blog post. You can find the individual works below.

A special thanks goes to our roundtable panelists Felix Jentzsch (Paderborn University), Lukas Stasytis (TU Darmstadt), Tomasz Kryjak (AGH University of Krakow) and Davide Conficconi (Politecnico di Milano) for sharing their perspectives and experiences.

Many thanks to all contributors and participants, you all made this workshop an unforgettable event!

Posters

• FINN+: Project Overview, F. Jentzsch, C. Berganski, L. Jungemann, B. Wintermann, Paderborn University
• LiveFIFO: FPGA-in-the-Loop Buffer Sizing for Dataflow Accelerators, F. Jentzsch, T. B. Preußer, L. Stasytis, Y. Umuroglu, J. Petri-Koenig, C. Berganski, M. Platzner, Paderborn University, TU Darmstadt and AMD
• Accelerating Buffer Sizing for Dataflow Architectures: Control-Path-Driven Black-Box RTL Simulation in FINN, L. Jungemann, B. Wintermann, H. Riebler, F. Jentzsch, C. Berganski, C. Plessl, Paderborn University
• Compiling Multi-DNN Dataflow Accelerators: Dynamic Weight Reconfiguration in FINN, F. Jentzsch, A. Klassen, M. Platzner, Paderborn University
• Multi-Layer Offloading (MLO) on AMD Versal with PYNQ, A. Klassen, AMD
• Multi-Thresholds for Non-Monotonic and Fine-Granular Activations, C. Berganski, F. Jentzsch, M. Platzner, Paderborn University
• ONNX Passes: Graph Transformation Infrastructure based on ONNX Script, C. Berganski, Paderborn University
• PWPolyF: DSP-Based Piecewise-Polynomial Activations for Transformers on FPGAs, O. Cassidy, AMD
• Rosetta + TINA: compiling NumPy signal processing onto AMD FPGAs through FINN, C. Boerkamp, VLV Technology
• Genetic-Algorithm-Based Parallelism Design Space Exploration for Transformer Accelerators in FINN/Brainsmith, Z. Yao, S. A. Fahmy, KAUST
• AccelQ3D: Extending FINN for FPGA acceleration of 3D CNNs, D. Diaconu, M. Leeser, Northeastern University
• PointNet at 2 to 4 Bits with Brevitas and FINN+: Sensitivity-Guided Mixed Precision on a ZU3EG, A. Rasouli, R. Stewart, Heriot-Watt University
• FINN4YOLO: Unlocking Real-Time Fisheye Vision with FINN-Accelerated YOLO on FPGA, Q. A. Ahmed, S. Karki, T. Jungeblut, Bielefeld University of Applied Sciences and Arts
• FINN for Real-Time Embedded Perception, M. Daniłowicz, B. Bańka, K. Lis, M. Wąsala, T. Kryjak, AGH University of Krakow
• A Methodology to Optimize Hardware Resources for Distributed Neural Network Inference on FPGAs, M. Hannoun, S. Zuckerman, O. Romain, CY Cergy Paris Université and Madicob

Organization

• Jakoba Petri-Koenig and Thomas Preusser, AMD