Dataflow compiler for QNN inference on FPGAs
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This project is maintained by Xilinx
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External Collaborators
- Paderborn University, Germany: Felix Paul Jentzsch, Marco Platzner
- TU Munich and BMW Group, Germany: Nael Fasfous, Manoj-Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Walter Stechele
- TU Delft, Netherlands: Zaid Al-Ars
- Heidelberg University, Germany: Hendrik Borras, Holger Froening
- NTNU, Norway: Magnus Jahre, Magnus Sjalander
- University of Sydney, Australia: Julian Faraone, Philip Leong
- ETH Zurich, Switzerland: Kaan Kara, Ce Zhang, Lois Orosa, Onur Mutlu
- University of Kaiserslautern, Germany: Vladimir Rybalkin, Mohsin Ghaffar, Nobert Wehn
- Imperial College, UK: Alex (Jiang) Su and Peter Cheung
- Northeastern University, USA: Miriam Leeser
- Trinity College Dublin, Ireland: Linda Doyle
- Missing Link Electronics, Germany