Publications

• IEEE Micro’22: Special Issue on Artificial Intelligence at the Edge: RadioML meets FINN: Enabling Future RF Applications with FPGA Streaming Architectures
• IEEE TECS’22: On the RTL Implementation of FINN Matrix Vector Unit
• ACM TRETS: Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning
• FPGA’21: S2N2: A Streaming Accelerator for Streaming Spiking Neural Networks and repository on GitHub
• FPT’20: Memory-Efficient Dataflow Inference for Deep CNNs on FPGA
• IEEE ToC: Evaluation of Optimized CNNs on Heterogeneous Accelerators using a Novel Benchmarking Approach
• FPL’20: LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications
• FCCM’20: High-Throughput DNN Inference with LogicNets
• GECCO’20: Evolutionary Bin Packing for Memory-Efficient Dataflow Inference Acceleration on FPGA
• FPGA’20: Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach
• ACM JETC: QuTiBench: Benchmarking neural networks on heterogeneous hardware
• ACM TRETS: Optimizing bit-serial matrix multiplication for reconfigurable computing
• FPL’18: FINN-L:Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs
• FPL’18: BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
• FPL’18: Customizing Low-Precision Deep Neural Networks For FPGAs
• ACM TRETS, Special Issue on Deep Learning: FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
• ARC’18: Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic
• CVPR’18: SYQ: Learning Symmetric Quantization For Efficient Deep Neural Networks
• DATE’18: Inference of quantized neural networks on heterogeneous all-programmable devices
• ICONIP’17: Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks
• ICCD’17: Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic
• PARMA-DITAM’17: Scaling Binarized Neural Networks on Reconfigurable Logic
• FPGA’17: FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
• H2RC’16: A C++ Library for Rapid Exploration of Binary Neural Networks on Reconfigurable Logic

External Publications and Projects Based on FINN

If you are using FINN in your work and would like to be listed here, please contact us! (jakoba.petri-koenig@amd.com)

• Towards Real-Time Deep Learning-Based Network Intrusion Detection on FPGA (KU Leuven)<\a>
• SAMO: Optimised Mapping of Convolutional Neural Networks to Streaming Architectures (Imperial College London)
• Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs (Scoula Superiore Sant’Anna)
• Hardware-Software Co-Design Real-time AI (UNC Charlotte)
• BinaryEye: A 20 kfps Streaming Camera System on FPGA with Real-Time On-Device Image Recognition Using Binary Neural Networks
• Cucumber sorting with FINN (in Japanese)
• ReBNet: Residual Binarized Neural Network, FCCM’18 best paper