Kria™ KV260 Vision AI Starter Kit Tutorial
Using Vivado to Build the Hardware Design
Build Vivado Design¶
This tutorial shows how to build the hardware design for applications running on KV260 Vision AI Starter Kit.
Vivado Design Suite of the appropiate version
Accessing the Tutorial Reference Files¶
Note: Skip the following steps if the design files have already been cloned and extracted to a working repository
To access the reference files, type the following into a terminal:
git clone --branch xlnx_rel_v2022.1 --recursive https://github.com/Xilinx/kria-vitis-platforms.git
Navigate to the
kria-vitis-platforms/kv260which is the working directory.
Generating an Extensible XSA¶
Go to the platform directory specific to the application
Applications and their corresponding platform names are listed in the table below
To build the XSA, Source Vivado and run the following command. The Makefile uses scripts/main.tcl file to create a Vivado project, populate the block design and finally build a XSA. The XSA generation may take couple of hours depending on the system specification
The generated XSA will be located at:
Note: The steps under Modifying the Vivado design and creating a new XSA are optinal and are required only if you need to change the platform design.
Modifying the Vivado design and creating a new XSA¶
Go to the directory specific to the platform design
To open the Vivado project, first open the Vivado GUI, then run the following command from the Vivado tcl console:
In the Flow Navigator pane on the left-hand side under IP integrator, click on Open Block Design. An IP integrator block design becomes visible that contains the Processing System (PS) IP and other PL IPs.
To view the Platform interfaces that are enabled for the Vitis compiler to stitch in accelerators, on the tool bar at the top click on Window > Platform Setup. Platform interfaces that are enabled are
Clocks: To drive clock inputs on the accelerator.
Master AXI: AXI memory-mapped master ports on the Interconnect IP to drive the accelerator’s control port.
Slave AXI: AXI memory-mapped slave ports driven by the accelerator’s read/write data ports.
Interrupts: pl_ps_irq0[7:0] for the accelerator to drive interrupt signals. (Not seen on the Platform setup)
You can now modify the block design and validate it (tool bar at the top: Tools → Validate design). Then, click on Run Synthesis to complete synthesis
To write out a new extensible platform XSA file, run the following command from the Vivado tcl console:
write_hw_platform -force -file <platform_name>.xsa
The generated XSA or the modified XSA file can now be used to create a Vitis Platform
For more information on how to setup Platform Interfaces refer to Xilinx Vitis Unified Software Platform Documentation UG1393
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