‘aie’ Dialect

This is a dialect for describing netlists of AIE components in a Versal device. It focuses on representing logical stream connections between cores and DMAs, along with the implementation of those logical connections in the various switch components. In the dialect, a switch is referred to as switchbox to avoid confusion with the switch keyword in C/C++.

[TOC]

Operations

aie.amsel (::xilinx::AIE::AMSelOp)

Declare an arbiter of a switchbox with a master select value (arbiter + msel)

Syntax:

operation ::= `aie.amsel` `<` $arbiterID `>` `(` $msel `)` attr-dict

A combination of arbiter ID and master select (msel) value. This op is used as a pointer to select the arbiter for routing a packet-switched flow

Example:

    %a0_0 = aie.amsel<5>(3)
    %m1 = aie.masterset("East" : 0, %a0_0 )
    aie.packet_rules("South" : 0) {
      aie.rule(0x1F, 0x10, %a0_0)
    }

This code associates arbiter 5 with msel=3. A packet-switched connection is made routing traffic from the South:0 port to the East:0 port using this arbiter. There are 6 arbiters per switchbox and 4 possible master select values. See also MasterSetOp, PacketRulesOp, and PacketRuleOp for more information.

Traits: HasParent<SwitchboxOp>

Interfaces: InferTypeOpInterface

Attributes:

Attribute	MLIR Type	Description
arbiterID	::mlir::IntegerAttr	8-bit signless integer attribute whose minimum value is 0 whose maximum value is 5
msel	::mlir::IntegerAttr	8-bit signless integer attribute whose minimum value is 0 whose maximum value is 3

Results:

Result	Description
«unnamed»	index

aie.bd_chain (::xilinx::AIE::BDChainOp)

Definition of a Parametrizable Chain of Buffer Descriptors

This operation allows you to define buffer descriptor chains with parametrizable inputs. This is useful for common patterns such as double buffering (ping-pong) that may look identical but use different input/output buffers and locks. Currently, only buffers and locks are parametrizable.

Once defined, an abstract BD chain can be used elsewhere using AIEX ops in the runtime sequence. In the future, abstract BD chains will also be usable elsewhere, inside the static configuration. At its usage sites, the abstract BD chain will be concretized with the given input arguments.

Traits: SkipAccessibilityCheckTrait

Interfaces: Symbol

Attributes:

Attribute	MLIR Type	Description
sym_name	::mlir::StringAttr	string attribute

aie.buffer (::xilinx::AIE::BufferOp)

Declare a buffer

Syntax:

operation ::= `aie.buffer` `(` $tile `)`
              attr-dict `:` type($buffer)
              custom<BufferInitialValue>(ref(type($buffer)), $initial_value)

This operation instantiates a buffer that belongs to a Memory Module of a tile.

Example:

  %tile33 = aie.tile(3, 3)
  %buf = aie.buffer(%tile33) : memref<256xi64>

This operation represents a buffer in tile (3, 3) of 256 elements, each a 64-bit integer.

Interfaces: OpAsmOpInterface, TileElement

Attributes:

Attribute	MLIR Type	Description
sym_name	::mlir::StringAttr	string attribute
address	::mlir::IntegerAttr	32-bit signless integer attribute
initial_value	::mlir::ElementsAttr	constant vector/tensor attribute
mem_bank	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
tile	index

Results:

Result	Description
buffer	memref of any type values

aie.cascade_flow (::xilinx::AIE::CascadeFlowOp)

A cascade connection between tiles

Syntax:

operation ::= `aie.cascade_flow` `(` $source_tile `,` $dest_tile `)` attr-dict

The aie.cascade_flow operation represents a cascade connection between two aie.tile operations. During lowering, this is replaced by aie.configure_cascade operations for each aie.tile based on their relative placement to one another.

Example:

  %tile03 = aie.tile(0, 3)
  %tile13 = aie.tile(1, 3)
  aie.cascade_flow(%tile03, %tile13)

Operands:

Operand	Description
source_tile	index
dest_tile	index

aie.configure_cascade (::xilinx::AIE::ConfigureCascadeOp)

An op to configure the input and output directions of the cascade for a single AIE tile

Syntax:

operation ::= `aie.configure_cascade` `(` $tile `,` $inputDir `,` $outputDir `)` attr-dict

An operation to configure the cascade on a single tile in both the input and the output directions.

Example:

  %tile00 = aie.tile(1, 3)
  aie.configure_cascade(%tile00, West, East)

Configures the input cascade port of %tile00 to the West direction, and the output port to the East direction.

Traits: HasParent<DeviceOp>

Attributes:

Attribute	MLIR Type	Description
inputDir	xilinx::AIE::CascadeDirAttr	Directions for cascade
outputDir	xilinx::AIE::CascadeDirAttr	Directions for cascade

Operands:

Operand	Description
tile	index

aie.connect (::xilinx::AIE::ConnectOp)

A circuit-switched connection inside a switchbox

Syntax:

operation ::= `aie.connect` `<` $source_bundle `:` $source_channel `,` $dest_bundle `:` $dest_channel `>` attr-dict

This operation represents a programmed circuit-switched connection in a stream switch. It associates a source bundle and source channel with a destination bundle and a destination channel. This operation must exist within an aie.switchbox or aie.shim_switchbox operation. All of the aie.connect operations in a switchbox must have different destinations. All of the aie.connect operations must also have a destination which is different from all of the aie.masterset operations in the same switchbox.

Example:

%tile = aie.tile(1, 1)
aie.switchbox(%tile) {
  aie.connect<"West" : 0, "Core" : 1>
}

Traits: HasParent<SwitchboxOp, ShimMuxOp>

Attributes:

Attribute	MLIR Type	Description
source_bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
source_channel	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0
dest_bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
dest_channel	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0

aie.core (::xilinx::AIE::CoreOp)

Declare a core module

Syntax:

operation ::= `aie.core` `(` $tile `)` regions attr-dict

This operation represents an AIEngine processor core belonging to a tile. The region of a CoreOp contains code that gets run on the AIE core. This code will typically be outlined into the LLVM dialect, eventually resulting in a binary file for each core. The name of this file can be be specified using the elf_file attribute.

If the elf_file attribute is present, no MLIR besides a terminator may be present in the core; in that case, the binary file linked dictates what will run in the core. The path specified should is relative to the MLIR file.

This op has an optional stackSize attribute, to control the amount of memory (in bytes) reserved for the stack. The default value is 1024. The stack (and other data allocations) are always stored in the local core memory, to avoid conflicts with static data allocations in other cores.

This op has an optional dynamic_objfifo_lowering attribute, to finely control whether the objectfifos in this core should be lowered using the dynamic runtime lowering.

Examples:

%tile = aie.tile(1, 1)
%lock11_8 = aie.lock(%tile, 8)
aie.core(%tile) {
  aie.use_lock(%lock11_8, "Acquire", 1)
  aie.use_lock(%lock11_8, "Release", 0)
  aie.end
}

%tile = aie.tile(3, 3)
aie.core(%tile) {
  aie.end
} { stackSize = 2048 : i32, elf_file = "core_33.elf" }

Interfaces: FlowEndPoint, InferTypeOpInterface, OpAsmOpInterface, TileElement

Attributes:

Attribute	MLIR Type	Description
stack_size	::mlir::IntegerAttr	32-bit signless integer attribute
link_with	::mlir::StringAttr	string attribute
elf_file	::mlir::StringAttr	string attribute
dynamic_objfifo_lowering	::mlir::BoolAttr	bool attribute

Operands:

Operand	Description
tile	index

Results:

Result	Description
«unnamed»	index

aie.debug (::xilinx::AIE::DebugOp)

Capture a value for debugging

Syntax:

operation ::= `aie.debug` `(` $arg `:` type($arg) `)` attr-dict

Output the given value for debugging. This is primarily used for simulation.

Operands:

Operand	Description
arg	any type

aie.device (::xilinx::AIE::DeviceOp)

Define an AIE design targetting a complete device

Syntax:

operation ::= `aie.device` `(` $device `)` ($sym_name^)? regions attr-dict

This operation describes a design that executes on a particular AIEngine device. It exists at the toplevel of a design; although currently it does not replace the default toplevel module in MLIR, the intention is that this could be the case in the future.

When using this operation, all resources in a physical device are available and the design does not need to be concerned with other potential users of a physical device. In addition, within an aie.device operation, tile addresses are absolute coordinates and are not intended to describe a relocatable design. To describe a portion of a device which may be relocatable, the intention would be to provide another operation, for instance maybe aie.segment. The design itself is described using a region of code contained by the device operation.

Example:

aie.device(xcvc1902) {
  %tile = aie.tile(1, 1)
  %CORE = aie.core(%tile) { ... }
}

Traits: HasDefaultDLTIDataLayout, HasParent<mlir::ModuleOp>, IsolatedFromAbove, SingleBlockImplicitTerminator<EndOp>, SingleBlock, SymbolTable

Interfaces: AIETarget, DataLayoutOpInterface, Symbol

Attributes:

Attribute	MLIR Type	Description
device	xilinx::AIE::AIEDeviceAttr	AIE Device
sym_name	::mlir::StringAttr	string attribute

aie.dma (::xilinx::AIE::DMAOp)

An op to describe a set of DMA operations.

Syntax:

operation ::= `aie.dma` `(` $channel_dir `,` $channel_index `)`
              attr-dict ` `
              `[`regions`]`

Traits: HasParent<MemOp, MemTileDMAOp, ShimDMAOp>, NoTerminator

Interfaces: InferTypeOpInterface, OpAsmOpInterface

Attributes:

Attribute	MLIR Type	Description
channel_dir	xilinx::AIE::DMAChannelDirAttr	DMA Channel direction
channel_index	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0
loop	::mlir::BoolAttr	bool attribute
repeat_count	::mlir::IntegerAttr	32-bit signless integer attribute
sym_name	::mlir::StringAttr	string attribute

Results:

Result	Description
valid	1-bit signless integer

aie.dma_bd (::xilinx::AIE::DMABDOp)

Declare a dma buffer descriptor op

This operation describes a buffer descriptor for DMA operations. In particular, it specifies what buffer to use, and optionally:

1. the offset into the buffer;
2. the transfer length;
3. the sizes and strides for n-d tensor addressing (described below);
4. the "bd_id" with which to associate the buffer descriptor (most often left empty);
5. the number of zeros to pad before and after every dimension of an n-d tensor (described below);
6. the burst length to use for the DMA operation. This option is only available for data movement between the host memory and Shim NOC tiles.
  The default value of 0 is interpreted as the maximum available burst length in the architecture.

offset, len, sizes and strides are all denominated in element width; e.g., transferring the whole of memref<512xi32> means len == 512, and also while transferring the whole of memref<512xi16>, len == 512.

The only caveat to this “everything-is-in-terms-of-element-width” rule is regarding the inner-most dimension’s stride (see Important gotcha regarding strides below).

dma_bd ops must appear in their own BBs (basic blocks) and such BBs can (optionally) include use_lock operations (specifying an “acquire” and a “release” lock; see the use_lock operation) and subsequent BDs in a “chain” of BDs (using next_bd as a “jump” to the next BB which contains a dma_bd).

Example:

  // this defines a BD that uses lock %lck0 and buffer %buf0
  ^bd5:
    aie.use_lock(%lck, "Acquire", 0)
    // transfer the first 32 elements of the memref
    aie.dma_bd(<$buf0 : memref<128xi32>, 0, 32)
    aie.use_lock(%lck, "Release", 1)
    aie.next_bd ^bd6 // point to the next bb, which describes the next buffer descriptor
  ^bd6:
    aie.use_lock(%lck, "Acquire", 1)
    // transfer the last 32 elements of the memref
    aie.dma_bd(<$buf1 : memref<128xi32>, 96, 32)
    aie.use_lock(%lck, "Release", 0)
    aie.next_bd ^end

  ...

  // this defines a BD that does not use any lock
  ^bd8:
    aie.dma_bd(<$buf2 : memref<64xi32>, 0, 64)

Background/context

A DMA channel in a Memory Module can process one buffer descriptor after another by chaining them. There are 16 buffer descriptors per Core memory module and 48 buffer descriptors per Memtile memory module. They are shared by four DMA channels (or 12).

DMA Data Layout Transformations on AIE-ML Devices

AIE-ML devices can apply data layout transformations at the buffer descriptor level. These transformation are described by strides and sizes in up to three dimensions (four dimensions on memtiles). Strides and sizes can be supplied to the dma_bd through an optional argument, an array of “tuple-like” attributes bd_dim_layout<size, stride>.

The first element of this array gives the outer-most dimension’s stride and size, the last element of the array gives the inner-most dimension’s stride and size. We can model the access pattern strides and sizes generate by a series of nested loops. In general, a set of strides and sizes like this…

[<size_2, stride_2>, <size_1, stride_1>, <size_0, stride_0>]

…translates to an access pattern that can be expressed like this:

int *buffer;  // i32
for(int i = 0; i < size_2; i++)
  for(int j = 0; j < size_1; j++)
    for(int k = 0; k < size_0; k++)
      // access/store element at/to buffer[  i * stride_2
      //                                   + j * stride_1
      //                                   + k * stride_0]

The following example shows an access pattern that corresponds to alternating between even and odd elements of the buffer/stream every 8 elements:

aie.dma_bd(%buf : memref<128xi32>, 0, 128, [<8, 16>, <2, 1>, <8, 2>])

implies

for(int i = 0; i < 8 /*size_2*/; i++)
  for(int j = 0; j < 2 /*size_1*/; j++)
    for(int k = 0; k < 8 /*size_0*/; k++)
      // access/store element at/to index (i * 16 /*stride_2*/ + j * 1 /*stride_1*/ + k * 2 /*stride_0*/)

Important gotcha regarding strides

All strides are expressed in multiples of the element width (just like len and offset) with the caveat that the inner-most dimension’s stride must be 1.

DMA constant padding on AIE-ML Devices

AIE-ML devices can apply constant padding at the buffer descriptor level, described with pairs of padding counts before and after a dimension, to all dimensions in the data layout transformations. The padding counts can be supplied to the dma_bd through an optional argument, an array of “tuple-like” attributes bd_pad_layout<const_pad_before, const_pad_after>, followed by an optional argument const_val (default is 0). All counts are expressed in multiples of the element width.

Attributes:

Attribute	MLIR Type	Description
offset	::mlir::IntegerAttr	32-bit signless integer attribute
len	::mlir::IntegerAttr	32-bit signless integer attribute
dimensions	::xilinx::AIE::BDDimLayoutArrayAttr
pad_dimensions	::xilinx::AIE::BDPadLayoutArrayAttr
pad_value	::mlir::IntegerAttr	32-bit signless integer attribute
bd_id	::mlir::IntegerAttr	32-bit signless integer attribute
packet	::xilinx::AIE::PacketInfoAttr	Tuple encoding the type and header of a packet;
burst_length	::mlir::IntegerAttr	32-bit signless integer attribute
next_bd_id	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
buffer	ranked or unranked memref of any type values

aie.dma_bd_packet (::xilinx::AIE::DMABDPACKETOp)

Enable packet headers for a dma block descriptor

Syntax:

operation ::= `aie.dma_bd_packet` `(` $packet_type `,` $packet_id `)` attr-dict

This operation enables packet headers for a block descriptor for DMA operations. In particular, it specifies the packet type (3-bits) and packet ID (5-bits).

This operation must be used in an MLIR block that lives inside a MemOp’s region, and before aie.dma_bd. The block descriptor specifies what lock to use and the buffer configuration.

Example:

  // this defines a BD that uses lock %lck0 and buffer %buf0
  ^bd5:
    aie.use_lock(%lck, "Acquire", 0)
    aie.dma_bd_packet(0x4, 0xD)
    aie.dma_bd(<$buf0 : memref<512xi32>, 0, 512>, 1)
    aie.use_lock(%lck, "Release", 1)
    br ^bd6 // point to the next Block, which is also a different Block Descriptor

Attributes:

Attribute	MLIR Type	Description
packet_type	::mlir::IntegerAttr	32-bit signless integer attribute
packet_id	::mlir::IntegerAttr	32-bit signless integer attribute

aie.dma_start (::xilinx::AIE::DMAStartOp)

An op to start DMA

Syntax:

operation ::= `aie.dma_start` `(` $channel_dir `,` $channel_index `,` $dest `,` $chain (`,` `repeat_count` `=` $repeat_count^)? `)` attr-dict

This operation declares a DMA channel to be used for data transfer. It usually exists inside either a MemOp (representing a TileDMA), a MemTileDMAOp (representing a DMA in a MemTile), or in a ShimDMAOp (representing a ShimDMA). A channel is defined by a direction (i.e., MM2S or S2MM) and an index.

Example:

    aie.dma_start("MM2S", 0, ^bd0, ^end)
  ^bd0:
    aie.use_lock(%lock0, "Acquire", 0)
    aie.dma_bd(%buffer : memref<16 x f32>, 0, 16)
    aie.use_lock(%lock0, "Release", 1)
    br ^bd0
  ^end:
    aie.end

Conceptually, the aie.dma_start operation is a terminator that either passes control to a basic block containing DMA operations (through its first successor) or to a basic block for another dma_start, to an aie.end operation.

Traits: HasParent<MemOp, MemTileDMAOp, mlir::func::FuncOp, ShimDMAOp>, Terminator

Interfaces: InferTypeOpInterface

Attributes:

Attribute	MLIR Type	Description
channel_dir	xilinx::AIE::DMAChannelDirAttr	DMA Channel direction
channel_index	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0
repeat_count	::mlir::IntegerAttr	32-bit signless integer attribute

Results:

Result	Description
valid	1-bit signless integer

Successors:

Successor	Description
dest	any successor
chain	any successor

aie.end (::xilinx::AIE::EndOp)

End op

Syntax:

operation ::= `aie.end` attr-dict

A generic terminator operation for AIE ops’ regions.

Traits: Terminator

aie.event (::xilinx::AIE::EventOp)

Event instruction

Syntax:

operation ::= `aie.event` `(` $val `)` attr-dict

Event instruction.

Attributes:

Attribute	MLIR Type	Description
val	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0 whose maximum value is 1

aie.external_buffer (::xilinx::AIE::ExternalBufferOp)

Declare a buffer in external memory

Syntax:

operation ::= `aie.external_buffer` attr-dict `:` type($buffer)

This operation represents a buffer that exists in some physical location in a device, most likely external memory. The exact address of the external buffer is passed by the mlir_aie_external_set_addr() and mlir_aie_external_set_addr_myBuffer_ functions in the associated .cpp test file.

These external buffers are used within the buffer descriptors of a shim_dma, i.e., within AIE_DMABdOp operations of a AIE_ShimDMAOp.

Example:

  %buf = aie.external_buffer : memref<256xi64>

This operation represents an external buffer.

Interfaces: OpAsmOpInterface

Attributes:

Attribute	MLIR Type	Description
sym_name	::mlir::StringAttr	string attribute
address	::mlir::IntegerAttr	64-bit signless integer attribute

Results:

Result	Description
buffer	memref of any type values

aie.flow (::xilinx::AIE::FlowOp)

A logical circuit-switched connection between cores

Syntax:

operation ::= `aie.flow` `(` $source `,` $source_bundle `:` $source_channel `,` $dest `,` $dest_bundle `:` $dest_channel `)` attr-dict

The aie.flow operation represents a circuit switched connection between two endpoints, usually aie.tile operations. During routing, this is replaced by aie.connect operations which represent the programmed connections inside a switchbox, along with aie.wire operations which represent physical connections between switchboxes and other components.

Example:

  %00 = aie.tile(0, 0)
  %11 = aie.tile(1, 1)
  %01 = aie.tile(0, 1)
  aie.flow(%00, "DMA" : 0, %11, "Core" : 1)

Attributes:

Attribute	MLIR Type	Description
source_bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
source_channel	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0
dest_bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
dest_channel	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0

Operands:

Operand	Description
source	index
dest	index

aie.get_cascade (::xilinx::AIE::GetCascadeOp)

An op to read from a cascading stream from a neighboring core

Syntax:

operation ::= `aie.get_cascade` `(` `)` attr-dict `:` type($cascade_value)

An op to read from a cascading stream from a neighboring core. The result type of this operation must have a size that matches the cascade size, which is architecture-dependent. e.g. AIE1: i384 or vector<8xi48> AIE2: i512 or vector<16xi32>

Results:

Result	Description
cascade_value	any type

aie.get_stream (::xilinx::AIE::GetStreamOp)

An op to read from a stream channel/port of a switchbox

Syntax:

operation ::= `aie.get_stream` `(` $channel `:` type($channel) `)` attr-dict `:` type($stream_value)

An op to read from a stream channel/port of a switchbox.

Traits: HasParent<CoreOp>

Operands:

Operand	Description
channel	integer

Results:

Result	Description
stream_value	32-bit float or 32-bit signless integer or 128-bit signless integer

aie.lock (::xilinx::AIE::LockOp)

Declare a physical lock

Syntax:

operation ::= `aie.lock` `(` $tile (`,` $lockID^ )? `)` attr-dict

This operation creates a physical lock. For this operation the lockID variable is optional. However, if that is the case then the lockID must be assigned using the AIEAssignLockIDs pass.

Example:

  %tile33 = aie.tile(3, 3)
  %lck = aie.lock(%tile33, 7)

This operation represents a lock that lives in the Memory module of Tile(3, 3) with a lockID of 7

Case when LockID is not assigned: Before AIEAssignLockIDs: %tile33 = aie.tile(3) After AIEAssignLockIDs: %tile33 = aie.tile(3, $assigned_value)

Interfaces: InferTypeOpInterface, OpAsmOpInterface, TileElement

Attributes:

Attribute	MLIR Type	Description
lockID	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0
init	::mlir::IntegerAttr	32-bit signless integer attribute
sym_name	::mlir::StringAttr	string attribute

Operands:

Operand	Description
tile	index

Results:

Result	Description
«unnamed»	index

aie.masterset (::xilinx::AIE::MasterSetOp)

Packet switched input connection

Syntax:

operation ::= `aie.masterset` `(` $dest_bundle `:` $dest_channel `,` $amsels `)` attr-dict

A packet switched connection inside a switchbox. This operation specifies the configuration for a master port.

Example:

  %a0_m2 = aie.amsel<0>(2)
  aie.masterset("Core" : 0, %a0_m2)

The code will configure the master port <”Core” : 0> to use arbiter 0 with msel 2 (see AMSelOp for more details regarding AMSel)

In the current architecture, a master port can only be associated with one arbiter. However, a master port can be activated by different msels from one arbiter

Example:

  %a1_0 = aie.amsel<1>(0)
  %a1_1 = aie.amsel<1>(1)
  %a2_3 = aie.amsel<2>(3)

  aie.masterset("West" : 2, %a1_0, %a2_3) // this is illegal, please don't do this
  aie.masterset("West" : 3, %a1_0, %a1_1) // this is OK

Traits: HasParent<SwitchboxOp>

Interfaces: InferTypeOpInterface

Attributes:

Attribute	MLIR Type	Description
dest_bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
dest_channel	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0
keep_pkt_header	::mlir::BoolAttr	bool attribute

Operands:

Operand	Description
amsels	variadic of index

Results:

Result	Description
«unnamed»	index

aie.mem (::xilinx::AIE::MemOp)

Declare a memory op

Syntax:

operation ::= `aie.mem` `(` $tile `)` regions attr-dict

This operation creates a Memory module that belongs to a tile. The region of a MemOp is used to setup the DMAs and Block Descriptors. See DMAStartOp and DMABdOp for more concrete examples on DMAs and Block Descriptors.

Example:

  m73 = aie.mem(%t73) {
      %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end)
    ^bd0:
      aie.use_lock(%lock, "Acquire", 0)
      aie.dma_bd(%buf : memref<64xi16>, 0, 64)
      aie.use_lock(%lock, "Release", 1)
      aie.next_bd ^bd0
    ^end:
      aie.end
  }

Create the memory module for tile %t73 and setup one DMA channel and one Buffer Descriptor.

Traits: HasValidBDs, HasValidDMAChannels

Interfaces: FlowEndPoint, InferTypeOpInterface, OpAsmOpInterface, TileElement

Operands:

Operand	Description
tile	index

Results:

Result	Description
«unnamed»	index

aie.memtile_dma (::xilinx::AIE::MemTileDMAOp)

Declare a memtile_dma op

Syntax:

operation ::= `aie.memtile_dma` `(` $tile `)` regions attr-dict

This operation describes a DMA inside an AIE2 MemTile. The region of the op is used to setup the DMAs and Block Descriptors. See DMAStartOp and DMABdOp for more concrete examples on DMAs and Block Descriptors.

This operation is restricted to certain compatible tiles in AIE2 devices: xcve2302: row 1 xcve2802: row 1 and 2

Example:

  m73 = aie.memtile_dma(%t71) {
      %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end)
    ^bd0:
      aie.use_lock(%lock, "Acquire", 0)
      aie.dma_bd(%buf : memref<64xi16>, 0, 64>, 0)
      aie.use_lock(%lock, "Release", 1)
      aie.next_bd ^bd0
    ^end:
      aie.end
  }

Create a description for tile %t73 and setup one DMA channel and one Buffer Descriptor.

Traits: HasValidBDs, HasValidDMAChannels

Interfaces: FlowEndPoint, InferTypeOpInterface, OpAsmOpInterface, TileElement

Operands:

Operand	Description
tile	index

Results:

Result	Description
«unnamed»	index

aie.next_bd (::xilinx::AIE::NextBDOp)

The next buffer descriptor

Syntax:

operation ::= `aie.next_bd` $dest attr-dict

This operation terminates the basic block describing a buffer descriptor inside a tile or shim DMA operation. It references a single following buffer descriptor. Note that unlike other terminators (like cf.br), canonicalization should not remove the next_bd terminator, since it would result in invalid buffer descriptors.

Example:

  m73 = aie.mem(%t73) {
      %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end)
    ^bd0:
      aie.use_lock(%lock, "Acquire", 0)
      aie.dma_bd(%buf : memref<64xi16>, 0, 64)
      aie.use_lock(%lock, "Release", 1)
      aie.next_bd ^bd0
    ^end:
      aie.end
  }

Traits: Terminator

Successors:

Successor	Description
dest	any successor

aie.objectfifo (::xilinx::AIE::ObjectFifoCreateOp)

Create a circular buffer or channel between two tiles

Syntax:

operation ::= `aie.objectfifo` $sym_name
              `(`
              custom<ObjectFifoProducerTile>($producerTile, $dimensionsToStream) `,`
              `{`
              custom<ObjectFifoConsumerTiles>($consumerTiles, $dimensionsFromStreamPerConsumer)
              `}`
              `,`
              $elemNumber
              `)` attr-dict `:` $elemType
              custom<ObjectFifoInitValues>(ref($elemNumber), ref($elemType), $initValues)

The aie.objectFifo operation creates a circular buffer established between a producer and one or more consumers, which are aie.tile operations. The aie.objectFifo instantiates the given number of buffers (of given output type) and their locks in the Memory Module of the appropriate tile(s) after lowering, based on tile-adjacency. These elements represent the conceptual depth of the objectFifo or, more specifically, of its object pool.

For the producer and for each consumer, a different size (i.e., element number) can be specified as an array of integer values. This will take effect in the case of consumers placed on tiles non-adjacent to the producer. Otherwise, the producer size will be applied. If a single size is specified, it will be applied to both producer and consumers.

This operation is then converted by the AIEObjectFifoStatefulTransformPass into aie.buffers and their associated aie.locks. The pass also establishes Flow and DMA operations between the producer and consumer tiles if they are not adjacent.

1-to-1 tile example:

  aie.objectfifo @of1 (%tile12, { %tile23 }, 4 : i32) : !aie.objectfifo<memref<16xi32>>

This operation creates an objectFifo between %tile12 and %tile23 of 4 elements, each a buffer of 16 32-bit integers. Note: If there are no ObjectFifoAcquireOps corresponding to this objectFifo on the cores of %tile12 and %tile23, then the depths of the object pools on each tile will be 4, as specified. Otherwise, the cores are scanned and the highest number of acquired elements (+1 for prefetching) will be used instead, to ensure minimal resource usage.

1-to-2 tiles broadcast example:

  aie.objectfifo @of2 (%tile12, { %tile13, %tile23 }, 4 : i32) : !aie.objectfifo<memref<16xi32>>

This operation creates an objectFifo between %tile12 and tiles %tile13, %tile23 of 4 elements, each a buffer of x16 32-bit integers.

1-to-2 tiles broadcast with explicit sizes example:

  aie.objectfifo @of3 (%tile12, { %tile13, %tile23 }, [2, 3, 4]) : !aie.objectfifo<memref<16xi32>>

This operation creates an objectFifo between %tile12, %tile13 and %tile23. The depths of the objectFifo object pool at each tile are respectively 2, 3 and 4 for tiles %tile12, %tile13 and %tile23. This overrides the depth analysis specified in the first example.

Data Layout Transformations on AIE-ML devices

On AIE-ML devices, objectFifos can also apply data layout transformations by using the DMAs n-dimensional address generation scheme. Two transformations can be applied for an objectFifo: one on the producer side, given by a dimensionsToStream attribute, and one transformation on the consumer side, given by a dimensionsFromStream attribute. See the DMABDOp documentation for a description of strides and sizes. The dimensionsToStream and dimensionsFromStream optional attributes are given directly following the producer or consumer tile declaration. Different transformations can be specified for each consumer. See example below.

Note that using data layout transformations will cause DMAs to be used even between adjacent tiles whose objectFifos would otherwise use shared memory.

Further note that data layout transforms always apply at a granularity of i32s, irrespective of the used memref data type. This is an architectural requirement. Hence, a stride of 4 always expresses 4 i32s, i.e. 16 bytes.

The following example shows an objectFifo which transposes a 16x16 matrix of i32s on the producer side using strides and sizes. No transformation is applied on the consumer side of %tile13 (in this case the fromStream attribute may also be left off), and a transformation on %tile23 first gives all even indices from the stream, followed by all odd indices:

  aie.objectfifo @of4 (%tile12 dimensionsToStream [<16, 1>, <16, 16>, <1,1>],
                       {
                        %tile13 dimensionsFromStream [],
                        %tile23 dimensionsFromStream [<2, 1>, <128, 2>]
                       }, 2 : i32
                      ) : !aie.objectfifo<memref<256xi32>>

The behavior of the objectFifo is further controlled by optional parameters. The repeat_count parameter specifies the number of times each individual object is repeated during transfer. When repeat_count == 1, each object is transferred once.

The iter_count parameter specifies the number of iterations of the buffer descriptor chain generated at the lower level. The total number of objects transferred is calculated as iter_count * elemNumber * repeat_count. When repeat_count == 1, this simplifies to iter_count * elemNumber.

Traits: HasParent<DeviceOp>

Interfaces: Symbol

Attributes:

Attribute	MLIR Type	Description
sym_name	::mlir::StringAttr	string attribute
elemNumber	::mlir::Attribute	32-bit signless integer attribute whose minimum value is 0 or array attribute
elemType	::mlir::TypeAttr	type attribute of
dimensionsToStream	::xilinx::AIE::BDDimLayoutArrayAttr
dimensionsFromStreamPerConsumer	::xilinx::AIE::BDDimLayoutArrayArrayAttr
via_DMA	::mlir::BoolAttr	bool attribute
plio	::mlir::BoolAttr	bool attribute
disable_synchronization	::mlir::BoolAttr	bool attribute
repeat_count	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 1
initValues	::mlir::ArrayAttr	array of ElementsAttr
padDimensions	::xilinx::AIE::BDPadLayoutArrayAttr
iter_count	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
producerTile	index
consumerTiles	variadic of index

aie.objectfifo.acquire (::xilinx::AIE::ObjectFifoAcquireOp)

Acquire operation to lock and return objects of an ObjectFifo

Syntax:

operation ::= `aie.objectfifo.acquire` attr-dict $objFifo_name `(` $port `,` $size `)` `:` qualified(type($subview))

The aie.objectFifo.acquire operation first acquires the locks of the next given number of objects in the objectFifo. The mode it acquires the locks in is chosen based on the port (producer: acquire for write, consumer: acquire for read). Then, it returns a subview of the acquired objects which can be used to access them.

This operation is then converted by the AIEObjectFifoStatefulTransformPass into aie.use_lock operations on the locks of the objectFifo objects that will be acquired. Under the hood, the operation only performs new acquires if necessary. For example, if two objects have been acquired in the past and none have yet to be released by the same process, then performing another acquire operation on the same objectFifo within the same process of size two or less will not result in any new use_lock operations (and for size greater than two, only (size - 2) use_lock operations will be performed).

Example:

  %subview = aie.objectfifo.acquire @of1 (Consume, 2) : !aie.objectfifosubview<memref<16xi32>>

This operation acquires the locks of the next two objects in the objectFifo named @of1 from its consumer port and returns a subview of the acquired objects.

Attributes:

Attribute	MLIR Type	Description
port	xilinx::AIE::ObjectFifoPortAttr	Ports of an object FIFO
objFifo_name	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
size	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 1

Results:

Result	Description
subview

aie.objectfifo.allocate (::xilinx::AIE::ObjectFifoAllocateOp)

Sets a tile’s memory module as the target for an objectfifo’s memory allocation

Syntax:

operation ::= `aie.objectfifo.allocate` $objFifo_name `(` $delegateTile `)` attr-dict

Specify a tile’s memory module to be used as the allocation target for this objectfifo. Only works if all the objectfifo’s tiles, producer and consumers, have shared memory access to the specified tile’s memory module.

In the following example the objects of @of4 will be allocated on %tile14:

  aie.objectfifo @of4 (%tile13, { %tile14 }, 2 : i32) : !aie.objectfifo<memref<256xi32>>
  aie.objectfifo.allocate @of4 (%tile14)

Traits: HasParent<DeviceOp>

Attributes:

Attribute	MLIR Type	Description
objFifo_name	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:

Operand	Description
delegateTile	index

aie.objectfifo.link (::xilinx::AIE::ObjectFifoLinkOp)

Links two objectFifos through an intermediary tile’s DMA

Syntax:

operation ::= `aie.objectfifo.link` $fifoIns `->` $fifoOuts `(` $src_offsets $dst_offsets `)` attr-dict

The aie.objectfifo.link operation marks two or more objectFifos as linked. This implies that the objectFifos form one dataflow movement which is split accross multiple objectFifos. Specifically, during the objectFifo lowering there will be less memory elements generated at the link point (i.e., the shared tile of all objectFifos in the link) as the objectFifos can share.

The objectFifos which are linked must have a link point (i.e., a shared AIE tile).

Example:

  aie.objectfifo @of1 (%t70, { %t72 }, 2) : !aie.objectfifo<memref<64xi16>>
  aie.objectfifo @of2 (%t72, { %t74 }, 2) : !aie.objectfifo<memref<64xi16>>
  aie.objectfifo.link [@of1] -> [@of2] ([] [])

This operation links two objectFifos which have tile %t72 as a link point. The offset input arrays are not required as the full size of the objects are transferred from @of1 to @of2.

To achieve a broadcast pattern through the link tile, the output objectFifo should have a list of all the consumers tiles. To achieve a distribute pattern from the link tile, there should be multiple output objectFifos in the OjbectFifoLinkOp. In this case, parts will be taken out of the input objectFifo’s buffers based on dst_offsets input array. The join pattern is the exact inverse of the distribute one and uses the src_offsets input array instead.

In the cases of the join and distribute patterns, the link has some special restrictions on toStream and fromStream dimensions:

• join: the toStream dimensions of the output objectFifo cannot access an index beyond the length of the minimum transfer length in the src_offsets.
• distribute: the fromStream dimensions of the input objectFifo cannot access an index beyond the length of the minimum transfer length in dst_offsets.

Traits: HasParent<DeviceOp>

Attributes:

Attribute	MLIR Type	Description
fifoIns	::mlir::ArrayAttr	symbol ref array attribute
fifoOuts	::mlir::ArrayAttr	symbol ref array attribute
src_offsets	::mlir::ArrayAttr	64-bit integer array attribute
dst_offsets	::mlir::ArrayAttr	64-bit integer array attribute

aie.objectfifo.register_external_buffers (::xilinx::AIE::ObjectFifoRegisterExternalBuffersOp)

Registers external buffers to an objectFifo’s shim tile(s) for use in the associated shim DMA(s)

Syntax:

operation ::= `aie.objectfifo.register_external_buffers` attr-dict $objFifo_name `(` $tile `,` `{` $externalBuffers `}` `)` `:` `(` type($externalBuffers) `)`

The aie.objectfifo.register_external_buffers operation is used to register one or multiple external buffers to the shim tile(s) used in an objectFifo creation. During the objectFifo lowering pass, shim DMAs that are generated for those shim tiles will use the registered external buffers. This is currently done because external buffers typically have a different size than the AIE buffers which are used in the AIE tiles of the same objectFifos.

Example:

  aie.objectfifo @of1 (%t70, %t73, 2) : !aie.objectfifo<memref<64xi16>>
  %buffer_in_0  = aie.external_buffer : memref<512 x i16>
  %buffer_in_1  = aie.external_buffer : memref<512 x i16>
  aie.objectfifo.register_external_buffers @of1 (%t70, {buffer_in_0, buffer_in_1}) : (memref<512 x i16>, memref<512 x i16>)

This operation registers external buffers %buffer_in_0 and %buffer_in_1 to use in the shim_dma of shimTile %t70.

Traits: HasParent<DeviceOp>

Interfaces: OpAsmOpInterface, TileElement

Attributes:

Attribute	MLIR Type	Description
objFifo_name	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:

Operand	Description
tile	index
externalBuffers	variadic of memref of any type values

aie.objectfifo.register_process (::xilinx::AIE::ObjectFifoRegisterProcessOp)

Operation that produces the acquire/release patterns for a process registered to an objectFifo

Syntax:

operation ::= `aie.objectfifo.register_process` attr-dict $objFifo_name `(`
              $port `,`
              $acquirePatternTensor `:` type($acquirePatternTensor) `,`
              $releasePatternTensor `:` type($releasePatternTensor) `,`
              $callee `,` $length
              `)`

The aie.registerProcess operation allows the user to register a function to an objectFifo along with its acquire and release patterns. These patterns will be used to generate a sequence of acquires and releases on the objectFifo elements. This generated sequence is often in the form of a for loop, however, in the case of cyclo-static patterns only the repetition of same number accesses and releases will generate a for loop. This may result in multiple for loops of different sizes being generated. If there is no repetition, then no loops will be generated.

Example:

  aie.objectfifo @of1 (%t72, %t73, 2) : !aie.objectfifo<memref<16xi32>>
  %length = arith.constant 10 : index
  %acquirePatternProducer = arith.constant dense<[1, 2, 2, 0]> : tensor<4xi32>
  %releasePatternProducer = arith.constant dense<[0, 1, 1, 2]> : tensor<4xi32>
  func @producer_work(%input : !aie.objectfifosubview<memref<16xi32>>) -> () { ... }

  aie.objectfifo.register_process @of1 (Produce, %acquirePatternProducer : tensor<4xi32>, %releasePatternProducer : tensor<4xi32>, @producer_work, %length)

This operation registers function @producer_work and associated patterns to the produce end of @of1. @producer_work will be called with the subviews produced when acquiring elements from @of1 following the acquire pattern.

If the input patterns are static (only one element) then the length of the produced for loop will be that of the input %length. If the input patterns are cyclo-static then they must be of the same size.

Attributes:

Attribute	MLIR Type	Description
port	xilinx::AIE::ObjectFifoPortAttr	Ports of an object FIFO
objFifo_name	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
callee	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:

Operand	Description
acquirePatternTensor	tensor of 32-bit signless integer values
releasePatternTensor	tensor of 32-bit signless integer values
length	index

aie.objectfifo.release (::xilinx::AIE::ObjectFifoReleaseOp)

Release operation for object locks in an ObjectFifo

Syntax:

operation ::= `aie.objectfifo.release` attr-dict $objFifo_name `(` $port `,` $size `)`

The aie.objectFifo.release operation releases the locks of the given number of objects in the objectFifo. The mode it releases the locks in is chosen based on the port (producer: release for read, consumer: release for write).

This operation is then converted by the AIEObjectFifoStatefulTransformPass into aie.use_lock operations.

Example:

  aie.objectfifo.release @of1 (Produce, 1)

This operation releases the lock of the next object in the objectFifo named @of1 from producer port.

Attributes:

Attribute	MLIR Type	Description
port	xilinx::AIE::ObjectFifoPortAttr	Ports of an object FIFO
objFifo_name	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
size	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 1

aie.objectfifo.subview.access (::xilinx::AIE::ObjectFifoSubviewAccessOp)

ObjectFifoSubview type accessor method

Syntax:

operation ::= `aie.objectfifo.subview.access` $subview `[` $index `]` attr-dict `:` qualified(type($subview)) `->` qualified(type($output))

Access the Nth element of a value of ObjectFifoSubview type.

Example:

  %subview = aie.objectfifo.acquire @of1 (Produce, 3) : !aie.objectfifosubview<memref<16xi32>>
  %elem = aie.objectfifo.subview.access %subview[0] : !aie.objectfifosubview<memref<16xi32>> -> memref<16xi32>

In this example, %elem is the first object of the subview. Note that this may not correspond to the first element of the objectFifo if other acquire operations took place beforehand.

Attributes:

Attribute	MLIR Type	Description
index	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0

Operands:

Operand	Description
subview

Results:

Result	Description
output	memref of any type values

aie.packet_dest (::xilinx::AIE::PacketDestOp)

A destination port

Syntax:

operation ::= `aie.packet_dest` `<` $tile `,` $bundle `:` $channel `>` attr-dict

A object representing the destination of a packet-switched flow. This must exist within an aie.packet_flow operation. The destination Must be unique within a design.

See aie.packet_flow for an example.

Traits: HasParent<PacketFlowOp>

Attributes:

Attribute	MLIR Type	Description
bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
channel	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0

Operands:

Operand	Description
tile	index

aie.packet_flow (::xilinx::AIE::PacketFlowOp)

Packet switched flow

Syntax:

operation ::= `aie.packet_flow` `(` $ID `)` regions attr-dict

A logical packet-switched flow between tiles. During place and route, this is replaced by MasterSets and PacketRules inside switchboxes.

The optional attribute keep_pkt_header indicates whether each data packet’s packet header gets preserved at the flow’s destination. The optional attribute priority_route indicates whether the packet flow is routed in priority over other flows, so that they always get allocated with the same master, slave ports, arbiters and master selects (msel).

Example:

  %01 = aie.tile(0, 1)
  aie.packet_flow(0x10) {
    aie.packet_source<%01, "Core" : 0>
    aie.packet_dest<%01, "Core" : 0>
  }

Traits: SingleBlockImplicitTerminator<EndOp>, SingleBlock

Attributes:

Attribute	MLIR Type	Description
ID	::mlir::IntegerAttr	8-bit signless integer attribute
keep_pkt_header	::mlir::BoolAttr	bool attribute
priority_route	::mlir::BoolAttr	bool attribute

aie.packet_rules (::xilinx::AIE::PacketRulesOp)

Packet switched routing rules

Syntax:

operation ::= `aie.packet_rules` `(` $source_bundle `:` $source_channel `)` regions attr-dict

This operation defines packet-switched routing configuration for packets entering a switchbox. It references a port of the containing switchbox, which must be unique among other packetRules operations and aie.connect operations in the containing switchbox. It contains a region of up to 4 aie.rule operations.

See aie.rule for an example.

Traits: SingleBlockImplicitTerminator<EndOp>, SingleBlock

Attributes:

Attribute	MLIR Type	Description
source_bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
source_channel	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0

aie.packet_source (::xilinx::AIE::PacketSourceOp)

A sourceport

Syntax:

operation ::= `aie.packet_source` `<` $tile `,` $bundle `:` $channel `>` attr-dict

An object representing the destination of a packet-switched flow. This must exist within an aie.packet_flow operation.

See aie.packet_flow for an example.

Traits: HasParent<PacketFlowOp>

Attributes:

Attribute	MLIR Type	Description
bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
channel	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0

Operands:

Operand	Description
tile	index

aie.plio (::xilinx::AIE::PLIOOp)

Declare an interface to the PL

Syntax:

operation ::= `aie.plio` `(` $col `)` attr-dict

An interface to the PL.

Interfaces: InferTypeOpInterface

Attributes:

Attribute	MLIR Type	Description
col	::mlir::IntegerAttr	32-bit signless integer attribute

Results:

Result	Description
«unnamed»	index

aie.put_cascade (::xilinx::AIE::PutCascadeOp)

An op to write to a cascading stream from a neighboring core

Syntax:

operation ::= `aie.put_cascade` `(` $cascade_value `:` type($cascade_value) `)` attr-dict

An op to write to a cascading stream from a neighboring core. The argument type of this operation must have a size that matches the cascade size, which is architecture-dependent. e.g. AIE1: i384 or vector<8xi48> AIE2: i512 or vector<16xi32>

Operands:

Operand	Description
cascade_value	any type

aie.put_stream (::xilinx::AIE::PutStreamOp)

An op to write to a stream channel/port of a switchbox

Syntax:

operation ::= `aie.put_stream` `(` $channel `:` type($channel) `,` $stream_value `:` type($stream_value) `)` attr-dict

An op to write to a stream channel/port of a switchbox.

Traits: HasParent<CoreOp>

Operands:

Operand	Description
channel	integer
stream_value	32-bit float or 32-bit signless integer or 128-bit signless integer

aie.rule (::xilinx::AIE::PacketRuleOp)

Packet switched routing rule

Syntax:

operation ::= `aie.rule` `(` $mask `,` $value `,` $amsel `)` attr-dict

This operation defines a matching rule and a destination for packet-switched connections in a switchbox. Routing is based on the ID field of packet arriving on the matching port of the containing aie.packetRules. The ID is first bitwise-AND’d with the mask and then checked for equality with the given ID. It is routed to arbiter and master set associated with the first matching entry.

Example: LUT ID | Mask | ID | Arbiter | Msel — | — | — | — | — 0 | 5’b11111 | 5’b00010 | 4 | 1 1 | 5’b11011 | 5’b00001 | 3 | 2 2 | | | | 3 | | | |

If a packet flow that has an ID of 2, it will be directed to the arbiter 4 with msel 1, If a packet flow that has an ID of 1 or 5, it will be directed to the arbiter 3 with msel 2,

We encapsulate the configuration table as follows: Example:

  %a4_1 = aie.amsel<4>(1)
  %a3_2 = aie.amsel<3>(2)

  aie.packet_rules("Core" : 0) {
    aie.rule(0x1F, 0x2, %a4_1)
    aie.rule(0x1B, 0x1, %a3_2)
  }

Traits: HasParent<PacketRulesOp>

Attributes:

Attribute	MLIR Type	Description
mask	::mlir::IntegerAttr	8-bit signless integer attribute
value	::mlir::IntegerAttr	8-bit signless integer attribute

Operands:

Operand	Description
amsel	index

aie.runtime_sequence (::xilinx::AIE::RuntimeSequenceOp)

Program the configuration co-processor of the AI Engine array

Instructions in this operation allow for runtime (re-)configuration of the AI Engine array, such as configuring data movement buffer descriptors. These instructions will execute on the configuration co-processor of the AI Engine array.

Typically, these instructions include configuring the data transfers between host and AIE array on the shims. The input arguments are arguments passed in from the host at kernel invocation time. This may include buffers on the host.

Traits: HasParent<DeviceOp>, NoTerminator

Interfaces: Symbol

Attributes:

Attribute	MLIR Type	Description
sym_name	::mlir::StringAttr	string attribute

aie.shim_dma (::xilinx::AIE::ShimDMAOp)

Declare a DMA in the PL shim

Syntax:

operation ::= `aie.shim_dma` `(` $tile `)` regions attr-dict

This operation creates a DMA that belongs to a shim tile. The region of a ShimDMAOp is used to setup the DMAs and Block Descriptors.

Example:

  %buf = aie.external_buffer : memref<256xi64>
  %lock1 = aie.lock(%t70, 1)

  %dma = aie.shim_dma(%t70) {
      aie.dma_start(MM2S, 0, ^bd0, ^end)
    ^bd0:
      aie.use_lock(%lock1, Acquire, 1)
      aie.dma_bd(%buf : memref<512 x i16>, 0, 512)
      aie.use_lock(%lock1, Release, 0)
      aie.next_bd ^bd0
    ^end:
      aie.end
  }

Create the shim_dma for tile %t70 and setup one DMA channel and one Buffer Descriptor.

Traits: HasValidBDs, HasValidDMAChannels

Interfaces: FlowEndPoint, InferTypeOpInterface, OpAsmOpInterface, TileElement

Operands:

Operand	Description
tile	index

Results:

Result	Description
«unnamed»	index

aie.shim_dma_allocation (::xilinx::AIE::ShimDMAAllocationOp)

Runtime allocation information for a single shim DMA

Syntax:

operation ::= `aie.shim_dma_allocation` $sym_name `(` $tile `,` $channel_dir `,` $channel_index (`,` $packet^)? `)` attr-dict

This op exists for cases where shim_dma configuration is performed outside of MLIR-AIE and hence there is no appropriate dma_start operation to indicate which channel is being used and on which shim tile the shim_dma is.

It contains attributes for the sym_name of an operation which generated the shim DMA, for the DMAChannelDir and channel index, and a reference to the shim tile.

Example:

  %tile00 = aie.tile(0, 0)
  %tile02 = aie.tile(0, 2)
  aie.objectfifo @of_in_0 (%tile00, { %tile02 }, 2) : !aie.objectfifo<memref<64xi16>>

could produce the following allocation info (channel direction MM2S, channel index 1, on tile %tile00):

  aie.shim_dma_allocation @of_in_0 (%tile00, MM2S, 1)

Traits: HasParent<DeviceOp>

Interfaces: Symbol

Attributes:

Attribute	MLIR Type	Description
sym_name	::mlir::StringAttr	string attribute
channel_dir	xilinx::AIE::DMAChannelDirAttr	DMA Channel direction
channel_index	::mlir::IntegerAttr	64-bit signless integer attribute
plio	::mlir::BoolAttr	bool attribute
packet	::xilinx::AIE::PacketInfoAttr	Tuple encoding the type and header of a packet;

Operands:

Operand	Description
tile	index

aie.shim_mux (::xilinx::AIE::ShimMuxOp)

Declare a switch in the PL shim

Syntax:

operation ::= `aie.shim_mux` `(` $tile `)` regions attr-dict

This operation represents the additional interconnect that is part of a shim interface tile. Like the aie.switchbox operation, aie.shim_mux is configured by code in its region, but can only contain connect operations

Example:

%tile = aie.tile(1, 1)
aie.shim_mux(%tile) {
  aie.connect<"North" : 0, "DMA" : 1>
}

Traits: SingleBlockImplicitTerminator<EndOp>, SingleBlock

Interfaces: InferTypeOpInterface, Interconnect, OpAsmOpInterface, TileElement

Operands:

Operand	Description
tile	index

Results:

Result	Description
«unnamed»	index

aie.shim_switchbox (::xilinx::AIE::ShimSwitchboxOp)

Declare a switch in the PL shim

Syntax:

operation ::= `aie.shim_switchbox` `(` $col `)` regions attr-dict

A switch in the Shim. AXI-Stream Master Ports AXI-Stream Slave Ports 6 Ports to North (Core Tile) 4 Ports from North (Core Tile) 4 Ports to West 4 Ports from West 4 Ports to East 4 Ports from East 6 Ports to South (DMA, NoC I/F, PL I/F) 8 Ports from South (DMA, NoC I/F, PL I/F) 2 Ports to FIFOs 2 Ports from FIFOs 1 Port for control packet for Shim register access 1 Port for response to access for Shim registers 1 Port for trace packet from Shim

Traits: SingleBlockImplicitTerminator<EndOp>, SingleBlock

Interfaces: InferTypeOpInterface

Attributes:

Attribute	MLIR Type	Description
col	::mlir::IntegerAttr	32-bit signless integer attribute

Results:

Result	Description
«unnamed»	index

aie.switchbox (::xilinx::AIE::SwitchboxOp)

Declare a switch

Syntax:

operation ::= `aie.switchbox` `(` $tile `)` regions attr-dict

This operation represents the switchbox that is part of a tile. A switchbox is configured by code in its region, representing various connections

Example:

%tile = aie.tile(1, 1)
aie.switchbox(%tile) {
  aie.connect<"West" : 0, "Core" : 1>
}

Traits: SingleBlockImplicitTerminator<EndOp>, SingleBlock

Interfaces: InferTypeOpInterface, Interconnect, OpAsmOpInterface, TileElement

Operands:

Operand	Description
tile	index

Results:

Result	Description
result	index

aie.tile (::xilinx::AIE::TileOp)

Declare an AIE tile

Syntax:

operation ::= `aie.tile` `(` $col `,` $row `)` attr-dict

This operation creates an AIE tile in the AIE array. We specify the column and the row of the tile. Optionally, we can specify the memory allocation scheme for the tile (basic-sequential or bank-aware).

A tile encompasses core module (CoreOp), memory module (MemOp), stream switch (SwitchboxOp), memory buffer (BufferOp), and lock (LockOp).

A tile is a logical abstraction. We use a tile to establish ownership of a hardware entity.

Note that row 0 of the Tile array is different from other rows, since it models the shim interface between the AIE array proper and the PL. The South-West/Lower Right most core exists in Tile(0,1).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, FlowEndPoint, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface), OpAsmOpInterface

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
col	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0
row	::mlir::IntegerAttr	32-bit signless integer attribute whose minimum value is 0
allocation_scheme	::mlir::StringAttr	string attribute

Results:

Result	Description
result	index

aie.use_lock (::xilinx::AIE::UseLockOp)

Acquire/release lock op

Syntax:

operation ::= `aie.use_lock` `(` $lock `,` $action (`,` $value^)? (`,` $blocking^)? `)` attr-dict

This operation uses a lock. AIE1 locks are binary locks while AIE2 locks are counting semaphores without an inherent acquire/release characteristic. This operation must appear in a parent op where the tile can be determined (A CoreOp, a ShimDMAOp, a MemOp, or a MemTileDMAOp). The behavior of this operation is dependent on action:

• Acquire: blocks execution until the lock is set to value.
• AcquireGreaterEqual (only AIE2): blocks execution until the lock is set to value or greater. Then, the value of the lock is decremented by value.
• Release: In AIE1, set the lock to value. In AIE2, increment the lock by value.

Attributes:

Attribute	MLIR Type	Description
action	xilinx::AIE::LockActionAttr	lock acquire/release
value	::mlir::IntegerAttr	32-bit signless integer attribute
blocking	xilinx::AIE::LockBlockingAttr	lock operation is blocking
acq_en	::mlir::BoolAttr	bool attribute

Operands:

Operand	Description
lock	index

aie.wire (::xilinx::AIE::WireOp)

A bundle of physical wires between components

Syntax:

operation ::= `aie.wire` `(` $source `:` $source_bundle `,` $dest `:` $dest_bundle `)` attr-dict

The aie.wire operation represents a physical set of connections between components in a Versal device. Typically, these components are switches, represented by an aie.switchbox operation, and tiles, represented by an aie.tile operation.

Attributes:

Attribute	MLIR Type	Description
source_bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
dest_bundle	xilinx::AIE::WireBundleAttr	Bundle of wires

Operands:

Operand	Description
source	index
dest	index

Attributes

BDDimLayoutArrayArrayAttr

Syntax:

#aie.bd_dim_layout_array_array<
  ::llvm::ArrayRef<BDDimLayoutArrayAttr>   # value
>

Parameters:

Parameter	C++ type	Description
value	::llvm::ArrayRef<BDDimLayoutArrayAttr>

BDDimLayoutArrayAttr

Syntax:

#aie.bd_dim_layout_array<
  ::llvm::ArrayRef<BDDimLayoutAttr>   # value
>

Parameters:

Parameter	C++ type	Description
value	::llvm::ArrayRef<BDDimLayoutAttr>

BDDimLayoutAttr

Tuple encoding the stride and size of one dimension in an AIE2 n-dimensional buffer descriptor;

Syntax:

#aie.bd_dim_layout<
  uint32_t,   # size
  uint32_t   # stride
>

Parameters:

Parameter	C++ type	Description
size	uint32_t
stride	uint32_t

BDPadLayoutArrayAttr

Syntax:

#aie.bd_pad_layout_array<
  ::llvm::ArrayRef<BDPadLayoutAttr>   # value
>

Parameters:

Parameter	C++ type	Description
value	::llvm::ArrayRef<BDPadLayoutAttr>

BDPadLayoutAttr

Tuple encoding number of zeros before and after on that dimension in an AIE2 n-dimensional buffer descriptor;

Syntax:

#aie.bd_pad_layout<
  uint16_t,   # const_pad_before
  uint16_t   # const_pad_after
>

Parameters:

Parameter	C++ type	Description
const_pad_before	uint16_t
const_pad_after	uint16_t

PacketInfoAttr

Tuple encoding the type and header of a packet;

Syntax:

#aie.packet_info<
  uint16_t,   # pkt_type
  uint16_t   # pkt_id
>

Parameters:

Parameter	C++ type	Description
pkt_type	uint16_t
pkt_id	uint16_t

Types

AIEObjectFifoSubviewType

Syntax:

!aie.objectfifosubview<
  ::mlir::MemRefType   # memref
>

An Object FIFO subview represents a subview of an object FIFO.

Parameters:

Parameter	C++ type	Description
memref	::mlir::MemRefType	memref of any type values

AIEObjectFifoType

Syntax:

!aie.objectfifo<
  ::mlir::MemRefType   # memref
>

An object FIFO represents the data movement connection between a source and one or multiple destinations.

Parameters:

Parameter	C++ type	Description
memref	::mlir::MemRefType	memref of any type values

Enums

AIEArch

AIE Architecture

Cases:

Symbol	Value	String
AIE1	1	AIE1
AIE2	2	AIE2
AIE2p	3	AIE2p

AIEDevice

AIE Device

Cases:

Symbol	Value	String
xcvc1902	1	xcvc1902
xcve2302	2	xcve2302
xcve2802	3	xcve2802
npu1	4	npu1
npu1_1col	5	npu1_1col
npu1_2col	6	npu1_2col
npu1_3col	7	npu1_3col
npu2	8	npu2
npu2_1col	9	npu2_1col
npu2_2col	10	npu2_2col
npu2_3col	11	npu2_3col
npu2_4col	12	npu2_4col
npu2_5col	13	npu2_5col
npu2_6col	14	npu2_6col
npu2_7col	15	npu2_7col

CascadeDir

Directions for cascade

Cases:

Symbol	Value	String
South	3	South
West	4	West
North	5	North
East	6	East

CoreEvent

Core module event enumeration for AIE

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
PERF_CNT_2	7	PERF_CNT_2
PERF_CNT_3	8	PERF_CNT_3
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
GROUP_PC_EVENT	15	GROUP_PC_EVENT
PC_0	16	PC_0
PC_1	17	PC_1
PC_2	18	PC_2
PC_3	19	PC_3
PC_RANGE_0_1	20	PC_RANGE_0_1
PC_RANGE_2_3	21	PC_RANGE_2_3
GROUP_STALL	22	GROUP_STALL
MEMORY_STALL	23	MEMORY_STALL
STREAM_STALL	24	STREAM_STALL
CASCADE_STALL	25	CASCADE_STALL
LOCK_STALL	26	LOCK_STALL
DEBUG_HALTED	27	DEBUG_HALTED
ACTIVE	28	ACTIVE
DISABLED	29	DISABLED
ECC_ERROR_STALL	30	ECC_ERROR_STALL
ECC_SCRUBBING_STALL	31	ECC_SCRUBBING_STALL
GROUP_PROGRAM_FLOW	32	GROUP_PROGRAM_FLOW
INSTR_EVENT_0	33	INSTR_EVENT_0
INSTR_EVENT_1	34	INSTR_EVENT_1
INSTR_CALL	35	INSTR_CALL
INSTR_RETURN	36	INSTR_RETURN
INSTR_VECTOR	37	INSTR_VECTOR
INSTR_LOAD	38	INSTR_LOAD
INSTR_STORE	39	INSTR_STORE
INSTR_STREAM_GET	40	INSTR_STREAM_GET
INSTR_STREAM_PUT	41	INSTR_STREAM_PUT
INSTR_CASCADE_GET	42	INSTR_CASCADE_GET
INSTR_CASCADE_PUT	43	INSTR_CASCADE_PUT
INSTR_LOCK_ACQUIRE_REQ	44	INSTR_LOCK_ACQUIRE_REQ
INSTR_LOCK_RELEASE_REQ	45	INSTR_LOCK_RELEASE_REQ
GROUP_ERRORS_0	46	GROUP_ERRORS_0
GROUP_ERRORS_1	47	GROUP_ERRORS_1
SRS_SATURATE	48	SRS_SATURATE
UPS_SATURATE	49	UPS_SATURATE
FP_OVERFLOW	50	FP_OVERFLOW
FP_UNDERFLOW	51	FP_UNDERFLOW
FP_INVALID	52	FP_INVALID
FP_DIV_BY_ZERO	53	FP_DIV_BY_ZERO
TLAST_IN_WSS_WORDS_0_2	54	TLAST_IN_WSS_WORDS_0_2
PM_REG_ACCESS_FAILURE	55	PM_REG_ACCESS_FAILURE
STREAM_PKT_PARITY_ERROR	56	STREAM_PKT_PARITY_ERROR
CONTROL_PKT_ERROR	57	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	58	AXI_MM_SLAVE_ERROR
INSTR_DECOMPRSN_ERROR	59	INSTR_DECOMPRSN_ERROR
DM_ADDRESS_OUT_OF_RANGE	60	DM_ADDRESS_OUT_OF_RANGE
PM_ECC_ERROR_SCRUB_CORRECTED	61	PM_ECC_ERROR_SCRUB_CORRECTED
PM_ECC_ERROR_SCRUB_2BIT	62	PM_ECC_ERROR_SCRUB_2BIT
PM_ECC_ERROR_1BIT	63	PM_ECC_ERROR_1BIT
PM_ECC_ERROR_2BIT	64	PM_ECC_ERROR_2BIT
PM_ADDRESS_OUT_OF_RANGE	65	PM_ADDRESS_OUT_OF_RANGE
DM_ACCESS_TO_UNAVAILABLE	66	DM_ACCESS_TO_UNAVAILABLE
LOCK_ACCESS_TO_UNAVAILABLE	67	LOCK_ACCESS_TO_UNAVAILABLE
INSTR_EVENT_2	68	INSTR_EVENT_2
INSTR_EVENT_3	69	INSTR_EVENT_3
GROUP_STREAM_SWITCH	73	GROUP_STREAM_SWITCH
PORT_IDLE_0	74	PORT_IDLE_0
PORT_RUNNING_0	75	PORT_RUNNING_0
PORT_STALLED_0	76	PORT_STALLED_0
PORT_TLAST_0	77	PORT_TLAST_0
PORT_IDLE_1	78	PORT_IDLE_1
PORT_RUNNING_1	79	PORT_RUNNING_1
PORT_STALLED_1	80	PORT_STALLED_1
PORT_TLAST_1	81	PORT_TLAST_1
PORT_IDLE_2	82	PORT_IDLE_2
PORT_RUNNING_2	83	PORT_RUNNING_2
PORT_STALLED_2	84	PORT_STALLED_2
PORT_TLAST_2	85	PORT_TLAST_2
PORT_IDLE_3	86	PORT_IDLE_3
PORT_RUNNING_3	87	PORT_RUNNING_3
PORT_STALLED_3	88	PORT_STALLED_3
PORT_TLAST_3	89	PORT_TLAST_3
PORT_IDLE_4	90	PORT_IDLE_4
PORT_RUNNING_4	91	PORT_RUNNING_4
PORT_STALLED_4	92	PORT_STALLED_4
PORT_TLAST_4	93	PORT_TLAST_4
PORT_IDLE_5	94	PORT_IDLE_5
PORT_RUNNING_5	95	PORT_RUNNING_5
PORT_STALLED_5	96	PORT_STALLED_5
PORT_TLAST_5	97	PORT_TLAST_5
PORT_IDLE_6	98	PORT_IDLE_6
PORT_RUNNING_6	99	PORT_RUNNING_6
PORT_STALLED_6	100	PORT_STALLED_6
PORT_TLAST_6	101	PORT_TLAST_6
PORT_IDLE_7	102	PORT_IDLE_7
PORT_RUNNING_7	103	PORT_RUNNING_7
PORT_STALLED_7	104	PORT_STALLED_7
PORT_TLAST_7	105	PORT_TLAST_7
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

CoreEventAIE2

Core module event enumeration for AIE2

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
PERF_CNT_2	7	PERF_CNT_2
PERF_CNT_3	8	PERF_CNT_3
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	13	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	14	EDGE_DETECTION_EVENT_1
GROUP_PC_EVENT	15	GROUP_PC_EVENT
PC_0	16	PC_0
PC_1	17	PC_1
PC_2	18	PC_2
PC_3	19	PC_3
PC_RANGE_0_1	20	PC_RANGE_0_1
PC_RANGE_2_3	21	PC_RANGE_2_3
GROUP_STALL	22	GROUP_STALL
MEMORY_STALL	23	MEMORY_STALL
STREAM_STALL	24	STREAM_STALL
CASCADE_STALL	25	CASCADE_STALL
LOCK_STALL	26	LOCK_STALL
DEBUG_HALTED	27	DEBUG_HALTED
ACTIVE	28	ACTIVE
DISABLED	29	DISABLED
ECC_ERROR_STALL	30	ECC_ERROR_STALL
ECC_SCRUBBING_STALL	31	ECC_SCRUBBING_STALL
GROUP_PROGRAM_FLOW	32	GROUP_PROGRAM_FLOW
INSTR_EVENT_0	33	INSTR_EVENT_0
INSTR_EVENT_1	34	INSTR_EVENT_1
INSTR_CALL	35	INSTR_CALL
INSTR_RETURN	36	INSTR_RETURN
INSTR_VECTOR	37	INSTR_VECTOR
INSTR_LOAD	38	INSTR_LOAD
INSTR_STORE	39	INSTR_STORE
INSTR_STREAM_GET	40	INSTR_STREAM_GET
INSTR_STREAM_PUT	41	INSTR_STREAM_PUT
INSTR_CASCADE_GET	42	INSTR_CASCADE_GET
INSTR_CASCADE_PUT	43	INSTR_CASCADE_PUT
INSTR_LOCK_ACQUIRE_REQ	44	INSTR_LOCK_ACQUIRE_REQ
INSTR_LOCK_RELEASE_REQ	45	INSTR_LOCK_RELEASE_REQ
GROUP_ERRORS_0	46	GROUP_ERRORS_0
GROUP_ERRORS_1	47	GROUP_ERRORS_1
SRS_OVERFLOW	48	SRS_OVERFLOW
UPS_OVERFLOW	49	UPS_OVERFLOW
FP_HUGE	50	FP_HUGE
INT_FP_0	51	INT_FP_0
FP_INVALID	52	FP_INVALID
FP_INF	53	FP_INF
PM_REG_ACCESS_FAILURE	55	PM_REG_ACCESS_FAILURE
STREAM_PKT_PARITY_ERROR	56	STREAM_PKT_PARITY_ERROR
CONTROL_PKT_ERROR	57	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	58	AXI_MM_SLAVE_ERROR
INSTR_DECOMPRSN_ERROR	59	INSTR_DECOMPRSN_ERROR
DM_ADDRESS_OUT_OF_RANGE	60	DM_ADDRESS_OUT_OF_RANGE
PM_ECC_ERROR_SCRUB_CORRECTED	61	PM_ECC_ERROR_SCRUB_CORRECTED
PM_ECC_ERROR_SCRUB_2BIT	62	PM_ECC_ERROR_SCRUB_2BIT
PM_ECC_ERROR_1BIT	63	PM_ECC_ERROR_1BIT
PM_ECC_ERROR_2BIT	64	PM_ECC_ERROR_2BIT
PM_ADDRESS_OUT_OF_RANGE	65	PM_ADDRESS_OUT_OF_RANGE
DM_ACCESS_TO_UNAVAILABLE	66	DM_ACCESS_TO_UNAVAILABLE
LOCK_ACCESS_TO_UNAVAILABLE	67	LOCK_ACCESS_TO_UNAVAILABLE
INSTR_WARNING	68	INSTR_WARNING
INSTR_ERROR	69	INSTR_ERROR
DECOMPRESSION_UNDERFLOW	70	DECOMPRESSION_UNDERFLOW
STREAM_SWITCH_PORT_PARITY_ERROR	71	STREAM_SWITCH_PORT_PARITY_ERROR
PROCESSOR_BUS_ERROR	72	PROCESSOR_BUS_ERROR
GROUP_STREAM_SWITCH	73	GROUP_STREAM_SWITCH
PORT_IDLE_0	74	PORT_IDLE_0
PORT_RUNNING_0	75	PORT_RUNNING_0
PORT_STALLED_0	76	PORT_STALLED_0
PORT_TLAST_0	77	PORT_TLAST_0
PORT_IDLE_1	78	PORT_IDLE_1
PORT_RUNNING_1	79	PORT_RUNNING_1
PORT_STALLED_1	80	PORT_STALLED_1
PORT_TLAST_1	81	PORT_TLAST_1
PORT_IDLE_2	82	PORT_IDLE_2
PORT_RUNNING_2	83	PORT_RUNNING_2
PORT_STALLED_2	84	PORT_STALLED_2
PORT_TLAST_2	85	PORT_TLAST_2
PORT_IDLE_3	86	PORT_IDLE_3
PORT_RUNNING_3	87	PORT_RUNNING_3
PORT_STALLED_3	88	PORT_STALLED_3
PORT_TLAST_3	89	PORT_TLAST_3
PORT_IDLE_4	90	PORT_IDLE_4
PORT_RUNNING_4	91	PORT_RUNNING_4
PORT_STALLED_4	92	PORT_STALLED_4
PORT_TLAST_4	93	PORT_TLAST_4
PORT_IDLE_5	94	PORT_IDLE_5
PORT_RUNNING_5	95	PORT_RUNNING_5
PORT_STALLED_5	96	PORT_STALLED_5
PORT_TLAST_5	97	PORT_TLAST_5
PORT_IDLE_6	98	PORT_IDLE_6
PORT_RUNNING_6	99	PORT_RUNNING_6
PORT_STALLED_6	100	PORT_STALLED_6
PORT_TLAST_6	101	PORT_TLAST_6
PORT_IDLE_7	102	PORT_IDLE_7
PORT_RUNNING_7	103	PORT_RUNNING_7
PORT_STALLED_7	104	PORT_STALLED_7
PORT_TLAST_7	105	PORT_TLAST_7
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

CoreEventAIE2P

Core module event enumeration for AIE2P

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
PERF_CNT_2	7	PERF_CNT_2
PERF_CNT_3	8	PERF_CNT_3
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	13	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	14	EDGE_DETECTION_EVENT_1
GROUP_PC_EVENT	15	GROUP_PC_EVENT
PC_0	16	PC_0
PC_1	17	PC_1
PC_2	18	PC_2
PC_3	19	PC_3
PC_RANGE_0_1	20	PC_RANGE_0_1
PC_RANGE_2_3	21	PC_RANGE_2_3
GROUP_STALL	22	GROUP_STALL
MEMORY_STALL	23	MEMORY_STALL
STREAM_STALL	24	STREAM_STALL
CASCADE_STALL	25	CASCADE_STALL
LOCK_STALL	26	LOCK_STALL
DEBUG_HALTED	27	DEBUG_HALTED
ACTIVE	28	ACTIVE
DISABLED	29	DISABLED
ECC_ERROR_STALL	30	ECC_ERROR_STALL
ECC_SCRUBBING_STALL	31	ECC_SCRUBBING_STALL
GROUP_PROGRAM_FLOW	32	GROUP_PROGRAM_FLOW
INSTR_EVENT_0	33	INSTR_EVENT_0
INSTR_EVENT_1	34	INSTR_EVENT_1
INSTR_CALL	35	INSTR_CALL
INSTR_RETURN	36	INSTR_RETURN
INSTR_VECTOR	37	INSTR_VECTOR
INSTR_LOAD	38	INSTR_LOAD
INSTR_STORE	39	INSTR_STORE
INSTR_STREAM_GET	40	INSTR_STREAM_GET
INSTR_STREAM_PUT	41	INSTR_STREAM_PUT
INSTR_CASCADE_GET	42	INSTR_CASCADE_GET
INSTR_CASCADE_PUT	43	INSTR_CASCADE_PUT
INSTR_LOCK_ACQUIRE_REQ	44	INSTR_LOCK_ACQUIRE_REQ
INSTR_LOCK_RELEASE_REQ	45	INSTR_LOCK_RELEASE_REQ
GROUP_ERRORS_0	46	GROUP_ERRORS_0
GROUP_ERRORS_1	47	GROUP_ERRORS_1
SRS_OVERFLOW	48	SRS_OVERFLOW
UPS_OVERFLOW	49	UPS_OVERFLOW
FP_HUGE	50	FP_HUGE
INT_FP_0	51	INT_FP_0
FP_INVALID	52	FP_INVALID
FP_INF	53	FP_INF
PM_REG_ACCESS_FAILURE	55	PM_REG_ACCESS_FAILURE
STREAM_PKT_PARITY_ERROR	56	STREAM_PKT_PARITY_ERROR
CONTROL_PKT_ERROR	57	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	58	AXI_MM_SLAVE_ERROR
INSTR_DECOMPRSN_ERROR	59	INSTR_DECOMPRSN_ERROR
DM_ADDRESS_OUT_OF_RANGE	60	DM_ADDRESS_OUT_OF_RANGE
PM_ECC_ERROR_SCRUB_CORRECTED	61	PM_ECC_ERROR_SCRUB_CORRECTED
PM_ECC_ERROR_SCRUB_2BIT	62	PM_ECC_ERROR_SCRUB_2BIT
PM_ECC_ERROR_1BIT	63	PM_ECC_ERROR_1BIT
PM_ECC_ERROR_2BIT	64	PM_ECC_ERROR_2BIT
PM_ADDRESS_OUT_OF_RANGE	65	PM_ADDRESS_OUT_OF_RANGE
DM_ACCESS_TO_UNAVAILABLE	66	DM_ACCESS_TO_UNAVAILABLE
LOCK_ACCESS_TO_UNAVAILABLE	67	LOCK_ACCESS_TO_UNAVAILABLE
INSTR_WARNING	68	INSTR_WARNING
INSTR_ERROR	69	INSTR_ERROR
SPARSITY_OVERFLOW	70	SPARSITY_OVERFLOW
STREAM_SWITCH_PORT_PARITY_ERROR	71	STREAM_SWITCH_PORT_PARITY_ERROR
PROCESSOR_BUS_ERROR	72	PROCESSOR_BUS_ERROR
GROUP_STREAM_SWITCH	73	GROUP_STREAM_SWITCH
PORT_IDLE_0	74	PORT_IDLE_0
PORT_RUNNING_0	75	PORT_RUNNING_0
PORT_STALLED_0	76	PORT_STALLED_0
PORT_TLAST_0	77	PORT_TLAST_0
PORT_IDLE_1	78	PORT_IDLE_1
PORT_RUNNING_1	79	PORT_RUNNING_1
PORT_STALLED_1	80	PORT_STALLED_1
PORT_TLAST_1	81	PORT_TLAST_1
PORT_IDLE_2	82	PORT_IDLE_2
PORT_RUNNING_2	83	PORT_RUNNING_2
PORT_STALLED_2	84	PORT_STALLED_2
PORT_TLAST_2	85	PORT_TLAST_2
PORT_IDLE_3	86	PORT_IDLE_3
PORT_RUNNING_3	87	PORT_RUNNING_3
PORT_STALLED_3	88	PORT_STALLED_3
PORT_TLAST_3	89	PORT_TLAST_3
PORT_IDLE_4	90	PORT_IDLE_4
PORT_RUNNING_4	91	PORT_RUNNING_4
PORT_STALLED_4	92	PORT_STALLED_4
PORT_TLAST_4	93	PORT_TLAST_4
PORT_IDLE_5	94	PORT_IDLE_5
PORT_RUNNING_5	95	PORT_RUNNING_5
PORT_STALLED_5	96	PORT_STALLED_5
PORT_TLAST_5	97	PORT_TLAST_5
PORT_IDLE_6	98	PORT_IDLE_6
PORT_RUNNING_6	99	PORT_RUNNING_6
PORT_STALLED_6	100	PORT_STALLED_6
PORT_TLAST_6	101	PORT_TLAST_6
PORT_IDLE_7	102	PORT_IDLE_7
PORT_RUNNING_7	103	PORT_RUNNING_7
PORT_STALLED_7	104	PORT_STALLED_7
PORT_TLAST_7	105	PORT_TLAST_7
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

DMAChannelDir

DMA Channel direction

Cases:

Symbol	Value	String
S2MM	0	S2MM
MM2S	1	MM2S

LockAction

Lock acquire/release

Cases:

Symbol	Value	String
Acquire	0	Acquire
AcquireGreaterEqual	2	AcquireGreaterEqual
Release	1	Release

LockBlocking

Lock operation is blocking

Cases:

Symbol	Value	String
NonBlocking	0	NonBlocking
Blocking	1	Blocking

MemEvent

Memory module event enumeration for AIE

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
GROUP_DMA_ACTIVITY	20	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_BD	21	DMA_S2MM_0_START_BD
DMA_S2MM_1_START_BD	22	DMA_S2MM_1_START_BD
DMA_MM2S_0_START_BD	23	DMA_MM2S_0_START_BD
DMA_MM2S_1_START_BD	24	DMA_MM2S_1_START_BD
DMA_S2MM_0_FINISHED_BD	25	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	26	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	27	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	28	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_GO_TO_IDLE	29	DMA_S2MM_0_GO_TO_IDLE
DMA_S2MM_1_GO_TO_IDLE	30	DMA_S2MM_1_GO_TO_IDLE
DMA_MM2S_0_GO_TO_IDLE	31	DMA_MM2S_0_GO_TO_IDLE
DMA_MM2S_1_GO_TO_IDLE	32	DMA_MM2S_1_GO_TO_IDLE
DMA_S2MM_0_STALLED_LOCK_ACQUIRE	33	DMA_S2MM_0_STALLED_LOCK_ACQUIRE
DMA_S2MM_1_STALLED_LOCK_ACQUIRE	34	DMA_S2MM_1_STALLED_LOCK_ACQUIRE
DMA_MM2S_0_STALLED_LOCK_ACQUIRE	35	DMA_MM2S_0_STALLED_LOCK_ACQUIRE
DMA_MM2S_1_STALLED_LOCK_ACQUIRE	36	DMA_MM2S_1_STALLED_LOCK_ACQUIRE
DMA_S2MM_0_MEMORY_CONFLICT	37	DMA_S2MM_0_MEMORY_CONFLICT
DMA_S2MM_1_MEMORY_CONFLICT	38	DMA_S2MM_1_MEMORY_CONFLICT
DMA_MM2S_0_MEMORY_CONFLICT	39	DMA_MM2S_0_MEMORY_CONFLICT
DMA_MM2S_1_MEMORY_CONFLICT	40	DMA_MM2S_1_MEMORY_CONFLICT
GROUP_LOCK	43	GROUP_LOCK
LOCK_0_ACQ	44	LOCK_0_ACQ
LOCK_0_REL	45	LOCK_0_REL
LOCK_1_ACQ	46	LOCK_1_ACQ
LOCK_1_REL	47	LOCK_1_REL
LOCK_2_ACQ	48	LOCK_2_ACQ
LOCK_2_REL	49	LOCK_2_REL
LOCK_3_ACQ	50	LOCK_3_ACQ
LOCK_3_REL	51	LOCK_3_REL
LOCK_4_ACQ	52	LOCK_4_ACQ
LOCK_4_REL	53	LOCK_4_REL
LOCK_5_ACQ	54	LOCK_5_ACQ
LOCK_5_REL	55	LOCK_5_REL
LOCK_6_ACQ	56	LOCK_6_ACQ
LOCK_6_REL	57	LOCK_6_REL
LOCK_7_ACQ	58	LOCK_7_ACQ
LOCK_7_REL	59	LOCK_7_REL
LOCK_8_ACQ	60	LOCK_8_ACQ
LOCK_8_REL	61	LOCK_8_REL
LOCK_9_ACQ	62	LOCK_9_ACQ
LOCK_9_REL	63	LOCK_9_REL
LOCK_10_ACQ	64	LOCK_10_ACQ
LOCK_10_REL	65	LOCK_10_REL
LOCK_11_ACQ	66	LOCK_11_ACQ
LOCK_11_REL	67	LOCK_11_REL
LOCK_12_ACQ	68	LOCK_12_ACQ
LOCK_12_REL	69	LOCK_12_REL
LOCK_13_ACQ	70	LOCK_13_ACQ
LOCK_13_REL	71	LOCK_13_REL
LOCK_14_ACQ	72	LOCK_14_ACQ
LOCK_14_REL	73	LOCK_14_REL
LOCK_15_ACQ	74	LOCK_15_ACQ
LOCK_15_REL	75	LOCK_15_REL
GROUP_MEMORY_CONFLICT	76	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	77	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	78	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	79	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	80	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	81	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	82	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	83	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	84	CONFLICT_DM_BANK_7
GROUP_ERRORS	86	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	87	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	88	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	89	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	90	DM_ECC_ERROR_2BIT
DM_PARITY_ERROR_BANK_2	91	DM_PARITY_ERROR_BANK_2
DM_PARITY_ERROR_BANK_3	92	DM_PARITY_ERROR_BANK_3
DM_PARITY_ERROR_BANK_4	93	DM_PARITY_ERROR_BANK_4
DM_PARITY_ERROR_BANK_5	94	DM_PARITY_ERROR_BANK_5
DM_PARITY_ERROR_BANK_6	95	DM_PARITY_ERROR_BANK_6
DM_PARITY_ERROR_BANK_7	96	DM_PARITY_ERROR_BANK_7
DMA_S2MM_0_ERROR	97	DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR	98	DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR	99	DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR	100	DMA_MM2S_1_ERROR
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

MemEventAIE2

Memory module event enumeration for AIE2

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	11	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	12	EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
GROUP_DMA_ACTIVITY	18	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK	19	DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK	20	DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK	21	DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK	22	DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD	23	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	24	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	25	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	26	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK	27	DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK	28	DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK	29	DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK	30	DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK	31	DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK	32	DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK	33	DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK	34	DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION	35	DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION	36	DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE	37	DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE	38	DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE	39	DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE	40	DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION	41	DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION	42	DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK	43	GROUP_LOCK
LOCK_SEL0_ACQ_EQ	44	LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE	45	LOCK_SEL0_ACQ_GE
LOCK_0_REL	46	LOCK_0_REL
LOCK_SEL0_EQUAL_TO_VALUE	47	LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ	48	LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE	49	LOCK_SEL1_ACQ_GE
LOCK_1_REL	50	LOCK_1_REL
LOCK_SEL1_EQUAL_TO_VALUE	51	LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ	52	LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE	53	LOCK_SEL2_ACQ_GE
LOCK_2_REL	54	LOCK_2_REL
LOCK_SEL2_EQUAL_TO_VALUE	55	LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ	56	LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE	57	LOCK_SEL3_ACQ_GE
LOCK_3_REL	58	LOCK_3_REL
LOCK_SEL3_EQUAL_TO_VALUE	59	LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ	60	LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE	61	LOCK_SEL4_ACQ_GE
LOCK_4_REL	62	LOCK_4_REL
LOCK_SEL4_EQUAL_TO_VALUE	63	LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ	64	LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE	65	LOCK_SEL5_ACQ_GE
LOCK_5_REL	66	LOCK_5_REL
LOCK_SEL5_EQUAL_TO_VALUE	67	LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ	68	LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE	69	LOCK_SEL6_ACQ_GE
LOCK_6_REL	70	LOCK_6_REL
LOCK_SEL6_EQUAL_TO_VALUE	71	LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ	72	LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE	73	LOCK_SEL7_ACQ_GE
LOCK_7_REL	74	LOCK_7_REL
LOCK_SEL7_EQUAL_TO_VALUE	75	LOCK_SEL7_EQUAL_TO_VALUE
GROUP_MEMORY_CONFLICT	76	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	77	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	78	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	79	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	80	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	81	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	82	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	83	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	84	CONFLICT_DM_BANK_7
GROUP_ERRORS	86	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	87	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	88	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	89	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	90	DM_ECC_ERROR_2BIT
DM_PARITY_ERROR_BANK_2	91	DM_PARITY_ERROR_BANK_2
DM_PARITY_ERROR_BANK_3	92	DM_PARITY_ERROR_BANK_3
DM_PARITY_ERROR_BANK_4	93	DM_PARITY_ERROR_BANK_4
DM_PARITY_ERROR_BANK_5	94	DM_PARITY_ERROR_BANK_5
DM_PARITY_ERROR_BANK_6	95	DM_PARITY_ERROR_BANK_6
DM_PARITY_ERROR_BANK_7	96	DM_PARITY_ERROR_BANK_7
DMA_S2MM_0_ERROR	97	DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR	98	DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR	99	DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR	100	DMA_MM2S_1_ERROR
LOCK_ERROR	101	LOCK_ERROR
DMA_TASK_TOKEN_STALL	102	DMA_TASK_TOKEN_STALL
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

MemEventAIE2P

Memory module event enumeration for AIE2P

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	11	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	12	EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
GROUP_DMA_ACTIVITY	18	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK	19	DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK	20	DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK	21	DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK	22	DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD	23	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	24	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	25	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	26	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK	27	DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK	28	DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK	29	DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK	30	DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK	31	DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK	32	DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK	33	DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK	34	DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION	35	DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION	36	DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE	37	DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE	38	DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE	39	DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE	40	DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION	41	DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION	42	DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK	43	GROUP_LOCK
LOCK_SEL0_ACQ_EQ	44	LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE	45	LOCK_SEL0_ACQ_GE
LOCK_0_REL	46	LOCK_0_REL
LOCK_SEL0_EQUAL_TO_VALUE	47	LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ	48	LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE	49	LOCK_SEL1_ACQ_GE
LOCK_1_REL	50	LOCK_1_REL
LOCK_SEL1_EQUAL_TO_VALUE	51	LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ	52	LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE	53	LOCK_SEL2_ACQ_GE
LOCK_2_REL	54	LOCK_2_REL
LOCK_SEL2_EQUAL_TO_VALUE	55	LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ	56	LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE	57	LOCK_SEL3_ACQ_GE
LOCK_3_REL	58	LOCK_3_REL
LOCK_SEL3_EQUAL_TO_VALUE	59	LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ	60	LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE	61	LOCK_SEL4_ACQ_GE
LOCK_4_REL	62	LOCK_4_REL
LOCK_SEL4_EQUAL_TO_VALUE	63	LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ	64	LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE	65	LOCK_SEL5_ACQ_GE
LOCK_5_REL	66	LOCK_5_REL
LOCK_SEL5_EQUAL_TO_VALUE	67	LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ	68	LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE	69	LOCK_SEL6_ACQ_GE
LOCK_6_REL	70	LOCK_6_REL
LOCK_SEL6_EQUAL_TO_VALUE	71	LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ	72	LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE	73	LOCK_SEL7_ACQ_GE
LOCK_7_REL	74	LOCK_7_REL
LOCK_SEL7_EQUAL_TO_VALUE	75	LOCK_SEL7_EQUAL_TO_VALUE
GROUP_MEMORY_CONFLICT	76	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	77	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	78	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	79	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	80	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	81	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	82	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	83	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	84	CONFLICT_DM_BANK_7
GROUP_ERRORS	86	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	87	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	88	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	89	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	90	DM_ECC_ERROR_2BIT
DM_PARITY_ERROR_BANK_2	91	DM_PARITY_ERROR_BANK_2
DM_PARITY_ERROR_BANK_3	92	DM_PARITY_ERROR_BANK_3
DM_PARITY_ERROR_BANK_4	93	DM_PARITY_ERROR_BANK_4
DM_PARITY_ERROR_BANK_5	94	DM_PARITY_ERROR_BANK_5
DM_PARITY_ERROR_BANK_6	95	DM_PARITY_ERROR_BANK_6
DM_PARITY_ERROR_BANK_7	96	DM_PARITY_ERROR_BANK_7
DMA_S2MM_0_ERROR	97	DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR	98	DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR	99	DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR	100	DMA_MM2S_1_ERROR
LOCK_ERROR	101	LOCK_ERROR
DMA_TASK_TOKEN_STALL	102	DMA_TASK_TOKEN_STALL
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

MemTileEvent

Memory tile event enumeration for AIE

Cases:

| Symbol | Value | String | | :—-: | :—: | —— |

MemTileEventAIE2

Memory tile event enumeration for AIE2

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT0_EVENT	5	PERF_CNT0_EVENT
PERF_CNT1_EVENT	6	PERF_CNT1_EVENT
PERF_CNT2_EVENT	7	PERF_CNT2_EVENT
PERF_CNT3_EVENT	8	PERF_CNT3_EVENT
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	13	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	14	EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
WATCHPOINT_2	18	WATCHPOINT_2
WATCHPOINT_3	19	WATCHPOINT_3
GROUP_DMA_ACTIVITY	20	GROUP_DMA_ACTIVITY
DMA_S2MM_SEL0_START_TASK	21	DMA_S2MM_SEL0_START_TASK
DMA_S2MM_SEL1_START_TASK	22	DMA_S2MM_SEL1_START_TASK
DMA_MM2S_SEL0_START_TASK	23	DMA_MM2S_SEL0_START_TASK
DMA_MM2S_SEL1_START_TASK	24	DMA_MM2S_SEL1_START_TASK
DMA_S2MM_SEL0_FINISHED_BD	25	DMA_S2MM_SEL0_FINISHED_BD
DMA_S2MM_SEL1_FINISHED_BD	26	DMA_S2MM_SEL1_FINISHED_BD
DMA_MM2S_SEL0_FINISHED_BD	27	DMA_MM2S_SEL0_FINISHED_BD
DMA_MM2S_SEL1_FINISHED_BD	28	DMA_MM2S_SEL1_FINISHED_BD
DMA_S2MM_SEL0_FINISHED_TASK	29	DMA_S2MM_SEL0_FINISHED_TASK
DMA_S2MM_SEL1_FINISHED_TASK	30	DMA_S2MM_SEL1_FINISHED_TASK
DMA_MM2S_SEL0_FINISHED_TASK	31	DMA_MM2S_SEL0_FINISHED_TASK
DMA_MM2S_SEL1_FINISHED_TASK	32	DMA_MM2S_SEL1_FINISHED_TASK
DMA_S2MM_SEL0_STALLED_LOCK	33	DMA_S2MM_SEL0_STALLED_LOCK
DMA_S2MM_SEL1_STALLED_LOCK	34	DMA_S2MM_SEL1_STALLED_LOCK
DMA_MM2S_SEL0_STALLED_LOCK	35	DMA_MM2S_SEL0_STALLED_LOCK
DMA_MM2S_SEL1_STALLED_LOCK	36	DMA_MM2S_SEL1_STALLED_LOCK
DMA_S2MM_SEL0_STREAM_STARVATION	37	DMA_S2MM_SEL0_STREAM_STARVATION
DMA_S2MM_SEL1_STREAM_STARVATION	38	DMA_S2MM_SEL1_STREAM_STARVATION
DMA_MM2S_SEL0_STREAM_BACKPRESSURE	39	DMA_MM2S_SEL0_STREAM_BACKPRESSURE
DMA_MM2S_SEL1_STREAM_BACKPRESSURE	40	DMA_MM2S_SEL1_STREAM_BACKPRESSURE
DMA_S2MM_SEL0_MEMORY_BACKPRESSURE	41	DMA_S2MM_SEL0_MEMORY_BACKPRESSURE
DMA_S2MM_SEL1_MEMORY_BACKPRESSURE	42	DMA_S2MM_SEL1_MEMORY_BACKPRESSURE
DMA_MM2S_SEL0_MEMORY_STARVATION	43	DMA_MM2S_SEL0_MEMORY_STARVATION
DMA_MM2S_SEL1_MEMORY_STARVATION	44	DMA_MM2S_SEL1_MEMORY_STARVATION
GROUP_LOCK	45	GROUP_LOCK
LOCK_SEL0_ACQ_EQ	46	LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE	47	LOCK_SEL0_ACQ_GE
LOCK_SEL0_REL	48	LOCK_SEL0_REL
LOCK_SEL0_EQUAL_TO_VALUE	49	LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ	50	LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE	51	LOCK_SEL1_ACQ_GE
LOCK_SEL1_REL	52	LOCK_SEL1_REL
LOCK_SEL1_EQUAL_TO_VALUE	53	LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ	54	LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE	55	LOCK_SEL2_ACQ_GE
LOCK_SEL2_REL	56	LOCK_SEL2_REL
LOCK_SEL2_EQUAL_TO_VALUE	57	LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ	58	LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE	59	LOCK_SEL3_ACQ_GE
LOCK_SEL3_REL	60	LOCK_SEL3_REL
LOCK_SEL3_EQUAL_TO_VALUE	61	LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ	62	LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE	63	LOCK_SEL4_ACQ_GE
LOCK_SEL4_REL	64	LOCK_SEL4_REL
LOCK_SEL4_EQUAL_TO_VALUE	65	LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ	66	LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE	67	LOCK_SEL5_ACQ_GE
LOCK_SEL5_REL	68	LOCK_SEL5_REL
LOCK_SEL5_EQUAL_TO_VALUE	69	LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ	70	LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE	71	LOCK_SEL6_ACQ_GE
LOCK_SEL6_REL	72	LOCK_SEL6_REL
LOCK_SEL6_EQUAL_TO_VALUE	73	LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ	74	LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE	75	LOCK_SEL7_ACQ_GE
LOCK_SEL7_REL	76	LOCK_SEL7_REL
LOCK_SEL7_EQUAL_TO_VALUE	77	LOCK_SEL7_EQUAL_TO_VALUE
GROUP_STREAM_SWITCH	78	GROUP_STREAM_SWITCH
PORT_IDLE_0	79	PORT_IDLE_0
PORT_RUNNING_0	80	PORT_RUNNING_0
PORT_STALLED_0	81	PORT_STALLED_0
PORT_TLAST_0	82	PORT_TLAST_0
PORT_IDLE_1	83	PORT_IDLE_1
PORT_RUNNING_1	84	PORT_RUNNING_1
PORT_STALLED_1	85	PORT_STALLED_1
PORT_TLAST_1	86	PORT_TLAST_1
PORT_IDLE_2	87	PORT_IDLE_2
PORT_RUNNING_2	88	PORT_RUNNING_2
PORT_STALLED_2	89	PORT_STALLED_2
PORT_TLAST_2	90	PORT_TLAST_2
PORT_IDLE_3	91	PORT_IDLE_3
PORT_RUNNING_3	92	PORT_RUNNING_3
PORT_STALLED_3	93	PORT_STALLED_3
PORT_TLAST_3	94	PORT_TLAST_3
PORT_IDLE_4	95	PORT_IDLE_4
PORT_RUNNING_4	96	PORT_RUNNING_4
PORT_STALLED_4	97	PORT_STALLED_4
PORT_TLAST_4	98	PORT_TLAST_4
PORT_IDLE_5	99	PORT_IDLE_5
PORT_RUNNING_5	100	PORT_RUNNING_5
PORT_STALLED_5	101	PORT_STALLED_5
PORT_TLAST_5	102	PORT_TLAST_5
PORT_IDLE_6	103	PORT_IDLE_6
PORT_RUNNING_6	104	PORT_RUNNING_6
PORT_STALLED_6	105	PORT_STALLED_6
PORT_TLAST_6	106	PORT_TLAST_6
PORT_IDLE_7	107	PORT_IDLE_7
PORT_RUNNING_7	108	PORT_RUNNING_7
PORT_STALLED_7	109	PORT_STALLED_7
PORT_TLAST_7	110	PORT_TLAST_7
GROUP_MEMORY_CONFLICT	111	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	112	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	113	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	114	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	115	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	116	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	117	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	118	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	119	CONFLICT_DM_BANK_7
CONFLICT_DM_BANK_8	120	CONFLICT_DM_BANK_8
CONFLICT_DM_BANK_9	121	CONFLICT_DM_BANK_9
CONFLICT_DM_BANK_10	122	CONFLICT_DM_BANK_10
CONFLICT_DM_BANK_11	123	CONFLICT_DM_BANK_11
CONFLICT_DM_BANK_12	124	CONFLICT_DM_BANK_12
CONFLICT_DM_BANK_13	125	CONFLICT_DM_BANK_13
CONFLICT_DM_BANK_14	126	CONFLICT_DM_BANK_14
CONFLICT_DM_BANK_15	127	CONFLICT_DM_BANK_15
GROUP_ERRORS	128	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	129	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	130	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	131	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	132	DM_ECC_ERROR_2BIT
DMA_S2MM_ERROR	133	DMA_S2MM_ERROR
DMA_MM2S_ERROR	134	DMA_MM2S_ERROR
STREAM_SWITCH_PARITY_ERROR	135	STREAM_SWITCH_PARITY_ERROR
STREAM_PKT_ERROR	136	STREAM_PKT_ERROR
CONTROL_PKT_ERROR	137	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	138	AXI_MM_SLAVE_ERROR
LOCK_ERROR	139	LOCK_ERROR
DMA_TASK_TOKEN_STALL	140	DMA_TASK_TOKEN_STALL
GROUP_BROADCAST	141	GROUP_BROADCAST
BROADCAST_0	142	BROADCAST_0
BROADCAST_1	143	BROADCAST_1
BROADCAST_2	144	BROADCAST_2
BROADCAST_3	145	BROADCAST_3
BROADCAST_4	146	BROADCAST_4
BROADCAST_5	147	BROADCAST_5
BROADCAST_6	148	BROADCAST_6
BROADCAST_7	149	BROADCAST_7
BROADCAST_8	150	BROADCAST_8
BROADCAST_9	151	BROADCAST_9
BROADCAST_10	152	BROADCAST_10
BROADCAST_11	153	BROADCAST_11
BROADCAST_12	154	BROADCAST_12
BROADCAST_13	155	BROADCAST_13
BROADCAST_14	156	BROADCAST_14
BROADCAST_15	157	BROADCAST_15
GROUP_USER_EVENT	158	GROUP_USER_EVENT
USER_EVENT_0	159	USER_EVENT_0
USER_EVENT_1	160	USER_EVENT_1

MemTileEventAIE2P

Memory tile event enumeration for AIE2P

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT0_EVENT	5	PERF_CNT0_EVENT
PERF_CNT1_EVENT	6	PERF_CNT1_EVENT
PERF_CNT2_EVENT	7	PERF_CNT2_EVENT
PERF_CNT3_EVENT	8	PERF_CNT3_EVENT
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	13	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	14	EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
WATCHPOINT_2	18	WATCHPOINT_2
WATCHPOINT_3	19	WATCHPOINT_3
GROUP_DMA_ACTIVITY	20	GROUP_DMA_ACTIVITY
DMA_S2MM_SEL0_START_TASK	21	DMA_S2MM_SEL0_START_TASK
DMA_S2MM_SEL1_START_TASK	22	DMA_S2MM_SEL1_START_TASK
DMA_MM2S_SEL0_START_TASK	23	DMA_MM2S_SEL0_START_TASK
DMA_MM2S_SEL1_START_TASK	24	DMA_MM2S_SEL1_START_TASK
DMA_S2MM_SEL0_FINISHED_BD	25	DMA_S2MM_SEL0_FINISHED_BD
DMA_S2MM_SEL1_FINISHED_BD	26	DMA_S2MM_SEL1_FINISHED_BD
DMA_MM2S_SEL0_FINISHED_BD	27	DMA_MM2S_SEL0_FINISHED_BD
DMA_MM2S_SEL1_FINISHED_BD	28	DMA_MM2S_SEL1_FINISHED_BD
DMA_S2MM_SEL0_FINISHED_TASK	29	DMA_S2MM_SEL0_FINISHED_TASK
DMA_S2MM_SEL1_FINISHED_TASK	30	DMA_S2MM_SEL1_FINISHED_TASK
DMA_MM2S_SEL0_FINISHED_TASK	31	DMA_MM2S_SEL0_FINISHED_TASK
DMA_MM2S_SEL1_FINISHED_TASK	32	DMA_MM2S_SEL1_FINISHED_TASK
DMA_S2MM_SEL0_STALLED_LOCK	33	DMA_S2MM_SEL0_STALLED_LOCK
DMA_S2MM_SEL1_STALLED_LOCK	34	DMA_S2MM_SEL1_STALLED_LOCK
DMA_MM2S_SEL0_STALLED_LOCK	35	DMA_MM2S_SEL0_STALLED_LOCK
DMA_MM2S_SEL1_STALLED_LOCK	36	DMA_MM2S_SEL1_STALLED_LOCK
DMA_S2MM_SEL0_STREAM_STARVATION	37	DMA_S2MM_SEL0_STREAM_STARVATION
DMA_S2MM_SEL1_STREAM_STARVATION	38	DMA_S2MM_SEL1_STREAM_STARVATION
DMA_MM2S_SEL0_STREAM_BACKPRESSURE	39	DMA_MM2S_SEL0_STREAM_BACKPRESSURE
DMA_MM2S_SEL1_STREAM_BACKPRESSURE	40	DMA_MM2S_SEL1_STREAM_BACKPRESSURE
DMA_S2MM_SEL0_MEMORY_BACKPRESSURE	41	DMA_S2MM_SEL0_MEMORY_BACKPRESSURE
DMA_S2MM_SEL1_MEMORY_BACKPRESSURE	42	DMA_S2MM_SEL1_MEMORY_BACKPRESSURE
DMA_MM2S_SEL0_MEMORY_STARVATION	43	DMA_MM2S_SEL0_MEMORY_STARVATION
DMA_MM2S_SEL1_MEMORY_STARVATION	44	DMA_MM2S_SEL1_MEMORY_STARVATION
GROUP_LOCK	45	GROUP_LOCK
LOCK_SEL0_ACQ_EQ	46	LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE	47	LOCK_SEL0_ACQ_GE
LOCK_SEL0_REL	48	LOCK_SEL0_REL
LOCK_SEL0_EQUAL_TO_VALUE	49	LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ	50	LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE	51	LOCK_SEL1_ACQ_GE
LOCK_SEL1_REL	52	LOCK_SEL1_REL
LOCK_SEL1_EQUAL_TO_VALUE	53	LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ	54	LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE	55	LOCK_SEL2_ACQ_GE
LOCK_SEL2_REL	56	LOCK_SEL2_REL
LOCK_SEL2_EQUAL_TO_VALUE	57	LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ	58	LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE	59	LOCK_SEL3_ACQ_GE
LOCK_SEL3_REL	60	LOCK_SEL3_REL
LOCK_SEL3_EQUAL_TO_VALUE	61	LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ	62	LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE	63	LOCK_SEL4_ACQ_GE
LOCK_SEL4_REL	64	LOCK_SEL4_REL
LOCK_SEL4_EQUAL_TO_VALUE	65	LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ	66	LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE	67	LOCK_SEL5_ACQ_GE
LOCK_SEL5_REL	68	LOCK_SEL5_REL
LOCK_SEL5_EQUAL_TO_VALUE	69	LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ	70	LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE	71	LOCK_SEL6_ACQ_GE
LOCK_SEL6_REL	72	LOCK_SEL6_REL
LOCK_SEL6_EQUAL_TO_VALUE	73	LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ	74	LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE	75	LOCK_SEL7_ACQ_GE
LOCK_SEL7_REL	76	LOCK_SEL7_REL
LOCK_SEL7_EQUAL_TO_VALUE	77	LOCK_SEL7_EQUAL_TO_VALUE
GROUP_STREAM_SWITCH	78	GROUP_STREAM_SWITCH
PORT_IDLE_0	79	PORT_IDLE_0
PORT_RUNNING_0	80	PORT_RUNNING_0
PORT_STALLED_0	81	PORT_STALLED_0
PORT_TLAST_0	82	PORT_TLAST_0
PORT_IDLE_1	83	PORT_IDLE_1
PORT_RUNNING_1	84	PORT_RUNNING_1
PORT_STALLED_1	85	PORT_STALLED_1
PORT_TLAST_1	86	PORT_TLAST_1
PORT_IDLE_2	87	PORT_IDLE_2
PORT_RUNNING_2	88	PORT_RUNNING_2
PORT_STALLED_2	89	PORT_STALLED_2
PORT_TLAST_2	90	PORT_TLAST_2
PORT_IDLE_3	91	PORT_IDLE_3
PORT_RUNNING_3	92	PORT_RUNNING_3
PORT_STALLED_3	93	PORT_STALLED_3
PORT_TLAST_3	94	PORT_TLAST_3
PORT_IDLE_4	95	PORT_IDLE_4
PORT_RUNNING_4	96	PORT_RUNNING_4
PORT_STALLED_4	97	PORT_STALLED_4
PORT_TLAST_4	98	PORT_TLAST_4
PORT_IDLE_5	99	PORT_IDLE_5
PORT_RUNNING_5	100	PORT_RUNNING_5
PORT_STALLED_5	101	PORT_STALLED_5
PORT_TLAST_5	102	PORT_TLAST_5
PORT_IDLE_6	103	PORT_IDLE_6
PORT_RUNNING_6	104	PORT_RUNNING_6
PORT_STALLED_6	105	PORT_STALLED_6
PORT_TLAST_6	106	PORT_TLAST_6
PORT_IDLE_7	107	PORT_IDLE_7
PORT_RUNNING_7	108	PORT_RUNNING_7
PORT_STALLED_7	109	PORT_STALLED_7
PORT_TLAST_7	110	PORT_TLAST_7
GROUP_MEMORY_CONFLICT	111	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	112	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	113	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	114	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	115	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	116	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	117	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	118	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	119	CONFLICT_DM_BANK_7
CONFLICT_DM_BANK_8	120	CONFLICT_DM_BANK_8
CONFLICT_DM_BANK_9	121	CONFLICT_DM_BANK_9
CONFLICT_DM_BANK_10	122	CONFLICT_DM_BANK_10
CONFLICT_DM_BANK_11	123	CONFLICT_DM_BANK_11
CONFLICT_DM_BANK_12	124	CONFLICT_DM_BANK_12
CONFLICT_DM_BANK_13	125	CONFLICT_DM_BANK_13
CONFLICT_DM_BANK_14	126	CONFLICT_DM_BANK_14
CONFLICT_DM_BANK_15	127	CONFLICT_DM_BANK_15
GROUP_ERRORS	128	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	129	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	130	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	131	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	132	DM_ECC_ERROR_2BIT
DMA_S2MM_ERROR	133	DMA_S2MM_ERROR
DMA_MM2S_ERROR	134	DMA_MM2S_ERROR
STREAM_SWITCH_PARITY_ERROR	135	STREAM_SWITCH_PARITY_ERROR
STREAM_PKT_ERROR	136	STREAM_PKT_ERROR
CONTROL_PKT_ERROR	137	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	138	AXI_MM_SLAVE_ERROR
LOCK_ERROR	139	LOCK_ERROR
DMA_TASK_TOKEN_STALL	140	DMA_TASK_TOKEN_STALL
GROUP_BROADCAST	141	GROUP_BROADCAST
BROADCAST_0	142	BROADCAST_0
BROADCAST_1	143	BROADCAST_1
BROADCAST_2	144	BROADCAST_2
BROADCAST_3	145	BROADCAST_3
BROADCAST_4	146	BROADCAST_4
BROADCAST_5	147	BROADCAST_5
BROADCAST_6	148	BROADCAST_6
BROADCAST_7	149	BROADCAST_7
BROADCAST_8	150	BROADCAST_8
BROADCAST_9	151	BROADCAST_9
BROADCAST_10	152	BROADCAST_10
BROADCAST_11	153	BROADCAST_11
BROADCAST_12	154	BROADCAST_12
BROADCAST_13	155	BROADCAST_13
BROADCAST_14	156	BROADCAST_14
BROADCAST_15	157	BROADCAST_15
GROUP_USER_EVENT	158	GROUP_USER_EVENT
USER_EVENT_0	159	USER_EVENT_0
USER_EVENT_1	160	USER_EVENT_1

ObjectFifoPort

Ports of an object FIFO

Cases:

Symbol	Value	String
Produce	0	Produce
Consume	1	Consume

ShimTileEvent

Shim tile event enumeration for AIE

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
GROUP_DMA_ACTIVITY	11	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_BD	12	DMA_S2MM_0_START_BD
DMA_S2MM_1_START_BD	13	DMA_S2MM_1_START_BD
DMA_MM2S_0_START_BD	14	DMA_MM2S_0_START_BD
DMA_MM2S_1_START_BD	15	DMA_MM2S_1_START_BD
DMA_S2MM_0_FINISHED_BD	16	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	17	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	18	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	19	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_GO_TO_IDLE	20	DMA_S2MM_0_GO_TO_IDLE
DMA_S2MM_1_GO_TO_IDLE	21	DMA_S2MM_1_GO_TO_IDLE
DMA_MM2S_0_GO_TO_IDLE	22	DMA_MM2S_0_GO_TO_IDLE
DMA_MM2S_1_GO_TO_IDLE	23	DMA_MM2S_1_GO_TO_IDLE
DMA_S2MM_0_STALLED_LOCK_ACQUIRE	24	DMA_S2MM_0_STALLED_LOCK_ACQUIRE
DMA_S2MM_1_STALLED_LOCK_ACQUIRE	25	DMA_S2MM_1_STALLED_LOCK_ACQUIRE
DMA_MM2S_0_STALLED_LOCK_ACQUIRE	26	DMA_MM2S_0_STALLED_LOCK_ACQUIRE
DMA_MM2S_1_STALLED_LOCK_ACQUIRE	27	DMA_MM2S_1_STALLED_LOCK_ACQUIRE
GROUP_LOCK	28	GROUP_LOCK
LOCK_0_ACQUIRED	29	LOCK_0_ACQUIRED
LOCK_0_RELEASED	30	LOCK_0_RELEASED
LOCK_1_ACQUIRED	31	LOCK_1_ACQUIRED
LOCK_1_RELEASED	32	LOCK_1_RELEASED
LOCK_2_ACQUIRED	33	LOCK_2_ACQUIRED
LOCK_2_RELEASED	34	LOCK_2_RELEASED
LOCK_3_ACQUIRED	35	LOCK_3_ACQUIRED
LOCK_3_RELEASED	36	LOCK_3_RELEASED
LOCK_4_ACQUIRED	37	LOCK_4_ACQUIRED
LOCK_4_RELEASED	38	LOCK_4_RELEASED
LOCK_5_ACQUIRED	39	LOCK_5_ACQUIRED
LOCK_5_RELEASED	40	LOCK_5_RELEASED
LOCK_6_ACQUIRED	41	LOCK_6_ACQUIRED
LOCK_6_RELEASED	42	LOCK_6_RELEASED
LOCK_7_ACQUIRED	43	LOCK_7_ACQUIRED
LOCK_7_RELEASED	44	LOCK_7_RELEASED
LOCK_8_ACQUIRED	45	LOCK_8_ACQUIRED
LOCK_8_RELEASED	46	LOCK_8_RELEASED
LOCK_9_ACQUIRED	47	LOCK_9_ACQUIRED
LOCK_9_RELEASED	48	LOCK_9_RELEASED
LOCK_10_ACQUIRED	49	LOCK_10_ACQUIRED
LOCK_10_RELEASED	50	LOCK_10_RELEASED
LOCK_11_ACQUIRED	51	LOCK_11_ACQUIRED
LOCK_11_RELEASED	52	LOCK_11_RELEASED
LOCK_12_ACQUIRED	53	LOCK_12_ACQUIRED
LOCK_12_RELEASED	54	LOCK_12_RELEASED
LOCK_13_ACQUIRED	55	LOCK_13_ACQUIRED
LOCK_13_RELEASED	56	LOCK_13_RELEASED
LOCK_14_ACQUIRED	57	LOCK_14_ACQUIRED
LOCK_14_RELEASED	58	LOCK_14_RELEASED
LOCK_15_ACQUIRED	59	LOCK_15_ACQUIRED
LOCK_15_RELEASED	60	LOCK_15_RELEASED
GROUP_ERRORS	61	GROUP_ERRORS
AXI_MM_SLAVE_TILE_ERROR	62	AXI_MM_SLAVE_TILE_ERROR
CONTROL_PKT_ERROR	63	CONTROL_PKT_ERROR
AXI_MM_DECODE_NSU_ERROR	64	AXI_MM_DECODE_NSU_ERROR
AXI_MM_SLAVE_NSU_ERROR	65	AXI_MM_SLAVE_NSU_ERROR
AXI_MM_UNSUPPORTED_TRAFFIC	66	AXI_MM_UNSUPPORTED_TRAFFIC
AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE	67	AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE
AXI_MM_BYTE_STROBE_ERROR	68	AXI_MM_BYTE_STROBE_ERROR
DMA_S2MM_0_ERROR	69	DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR	70	DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR	71	DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR	72	DMA_MM2S_1_ERROR
GROUP_STREAM_SWITCH	73	GROUP_STREAM_SWITCH
PORT_IDLE_0	74	PORT_IDLE_0
PORT_RUNNING_0	75	PORT_RUNNING_0
PORT_STALLED_0	76	PORT_STALLED_0
PORT_TLAST_0	77	PORT_TLAST_0
PORT_IDLE_1	78	PORT_IDLE_1
PORT_RUNNING_1	79	PORT_RUNNING_1
PORT_STALLED_1	80	PORT_STALLED_1
PORT_TLAST_1	81	PORT_TLAST_1
PORT_IDLE_2	82	PORT_IDLE_2
PORT_RUNNING_2	83	PORT_RUNNING_2
PORT_STALLED_2	84	PORT_STALLED_2
PORT_TLAST_2	85	PORT_TLAST_2
PORT_IDLE_3	86	PORT_IDLE_3
PORT_RUNNING_3	87	PORT_RUNNING_3
PORT_STALLED_3	88	PORT_STALLED_3
PORT_TLAST_3	89	PORT_TLAST_3
PORT_IDLE_4	90	PORT_IDLE_4
PORT_RUNNING_4	91	PORT_RUNNING_4
PORT_STALLED_4	92	PORT_STALLED_4
PORT_TLAST_4	93	PORT_TLAST_4
PORT_IDLE_5	94	PORT_IDLE_5
PORT_RUNNING_5	95	PORT_RUNNING_5
PORT_STALLED_5	96	PORT_STALLED_5
PORT_TLAST_5	97	PORT_TLAST_5
PORT_IDLE_6	98	PORT_IDLE_6
PORT_RUNNING_6	99	PORT_RUNNING_6
PORT_STALLED_6	100	PORT_STALLED_6
PORT_TLAST_6	101	PORT_TLAST_6
PORT_IDLE_7	102	PORT_IDLE_7
PORT_RUNNING_7	103	PORT_RUNNING_7
PORT_STALLED_7	104	PORT_STALLED_7
PORT_TLAST_7	105	PORT_TLAST_7
GROUP_BROADCAST_A	106	GROUP_BROADCAST_A
BROADCAST_A_0	107	BROADCAST_A_0
BROADCAST_A_1	108	BROADCAST_A_1
BROADCAST_A_2	109	BROADCAST_A_2
BROADCAST_A_3	110	BROADCAST_A_3
BROADCAST_A_4	111	BROADCAST_A_4
BROADCAST_A_5	112	BROADCAST_A_5
BROADCAST_A_6	113	BROADCAST_A_6
BROADCAST_A_7	114	BROADCAST_A_7
BROADCAST_A_8	115	BROADCAST_A_8
BROADCAST_A_9	116	BROADCAST_A_9
BROADCAST_A_10	117	BROADCAST_A_10
BROADCAST_A_11	118	BROADCAST_A_11
BROADCAST_A_12	119	BROADCAST_A_12
BROADCAST_A_13	120	BROADCAST_A_13
BROADCAST_A_14	121	BROADCAST_A_14
BROADCAST_A_15	122	BROADCAST_A_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

ShimTileEventAIE2

Shim tile event enumeration for AIE2

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	11	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	12	EDGE_DETECTION_EVENT_1
GROUP_DMA_ACTIVITY	13	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK	14	DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK	15	DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK	16	DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK	17	DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD	18	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	19	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	20	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	21	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK	22	DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK	23	DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK	24	DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK	25	DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK	26	DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK	27	DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK	28	DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK	29	DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION	30	DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION	31	DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE	32	DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE	33	DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE	34	DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE	35	DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION	36	DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION	37	DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK	38	GROUP_LOCK
LOCK_0_ACQ_EQ	39	LOCK_0_ACQ_EQ
LOCK_0_ACQ_GE	40	LOCK_0_ACQ_GE
LOCK_0_REL	41	LOCK_0_REL
LOCK_0_EQUAL_TO_VALUE	42	LOCK_0_EQUAL_TO_VALUE
LOCK_1_ACQ_EQ	43	LOCK_1_ACQ_EQ
LOCK_1_ACQ_GE	44	LOCK_1_ACQ_GE
LOCK_1_REL	45	LOCK_1_REL
LOCK_1_EQUAL_TO_VALUE	46	LOCK_1_EQUAL_TO_VALUE
LOCK_2_ACQ_EQ	47	LOCK_2_ACQ_EQ
LOCK_2_ACQ_GE	48	LOCK_2_ACQ_GE
LOCK_2_REL	49	LOCK_2_REL
LOCK_2_EQUAL_TO_VALUE	50	LOCK_2_EQUAL_TO_VALUE
LOCK_3_ACQ_EQ	51	LOCK_3_ACQ_EQ
LOCK_3_ACQ_GE	52	LOCK_3_ACQ_GE
LOCK_3_REL	53	LOCK_3_REL
LOCK_3_EQUAL_TO_VALUE	54	LOCK_3_EQUAL_TO_VALUE
LOCK_4_ACQ_EQ	55	LOCK_4_ACQ_EQ
LOCK_4_ACQ_GE	56	LOCK_4_ACQ_GE
LOCK_4_REL	57	LOCK_4_REL
LOCK_4_EQUAL_TO_VALUE	58	LOCK_4_EQUAL_TO_VALUE
LOCK_5_ACQ_EQ	59	LOCK_5_ACQ_EQ
LOCK_5_ACQ_GE	60	LOCK_5_ACQ_GE
LOCK_5_REL	61	LOCK_5_REL
LOCK_5_EQUAL_TO_VALUE	62	LOCK_5_EQUAL_TO_VALUE
GROUP_ERRORS	63	GROUP_ERRORS
AXI_MM_SLAVE_ERROR	64	AXI_MM_SLAVE_ERROR
CONTROL_PKT_ERROR	65	CONTROL_PKT_ERROR
STREAM_SWITCH_PARITY_ERROR	66	STREAM_SWITCH_PARITY_ERROR
AXI_MM_DECODE_NSU_ERROR	67	AXI_MM_DECODE_NSU_ERROR
AXI_MM_SLAVE_NSU_ERROR	68	AXI_MM_SLAVE_NSU_ERROR
AXI_MM_UNSUPPORTED_TRAFFIC	69	AXI_MM_UNSUPPORTED_TRAFFIC
AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE	70	AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE
AXI_MM_BYTE_STROBE_ERROR	71	AXI_MM_BYTE_STROBE_ERROR
DMA_S2MM_ERROR	72	DMA_S2MM_ERROR
DMA_MM2S_ERROR	73	DMA_MM2S_ERROR
LOCK_ERROR	74	LOCK_ERROR
DMA_TASK_TOKEN_STALL	75	DMA_TASK_TOKEN_STALL
GROUP_STREAM_SWITCH	76	GROUP_STREAM_SWITCH
PORT_IDLE_0	77	PORT_IDLE_0
PORT_RUNNING_0	78	PORT_RUNNING_0
PORT_STALLED_0	79	PORT_STALLED_0
PORT_TLAST_0	80	PORT_TLAST_0
PORT_IDLE_1	81	PORT_IDLE_1
PORT_RUNNING_1	82	PORT_RUNNING_1
PORT_STALLED_1	83	PORT_STALLED_1
PORT_TLAST_1	84	PORT_TLAST_1
PORT_IDLE_2	85	PORT_IDLE_2
PORT_RUNNING_2	86	PORT_RUNNING_2
PORT_STALLED_2	87	PORT_STALLED_2
PORT_TLAST_2	88	PORT_TLAST_2
PORT_IDLE_3	89	PORT_IDLE_3
PORT_RUNNING_3	90	PORT_RUNNING_3
PORT_STALLED_3	91	PORT_STALLED_3
PORT_TLAST_3	92	PORT_TLAST_3
PORT_IDLE_4	93	PORT_IDLE_4
PORT_RUNNING_4	94	PORT_RUNNING_4
PORT_STALLED_4	95	PORT_STALLED_4
PORT_TLAST_4	96	PORT_TLAST_4
PORT_IDLE_5	97	PORT_IDLE_5
PORT_RUNNING_5	98	PORT_RUNNING_5
PORT_STALLED_5	99	PORT_STALLED_5
PORT_TLAST_5	100	PORT_TLAST_5
PORT_IDLE_6	101	PORT_IDLE_6
PORT_RUNNING_6	102	PORT_RUNNING_6
PORT_STALLED_6	103	PORT_STALLED_6
PORT_TLAST_6	104	PORT_TLAST_6
PORT_IDLE_7	105	PORT_IDLE_7
PORT_RUNNING_7	106	PORT_RUNNING_7
PORT_STALLED_7	107	PORT_STALLED_7
PORT_TLAST_7	108	PORT_TLAST_7
GROUP_BROADCAST_A	109	GROUP_BROADCAST_A
BROADCAST_A_0	110	BROADCAST_A_0
BROADCAST_A_1	111	BROADCAST_A_1
BROADCAST_A_2	112	BROADCAST_A_2
BROADCAST_A_3	113	BROADCAST_A_3
BROADCAST_A_4	114	BROADCAST_A_4
BROADCAST_A_5	115	BROADCAST_A_5
BROADCAST_A_6	116	BROADCAST_A_6
BROADCAST_A_7	117	BROADCAST_A_7
BROADCAST_A_8	118	BROADCAST_A_8
BROADCAST_A_9	119	BROADCAST_A_9
BROADCAST_A_10	120	BROADCAST_A_10
BROADCAST_A_11	121	BROADCAST_A_11
BROADCAST_A_12	122	BROADCAST_A_12
BROADCAST_A_13	123	BROADCAST_A_13
BROADCAST_A_14	124	BROADCAST_A_14
BROADCAST_A_15	125	BROADCAST_A_15
USER_EVENT_0	126	USER_EVENT_0
USER_EVENT_1	127	USER_EVENT_1

ShimTileEventAIE2P

Shim tile event enumeration for AIE2P

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	11	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	12	EDGE_DETECTION_EVENT_1
GROUP_DMA_ACTIVITY	13	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK	14	DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK	15	DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK	16	DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK	17	DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD	18	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	19	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	20	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	21	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK	22	DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK	23	DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK	24	DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK	25	DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK	26	DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK	27	DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK	28	DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK	29	DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION	30	DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION	31	DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE	32	DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE	33	DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE	34	DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE	35	DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION	36	DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION	37	DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK	38	GROUP_LOCK
LOCK_0_ACQ_EQ	39	LOCK_0_ACQ_EQ
LOCK_0_ACQ_GE	40	LOCK_0_ACQ_GE
LOCK_0_REL	41	LOCK_0_REL
LOCK_0_EQUAL_TO_VALUE	42	LOCK_0_EQUAL_TO_VALUE
LOCK_1_ACQ_EQ	43	LOCK_1_ACQ_EQ
LOCK_1_ACQ_GE	44	LOCK_1_ACQ_GE
LOCK_1_REL	45	LOCK_1_REL
LOCK_1_EQUAL_TO_VALUE	46	LOCK_1_EQUAL_TO_VALUE
LOCK_2_ACQ_EQ	47	LOCK_2_ACQ_EQ
LOCK_2_ACQ_GE	48	LOCK_2_ACQ_GE
LOCK_2_REL	49	LOCK_2_REL
LOCK_2_EQUAL_TO_VALUE	50	LOCK_2_EQUAL_TO_VALUE
LOCK_3_ACQ_EQ	51	LOCK_3_ACQ_EQ
LOCK_3_ACQ_GE	52	LOCK_3_ACQ_GE
LOCK_3_REL	53	LOCK_3_REL
LOCK_3_EQUAL_TO_VALUE	54	LOCK_3_EQUAL_TO_VALUE
LOCK_4_ACQ_EQ	55	LOCK_4_ACQ_EQ
LOCK_4_ACQ_GE	56	LOCK_4_ACQ_GE
LOCK_4_REL	57	LOCK_4_REL
LOCK_4_EQUAL_TO_VALUE	58	LOCK_4_EQUAL_TO_VALUE
LOCK_5_ACQ_EQ	59	LOCK_5_ACQ_EQ
LOCK_5_ACQ_GE	60	LOCK_5_ACQ_GE
LOCK_5_REL	61	LOCK_5_REL
LOCK_5_EQUAL_TO_VALUE	62	LOCK_5_EQUAL_TO_VALUE
GROUP_ERRORS	63	GROUP_ERRORS
AXI_MM_SLAVE_ERROR	64	AXI_MM_SLAVE_ERROR
CONTROL_PKT_ERROR	65	CONTROL_PKT_ERROR
STREAM_SWITCH_PARITY_ERROR	66	STREAM_SWITCH_PARITY_ERROR
AXI_MM_DECODE_NSU_ERROR	67	AXI_MM_DECODE_NSU_ERROR
AXI_MM_SLAVE_NSU_ERROR	68	AXI_MM_SLAVE_NSU_ERROR
AXI_MM_UNSUPPORTED_TRAFFIC	69	AXI_MM_UNSUPPORTED_TRAFFIC
AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE	70	AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE
AXI_MM_BYTE_STROBE_ERROR	71	AXI_MM_BYTE_STROBE_ERROR
DMA_S2MM_ERROR	72	DMA_S2MM_ERROR
DMA_MM2S_ERROR	73	DMA_MM2S_ERROR
LOCK_ERROR	74	LOCK_ERROR
DMA_TASK_TOKEN_STALL	75	DMA_TASK_TOKEN_STALL
GROUP_STREAM_SWITCH	76	GROUP_STREAM_SWITCH
PORT_IDLE_0	77	PORT_IDLE_0
PORT_RUNNING_0	78	PORT_RUNNING_0
PORT_STALLED_0	79	PORT_STALLED_0
PORT_TLAST_0	80	PORT_TLAST_0
PORT_IDLE_1	81	PORT_IDLE_1
PORT_RUNNING_1	82	PORT_RUNNING_1
PORT_STALLED_1	83	PORT_STALLED_1
PORT_TLAST_1	84	PORT_TLAST_1
PORT_IDLE_2	85	PORT_IDLE_2
PORT_RUNNING_2	86	PORT_RUNNING_2
PORT_STALLED_2	87	PORT_STALLED_2
PORT_TLAST_2	88	PORT_TLAST_2
PORT_IDLE_3	89	PORT_IDLE_3
PORT_RUNNING_3	90	PORT_RUNNING_3
PORT_STALLED_3	91	PORT_STALLED_3
PORT_TLAST_3	92	PORT_TLAST_3
PORT_IDLE_4	93	PORT_IDLE_4
PORT_RUNNING_4	94	PORT_RUNNING_4
PORT_STALLED_4	95	PORT_STALLED_4
PORT_TLAST_4	96	PORT_TLAST_4
PORT_IDLE_5	97	PORT_IDLE_5
PORT_RUNNING_5	98	PORT_RUNNING_5
PORT_STALLED_5	99	PORT_STALLED_5
PORT_TLAST_5	100	PORT_TLAST_5
PORT_IDLE_6	101	PORT_IDLE_6
PORT_RUNNING_6	102	PORT_RUNNING_6
PORT_STALLED_6	103	PORT_STALLED_6
PORT_TLAST_6	104	PORT_TLAST_6
PORT_IDLE_7	105	PORT_IDLE_7
PORT_RUNNING_7	106	PORT_RUNNING_7
PORT_STALLED_7	107	PORT_STALLED_7
PORT_TLAST_7	108	PORT_TLAST_7
GROUP_BROADCAST_A	109	GROUP_BROADCAST_A
BROADCAST_A_0	110	BROADCAST_A_0
BROADCAST_A_1	111	BROADCAST_A_1
BROADCAST_A_2	112	BROADCAST_A_2
BROADCAST_A_3	113	BROADCAST_A_3
BROADCAST_A_4	114	BROADCAST_A_4
BROADCAST_A_5	115	BROADCAST_A_5
BROADCAST_A_6	116	BROADCAST_A_6
BROADCAST_A_7	117	BROADCAST_A_7
BROADCAST_A_8	118	BROADCAST_A_8
BROADCAST_A_9	119	BROADCAST_A_9
BROADCAST_A_10	120	BROADCAST_A_10
BROADCAST_A_11	121	BROADCAST_A_11
BROADCAST_A_12	122	BROADCAST_A_12
BROADCAST_A_13	123	BROADCAST_A_13
BROADCAST_A_14	124	BROADCAST_A_14
BROADCAST_A_15	125	BROADCAST_A_15
USER_EVENT_0	126	USER_EVENT_0
USER_EVENT_1	127	USER_EVENT_1

WireBundle

Bundle of wires

Cases:

Symbol	Value	String
Core	0	Core
DMA	1	DMA
FIFO	2	FIFO
South	3	South
West	4	West
North	5	North
East	6	East
PLIO	7	PLIO
NOC	8	NOC
Trace	9	Trace
TileControl	10	TileControl