‘aievec’ Dialect

Types and operations for AIE vector dialect

[TOC]

Operations

aievec.add_elem (::xilinx::aievec::AddElemOp)

AIE vector add elem

Syntax:

operation ::= `aievec.add_elem` $lhs `,` $rhs attr-dict `:` type($result)

AMD-specific AIE2 intrinsic that allows you to perform addition operation on all types of vectors.$result = $lhs + $rhs`.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.band (::xilinx::aievec::BandOp)

AIE vector bitwise and

Syntax:

operation ::= `aievec.band` $lhs `,` $rhs attr-dict `:` type($lhs) `,` type($rhs)
              `,` type($result)

AMD-specific intrinsic that computes bitwise and of two vectors and returns the result. $result = band($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type
rhs	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

Results:

Result	Description
result	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

aievec.bneg (::xilinx::aievec::BnegOp)

AIE vector bitwise negation

Syntax:

operation ::= `aievec.bneg` $source attr-dict `:` type($result)

AMD-specific intrinsic that computes bitwise negation of a vector and returns the result. $result = bneg($source`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
source	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

Results:

Result	Description
result	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

aievec.bor (::xilinx::aievec::BorOp)

AIE vector bitwise or

Syntax:

operation ::= `aievec.bor` $lhs `,` $rhs attr-dict `:` type($lhs) `,` type($rhs)
              `,` type($result)

AMD-specific intrinsic that computes bitwise or of two vectors and returns the result. $result = bor($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type
rhs	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

Results:

Result	Description
result	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

aievec.broadcast (::xilinx::aievec::BroadcastOp)

AIE2 broadcast

AMD-specific broadcast intrinsic. Extract element index from vector and broadcasts its value to all lanes of the vector. $result = broadcast($source, $idx)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
idx	::mlir::IntegerAttr	8-bit signless integer attribute whose value is non-negative

Operands:

Operand	Description
source	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.broadcast_scalar (::xilinx::aievec::BroadcastScalarOp)

AIE2 broadcast scalar

AMD-specific broadcast scalar intrinsic. Broadcasts input value to all vector lanes. $result = broadcast_scalar($source)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
source	bfloat16 type or 32-bit float or 32-bit signless integer or 16-bit signless integer or 8-bit signless integer

Results:

Result	Description
result	vector of any type values

aievec.bxor (::xilinx::aievec::BxorOp)

AIE vector bitwise xor

Syntax:

operation ::= `aievec.bxor` $lhs `,` $rhs attr-dict `:` type($lhs) `,` type($rhs)
              `,` type($result)

AMD-specific intrinsic that computes bitwise xor of two vectors and returns the result. $result = bxor($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type
rhs	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

Results:

Result	Description
result	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

aievec.cast (::xilinx::aievec::CastOp)

AIE cast

AIE2 cast intrinsic. Cast values from source data type to result data types. $result = cast($source, isResAcc)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
isResAcc	::mlir::BoolAttr	bool attribute

Operands:

Operand	Description
source	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.cmp (::xilinx::aievec::CmpOp)

AIE vector comparison

Syntax:

operation ::= `aievec.cmp` $lhs `,` $rhs ` ` `{` `pred` `=` $pred attr-dict `}` `:` type($lhs) `,` type($rhs)  `,` type($result)

AMD-specific intrinsic that performs element-wise comparisonof two input vectors. The attribute predicate defines which type of comparison is performed. The following comparisons are supported:

• equal (mnemonic: "eq")
• not equal (mnemonic: "ne")
• signed less than (mnemonic: "slt")
• unsigned less than (mnemonic: "ult")
• signed less than or equal (mnemonic: "sle")
• unsigned less than or equal (mnemonic: "ule")
• signed greater than (mnemonic: "sgt")
• unsigned greater than (mnemonic: "ugt")
• signed greater than or equal (mnemonic: "sge")
• unsigned greater than or equal (mnemonic: "uge")

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
pred	::mlir::StringAttr	string attribute

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values

Results:

Result	Description
result	unsigned integer

aievec.concat (::xilinx::aievec::ConcatOp)

AIE concat

AMD-specific concat intrinsic. Concatenates two or more smaller vectors into a bigger vector. The verifier confirms that all the input vectors have the same number of lanes. $result = concat($sources[0], $sources[1], ...)

Traits: AlwaysSpeculatableImplTrait, InferTypeOpAdaptor

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
sources	variadic of vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.ext (::xilinx::aievec::ExtOp)

AIE ext

AMD-specific vector extract intrinsic. Selects contiguous lanes from the source vector, and transfers the data from those lanes to the result. The lane selection is controlled by index. There are two cases:

1. Extracted vector fills half of the original vector lanes (e.g. extract v64int8 from v128int8)
2. Extracted vector fills a fourth of the original vector lanes (e.g. extract v32int8 from v128int8) In the first case, index can be 0 or 1. Index 0 extracts the lower half, and index 1 extracts the upper half. In the second case, index can be 0 to 3. Index 0 extracts the lowest quarter, index 1 the next quarter, and so on. $result = ext($source, $index)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
index	::mlir::IntegerAttr	8-bit signless integer attribute whose minimum value is 0 whose maximum value is 8

Operands:

Operand	Description
source	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.ext_elem (::xilinx::aievec::ExtElemOp)

AIE extract element

Syntax:

operation ::= `aievec.ext_elem` $source `,` $index attr-dict `:` type($source) `,` type($index) `,` type($result)

AMD - specific extract element intrinsic. Extract element determined by index from vector. $result = ext_elem($source, $index).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
source	vector of any type values
index	32-bit signless integer

Results:

Result	Description
result	bfloat16 type or 32-bit float or 32-bit signless integer or 16-bit signless integer or 8-bit signless integer

aievec.fma_conv (::xilinx::aievec::FMAConvOp)

AIE2 multiply accumulate convolution

AMD-specific multiply accumulate convolution intrinsic. Multiply accumulate convolution operation of (M x N)matrix with (N x 1)kernel. $result = mac_convMxN($lhs, $rhs, $acc)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
M	::mlir::IntegerAttr	32-bit signless integer attribute
N	::mlir::IntegerAttr	32-bit signless integer attribute
fmsub	::mlir::BoolAttr	bool attribute

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values
acc	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.legacyshuffle (::xilinx::aievec::LegacyShuffleOp)

AIE2 shuffle

AMD-specific vector shuffle intrinsic by a specific shuffle mode. $result = shuffle($source, $mode)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
mode	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
source	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.mac_elem (::xilinx::aievec::FMAElemOp)

AIE2 element-wise vector fused multiply-add

AMD-specific multiply-add operation. It multiplies two 1-D vectors in the same channel, and adds the result to an accumulator. $result = $lhs * $rhs + $acc`. Note: the same operator can be used as fmsub operator by setting the ‘fmsub’ bool to true.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
fmsub	::mlir::BoolAttr	bool attribute

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values
acc	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.matmul (::xilinx::aievec::MatMulOp)

AIE2 matrix-multiply and accummulate

Syntax:

operation ::= `aievec.matmul` $lhs `,` $rhs `,` $acc attr-dict `:` type($lhs) `,`
              type($rhs) `into` type($acc)

AMD AIEv2-specific intrinsic that performs a matrix multiplications between lhs and rhs, and accumulates the result in acc.

Currently, this intrinsic supports the following type combinations:

 lhs                | rhs                | Accumulator
:------------------:|:------------------:|:-----------------:
 `vector<4x16xi8>`  | `vector<16x8xi4>`  | `vector<4x8xi32>`
 `vector<4x8xi8>`   | `vector<8x8xi8>`   | `vector<4x8xi32>`
 `vector<4x4xi16>`  | `vector<4x8xi8>`   | `vector<4x8xi32>`
 `vector<4x2xi16>`  | `vector<2x8xi16>`  | `vector<4x8xi32>`
 `vector<2x8xi16>`  | `vector<8x8xi8>`   | `vector<2x8xi64>`
 `vector<4x8xi16>`  | `vector<8x4xi8>`   | `vector<4x4xi64>`
 `vector<2x4xi16>`  | `vector<4x8xi16>`  | `vector<2x8xi64>`
 `vector<4x4xi16>`  | `vector<4x4xi16>`  | `vector<4x4xi64>`
 `vector<4x2xi32>`  | `vector<2x4xi16>`  | `vector<4x4xi64>`
 `vector<4x8xbf16>` | `vector<8x4xbf16>` | `vector<4x4xf32>`

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	a vector compatible with a lhs operand of matrix-multiply and accumulate
rhs	a vector compatible with a rhs operand of matrix-multiply and accumulate
acc	a vector compatible with an accumulator of matrix-multiply and accumulate

Results:

Result	Description
result	a vector compatible with an accumulator of matrix-multiply and accumulate

aievec.max (::xilinx::aievec::MaxOp)

AIE vector maximum

Syntax:

operation ::= `aievec.max` $lhs `,` $rhs attr-dict `:` type($result)

AMD-specific intrinsic that calculates the maximum between two input vectors. $result = max($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.min (::xilinx::aievec::MinOp)

AIE vector minimum

Syntax:

operation ::= `aievec.min` $lhs `,` $rhs attr-dict `:` type($result)

AMD-specific intrinsic that calculates the minimum between two input vectors. $result = min($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.mul_conv (::xilinx::aievec::MulConvOp)

AIE2 multiply convolution

AMD-specific multiply convolution intrinsic. Multiply convolution operation of (M x N)matrix with (N x 1)kernel. $result = mul_convMxN($lhs, $rhs)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
M	::mlir::IntegerAttr	32-bit signless integer attribute
N	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.mul_elem (::xilinx::aievec::MulElemOp)

AIE2 vector element-wise multiply

AMD-specific multiply operation that multiplies two 1-D vectors in the same channel. The vector sizes are at least 512 bits. $result = $lhs * $rhs. Currently, the following are the supported type combinations: lhs | rhs | Accumulator :------------------:|:------------------:|:-----------------: vector<32xi8> | vector<32xi8> | vector<32xi32> vector<32xi16> | vector<32xi16> | vector<32xi32> vector<16xi32> | vector<16xi32> | vector<16xi64> vector<16xbf16> | vector<16xbf16> | vector<16xf32> vector<16xf32> | vector<16xf32> | vector<16xf32>`’

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultShape, SameOperandsShape, SameTypeOperands

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type or 32-bit float values of length 16/32
rhs	vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type or 32-bit float values of length 16/32

Results:

Result	Description
result	vector of 32-bit signless integer or 64-bit signless integer or 32-bit float values of length 16/32

aievec.neg (::xilinx::aievec::NegOp)

AIE vector negative

Syntax:

operation ::= `aievec.neg` $source attr-dict `:` type($result)

AMD-specific intrinsic that negates the vector and returns the result. $result = neg($source`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
source	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.pack (::xilinx::aievec::PackOp)

AIE pack

AMD-specific pack intrinsic. Pack a vector of 16-bit values into a vector of 8-bit values. $result = pack($source)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
source	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.sel (::xilinx::aievec::SelOp)

AIE vector lane wise selection

Syntax:

operation ::= `aievec.sel` $lhs `,` $rhs `,` $sel attr-dict `:` type($lhs) `,` type($rhs) `,` type($sel) `,` type($result)

AMD-specific intrinsic that performs lane wise selection between two input vectors, if a bit of sel is zero, the lane of vector lhs is selected, else the lane of vector rhs is selected. $result = sel($lhs, $rhs, $sel`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values
sel	unsigned integer

Results:

Result	Description
result	vector of any type values

aievec.shift (::xilinx::aievec::ShiftOp)

AIE2 concat and shift

AMD-specific shift intrinsic. Concatenates two vectors into a bigger vector, interprets them as a vector of 128 bytes and returns v1::v2[shift: shift+64]. shift is the number of bytes to be shifted. The verifier confirms that all the input and result vectors have the same number of lanes and element types. $result = shift($lhs, $rhs, $shift)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
isAcc	::mlir::BoolAttr	bool attribute

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values
shift	32-bit signless integer

Results:

Result	Description
result	vector of any type values

aievec.shuffle (::xilinx::aievec::ShuffleOp)

AIE2 shuffle

Syntax:

operation ::= `aievec.shuffle` $lhs (`,` $rhs^)? $mode attr-dict `:` type($result)

AMD AIEv2-specific vector shuffle. It performs a shuffle of the elements of 1 or 2 input vectors using the specified shuffle mode. The shuffle mode is specified as:

t<width>_<r>x<c>(_(hi|lo))?

where <width> is the bitwidth of the vector element type, <r> and <c> are the number of rows and columns that will be transposed to perform the shuffle, and, for modes that require two 512-bit vectors, hi and lo indicate which part of the resulting extended 1024-bit vector will be assembled and returned.

E.g.: t32_4x8 would take two 512-bit vectors, lhs and rhs, with 16 elements of 32 bits each. The resulting vector would contain either the least (lo) or most (hi) significant 16 elements of the 32 element vector that would result from selecting, out of the concatenated vectors lhs:rhs, 8 blocks of 4 elements, each block taking one of every 8 elements starting from the block index.

That is, for two vector<16xi32> operands containing:

lhs = [0,   1,  2,  3, ..., 15]
rhs = [17, 18, 19, 20, ..., 31]

The first 8 blocks would be:

b0 = [0,  8, 16, 24]
b1 = [1,  9, 17, 25]
b2 = [2, 10, 18, 26]
b3 = [3, 11, 19, 27]
   ...
b7 = [7, 15, 23, 31]

t32_4x8_lo would return first four blocks:

result = [0, 8, 16, 24, 1, 9, 17, 25, ..., 3, 11, 19, 27]

And t32_4x8_hi would return the last four blocks:

result = [4, 12, 20, 28, 5, 13, 21, 29, ..., 7, 15, 24, 31]

It can be seen as flattened 4x8 matrix, split in two 16-element halfs, being tranposed to a 8x4 arrangement. In the example above:

lhs = [ 0,  1,  2,  3,  4,  5,  6,  7]
      [ 8,  9, 10, 11, 12, 13, 14, 15]
rhs = [16, 17, 18, 19, 20, 21, 22, 23]
      [24, 25, 26, 27, 28, 29, 30, 31]

Would result in:

t32_4x8_lo = [0,  8, 16, 24]
             [1,  9, 17, 25]
             [2, 10, 18, 26]
             [3, 11, 19, 27]
t32_4x8_hi = [4, 12, 20, 28]
             [5, 13, 21, 29]
             [6, 14, 22, 30]
             [7, 15, 23, 31]

A special mode, t16_1x2_flip, swaps each pair of elements in a vector with 32 16-bit elements. E.g.:

lhs = [0, 1, 2, 3, ..., 28, 29, 30, 31]

Would result in:

t16_1x2_flip = [1, 0, 3, 2, ..., 29, 28, 31, 30]

The list of supported shuffle modes, required operands, and associated vector types are the following:

 Shuffle Mode       | Operands           | Types Supported
:------------------:|:------------------:|:------------------:
 t8_8x4             | `lhs`              | `vector<64xi8>`
 t8_4x8             | ^                  | ^
 t8_8x8             | ^                  | ^
 t8_16x4            | ^                  | ^
 t8_4x16            | ^                  | ^
 t8_64x2_lo         | `lhs` & `rhs`      | ^
 t8_64x2_hi         | ^                  | ^
 t8_2x64_lo         | ^                  | ^
 t8_2x64_hi         | ^                  | ^
 t16_4x2            | `lhs`              | `vector<32xi16>` or `vector<32xbf16>`
 t16_2x4            | ^                  | ^
 t16_4x4            | ^                  | ^
 t16_8x2            | ^                  | ^
 t16_2x8            | ^                  | ^
 t16_8x4            | ^                  | ^
 t16_4x8            | ^                  | ^
 t16_16x2           | ^                  | ^
 t16_2x16           | ^                  | ^
 t16_1x2_flip       | ^                  | ^
 t16_32x2_lo        | `lhs` & `rhs`      | ^
 t16_32x2_hi        | ^                  | ^
 t16_2x32_lo        | ^                  | ^
 t16_2x32_hi        | ^                  | ^
 t16_16x4_lo        | ^                  | ^
 t16_16x4_hi        | ^                  | ^
 t16_4x16_lo        | ^                  | ^
 t16_4x16_hi        | ^                  | ^
 t32_4x4            | `lhs`              | `vector<16xi32>` or `vector<16xf32>`
 t32_16x2_lo        | `lhs` & `rhs`      | ^
 t32_16x2_hi        | ^                  | ^
 t32_2x16_lo        | ^                  | ^
 t32_2x16_hi        | ^                  | ^
 t32_8x4_lo         | ^                  | ^
 t32_8x4_hi         | ^                  | ^
 t32_4x8_lo         | ^                  | ^
 t32_4x8_hi         | ^                  | ^
 t64_8x2_lo         | ^                  | `vector<8xi64>`
 t64_8x2_hi         | ^                  | ^
 t64_2x8_lo         | ^                  | ^
 t64_2x8_hi         | ^                  | ^
 t128_4x2_lo        | ^                  | `vector<4xi128>`
 t128_4x2_hi        | ^                  | ^
 t128_2x4_lo        | ^                  | ^
 t128_2x4_hi        | ^                  | ^
 t256_2x2_lo        | ^                  | `vector<2xi256>`
 t256_2x2_hi        | ^                  | ^
 t512_1x2_lo        | ^                  | `vector<1xi512>`
 t512_1x2_hi        | ^                  | ^

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
mode	::xilinx::aievec::ShuffleModeAttr	Shuffle mode for AIEVec shuffle operations Enum cases: * t8_64x2_lo (`T8_64X2_LO`) * t8_64x2_hi (`T8_64X2_HI`) * t16_32x2_lo (`T16_32X2_LO`) * t16_32x2_hi (`T16_32X2_HI`) * t32_16x2_lo (`T32_16X2_LO`) * t32_16x2_hi (`T32_16X2_HI`) * t64_8x2_lo (`T64_8X2_LO`) * t64_8x2_hi (`T64_8X2_HI`) * t128_4x2_lo (`T128_4X2_LO`) * t128_4x2_hi (`T128_4X2_HI`) * t256_2x2_lo (`T256_2X2_LO`) * t256_2x2_hi (`T256_2X2_HI`) * t128_2x4_lo (`T128_2X4_LO`) * t128_2x4_hi (`T128_2X4_HI`) * t64_2x8_lo (`T64_2X8_LO`) * t64_2x8_hi (`T64_2X8_HI`) * t32_2x16_lo (`T32_2X16_LO`) * t32_2x16_hi (`T32_2X16_HI`) * t16_2x32_lo (`T16_2X32_LO`) * t16_2x32_hi (`T16_2X32_HI`) * t8_2x64_lo (`T8_2X64_LO`) * t8_2x64_hi (`T8_2X64_HI`) * t512_1x2_lo (`T512_1X2_LO`) * t512_1x2_hi (`T512_1X2_HI`) * t16_16x4_lo (`T16_16X4_LO`) * t16_16x4_hi (`T16_16X4_HI`) * t16_4x16_lo (`T16_4X16_LO`) * t16_4x16_hi (`T16_4X16_HI`) * t16_8x4 (`T16_8X4`) * t16_4x8 (`T16_4X8`) * t32_8x4_lo (`T32_8X4_LO`) * t32_8x4_hi (`T32_8X4_HI`) * t32_4x8_lo (`T32_4X8_LO`) * t32_4x8_hi (`T32_4X8_HI`) * t32_4x4 (`T32_4X4`) * t8_8x8 (`T8_8X8`) * t8_16x4 (`T8_16X4`) * t8_4x16 (`T8_4X16`) * t16_1x2_flip (`T16_1X2_flip`) * t16_4x4 (`T16_4X4`) * t16_4x2 (`T16_4X2`) * t16_2x4 (`T16_2X4`) * t16_8x2 (`T16_8X2`) * t16_2x8 (`T16_2X8`) * t16_16x2 (`T16_16X2`) * t16_2x16 (`T16_2X16`) * t8_8x4 (`T8_8X4`) * t8_4x8 (`T8_4X8`)

Operands:

Operand	Description
lhs	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer or 128-bit signless integer or 256-bit signless integer or 512-bit signless integer or bfloat16 type or 32-bit float
rhs	512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer or 128-bit signless integer or 256-bit signless integer or 512-bit signless integer or bfloat16 type or 32-bit float

Results:

Result	Description
result	vector of any type values

aievec.srs (::xilinx::aievec::SRSOp)

AIE srs

AMD-specific shift-round-saturate intrinsic. Moves values from accumulator data type to AIE vector data types. The adjustment in precision is controlled by the shift parameter. $result = srs($source, $shift)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
source	vector of any type values
shift	integer

Results:

Result	Description
result	vector of any type values

aievec.sub_elem (::xilinx::aievec::SubElemOp)

AIE vector sub elem

Syntax:

operation ::= `aievec.sub_elem` $lhs `,` $rhs attr-dict `:` type($result)

AMD-specific AIE2 intrinsic that allows you to perform substraction operation on all types of vectors.$result = $lhs - $rhs`.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
lhs	vector of any type values
rhs	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.unpack (::xilinx::aievec::UnpackOp)

AIE unpack

AMD-specific unpack intrinsic. Unpack a vector of 8-bit values into a vector of 16-bit values. $result = unpack($source)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand	Description
source	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.upd (::xilinx::aievec::UPDOp)

AIE upd

AMD-specific update intrinsic. General upd intrinsic updates contiguous lanes of the result vector from a smaller source vector. This form of upd intrinsic combines the load of data from memory into a vector register, and then updating the lanes of the result vector using it. $result = upd($source[$indices], $offset, $index)

Traits: AlwaysSpeculatableImplTrait, AttrSizedOperandSegments

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
offset	::mlir::IntegerAttr	32-bit signless integer attribute
index	::mlir::IntegerAttr	8-bit signless integer attribute whose minimum value is 0 whose maximum value is 1

Operands:

Operand	Description
source	shaped of any type values
indices	variadic of index
vector	vector of any type values

Results:

Result	Description
result	vector of any type values

aievec.ups (::xilinx::aievec::UPSOp)

AIE ups

AMD-specific upshift intrinsic. Moves data from AIE vector data type to accumulator data type. The adjustment in precision is controlled by the shift parameter. $result = ups($source, $shift)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

Attribute	MLIR Type	Description
shift	::mlir::IntegerAttr	8-bit signless integer attribute whose value is non-negative

Operands:

Operand	Description
source	vector of any type values

Results:

Result	Description
result	vector of any type values

Attributes

ShuffleModeAttr

Shuffle mode for AIEVec shuffle operations

Syntax:

#aievec.mode<
  ::xilinx::aievec::ShuffleMode   # value
>

Enum cases:

• t8_64x2_lo (T8_64X2_LO)
• t8_64x2_hi (T8_64X2_HI)
• t16_32x2_lo (T16_32X2_LO)
• t16_32x2_hi (T16_32X2_HI)
• t32_16x2_lo (T32_16X2_LO)
• t32_16x2_hi (T32_16X2_HI)
• t64_8x2_lo (T64_8X2_LO)
• t64_8x2_hi (T64_8X2_HI)
• t128_4x2_lo (T128_4X2_LO)
• t128_4x2_hi (T128_4X2_HI)
• t256_2x2_lo (T256_2X2_LO)
• t256_2x2_hi (T256_2X2_HI)
• t128_2x4_lo (T128_2X4_LO)
• t128_2x4_hi (T128_2X4_HI)
• t64_2x8_lo (T64_2X8_LO)
• t64_2x8_hi (T64_2X8_HI)
• t32_2x16_lo (T32_2X16_LO)
• t32_2x16_hi (T32_2X16_HI)
• t16_2x32_lo (T16_2X32_LO)
• t16_2x32_hi (T16_2X32_HI)
• t8_2x64_lo (T8_2X64_LO)
• t8_2x64_hi (T8_2X64_HI)
• t512_1x2_lo (T512_1X2_LO)
• t512_1x2_hi (T512_1X2_HI)
• t16_16x4_lo (T16_16X4_LO)
• t16_16x4_hi (T16_16X4_HI)
• t16_4x16_lo (T16_4X16_LO)
• t16_4x16_hi (T16_4X16_HI)
• t16_8x4 (T16_8X4)
• t16_4x8 (T16_4X8)
• t32_8x4_lo (T32_8X4_LO)
• t32_8x4_hi (T32_8X4_HI)
• t32_4x8_lo (T32_4X8_LO)
• t32_4x8_hi (T32_4X8_HI)
• t32_4x4 (T32_4X4)
• t8_8x8 (T8_8X8)
• t8_16x4 (T8_16X4)
• t8_4x16 (T8_4X16)
• t16_1x2_flip (T16_1X2_flip)
• t16_4x4 (T16_4X4)
• t16_4x2 (T16_4X2)
• t16_2x4 (T16_2X4)
• t16_8x2 (T16_8X2)
• t16_2x8 (T16_2X8)
• t16_16x2 (T16_16X2)
• t16_2x16 (T16_2X16)
• t8_8x4 (T8_8X4)
• t8_4x8 (T8_4X8)

Parameters:

Parameter	C++ type	Description
value	::xilinx::aievec::ShuffleMode	an enum of type ShuffleMode

Enums

AIEArch

AIE Architecture

Cases:

Symbol	Value	String
AIE1	1	AIE1
AIE2	2	AIE2
AIE2p	3	AIE2p

AIEDevice

AIE Device

Cases:

Symbol	Value	String
xcvc1902	1	xcvc1902
xcve2302	2	xcve2302
xcve2802	3	xcve2802
npu1	4	npu1
npu1_1col	5	npu1_1col
npu1_2col	6	npu1_2col
npu1_3col	7	npu1_3col
npu1_4col	8	npu1_4col
npu2	9	npu2

CascadeDir

Directions for cascade

Cases:

Symbol	Value	String
South	3	South
West	4	West
North	5	North
East	6	East

DMAChannelDir

DMA Channel direction

Cases:

Symbol	Value	String
S2MM	0	S2MM
MM2S	1	MM2S

LockAction

lock acquire/release

Cases:

Symbol	Value	String
Acquire	0	Acquire
AcquireGreaterEqual	2	AcquireGreaterEqual
Release	1	Release

LockBlocking

lock operation is blocking

Cases:

Symbol	Value	String
NonBlocking	0	NonBlocking
Blocking	1	Blocking

ObjectFifoPort

Ports of an object FIFO

Cases:

Symbol	Value	String
Produce	0	Produce
Consume	1	Consume

ShuffleMode

Shuffle mode for AIEVec shuffle operations

Cases:

Symbol	Value	String
T8_64X2_LO	0	t8_64x2_lo
T8_64X2_HI	1	t8_64x2_hi
T16_32X2_LO	2	t16_32x2_lo
T16_32X2_HI	3	t16_32x2_hi
T32_16X2_LO	4	t32_16x2_lo
T32_16X2_HI	5	t32_16x2_hi
T64_8X2_LO	6	t64_8x2_lo
T64_8X2_HI	7	t64_8x2_hi
T128_4X2_LO	8	t128_4x2_lo
T128_4X2_HI	9	t128_4x2_hi
T256_2X2_LO	10	t256_2x2_lo
T256_2X2_HI	11	t256_2x2_hi
T128_2X4_LO	12	t128_2x4_lo
T128_2X4_HI	13	t128_2x4_hi
T64_2X8_LO	14	t64_2x8_lo
T64_2X8_HI	15	t64_2x8_hi
T32_2X16_LO	16	t32_2x16_lo
T32_2X16_HI	17	t32_2x16_hi
T16_2X32_LO	18	t16_2x32_lo
T16_2X32_HI	19	t16_2x32_hi
T8_2X64_LO	20	t8_2x64_lo
T8_2X64_HI	21	t8_2x64_hi
T512_1X2_LO	22	t512_1x2_lo
T512_1X2_HI	23	t512_1x2_hi
T16_16X4_LO	24	t16_16x4_lo
T16_16X4_HI	25	t16_16x4_hi
T16_4X16_LO	26	t16_4x16_lo
T16_4X16_HI	27	t16_4x16_hi
T16_8X4	28	t16_8x4
T16_4X8	29	t16_4x8
T32_8X4_LO	30	t32_8x4_lo
T32_8X4_HI	31	t32_8x4_hi
T32_4X8_LO	32	t32_4x8_lo
T32_4X8_HI	33	t32_4x8_hi
T32_4X4	34	t32_4x4
T8_8X8	35	t8_8x8
T8_16X4	36	t8_16x4
T8_4X16	37	t8_4x16
T16_1X2_flip	38	t16_1x2_flip
T16_4X4	39	t16_4x4
T16_4X2	40	t16_4x2
T16_2X4	41	t16_2x4
T16_8X2	42	t16_8x2
T16_2X8	43	t16_2x8
T16_16X2	44	t16_16x2
T16_2X16	45	t16_2x16
T8_8X4	46	t8_8x4
T8_4X8	47	t8_4x8

WireBundle

Bundle of wires

Cases:

Symbol	Value	String
Core	0	Core
DMA	1	DMA
FIFO	2	FIFO
South	3	South
West	4	West
North	5	North
East	6	East
PLIO	7	PLIO
NOC	8	NOC
Trace	9	Trace
Ctrl	10	Ctrl