‘aiex’ Dialect

This is a dialect for experimental work related to AIEngine processors. The expectation is that new ideas can be developed here before migration to the more mature AIE dialect.

[TOC]

Operations

aiex.bp_dest (::xilinx::AIEX::BPDestOp)

A destination port

Syntax:

operation ::= `aiex.bp_dest` `<` $tile `,` $bundle `:` $channel `>` attr-dict

An object representing the destination of a Broad Packet. This must exist within an [AIE.bp_id] operation. See [AIE.broadcast_packet] for an example.

Traits: HasParent<BPIDOp>

Attributes:

Attribute	MLIR Type	Description
bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
channel	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
tile	index

aiex.bp_id (::xilinx::AIEX::BPIDOp)

A set of packets that share the same ID

Syntax:

operation ::= `aiex.bp_id` `(` $ID `)` regions attr-dict

A set of destination packets that share the same source and ID. This must exist within an [AIE.broadcast_packet] operation. See [AIE.broadcast_packet]for an example.

Traits: SingleBlockImplicitTerminator<AIE::EndOp>, SingleBlock

Attributes:

Attribute	MLIR Type	Description
ID	::mlir::IntegerAttr	8-bit signless integer attribute

aiex.broadcast_packet (::xilinx::AIEX::BroadcastPacketOp)

Combination of broadcast and packet-switch

Syntax:

operation ::= `aiex.broadcast_packet` `(` $tile `,` $bundle `:` $channel `)` regions attr-dict

An abstraction of broadcast and packet-switched flow. During place and route, it will be replaced by packet-switched flow and further replaced by MasterSets and PacketRules inside switchboxes.

Example:

  %70 = AIE.tile(7, 0)
  %73 = AIE.tile(7, 3)
  %74 = AIE.tile(7, 4)
  %63 = AIE.tile(6, 3)
  %64 = AIE.tile(6, 4)
  AIE.broadcast_packet(%70, "DMA" : 0){
    AIE.bp_id(0x0){
      AIE.bp_dest<%73, "DMA" : 0>
      AIE.bp_dest<%63, "DMA" : 0>
    }
    AIE.bp_id(0x1){
      AIE.bp_dest<%74, "DMA" : 0>
      AIE.bp_dest<%64, "DMA" : 0>
    }
  }

Traits: SingleBlockImplicitTerminator<AIE::EndOp>, SingleBlock

Attributes:

Attribute	MLIR Type	Description
bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
channel	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
tile	index

aiex.configure (::xilinx::AIEX::ConfigureOp)

Set up a configuration (program memories, stream switches, etc.) on the NPU device.

Syntax:

operation ::= `aiex.configure` $symbol regions attr-dict

Traits: HasParent<AIE::RuntimeSequenceOp>, NoTerminator

Attributes:

Attribute	MLIR Type	Description
symbol	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

aiex.connection (::xilinx::AIEX::ConnectionOp)

A logical circuit-switched connection between cores

Syntax:

operation ::= `aiex.connection` `(` $source `,` $sourceBundle `:` $sourceChannel `,` $dest `,` $destBundle `:` $destChannel `)` attr-dict

The “aie.connection” operation represents a circuit switched connection between two endpoints, usually “aie.core” operations. During routing, this is replaced by “aie.connect” operations which represent the programmed connections inside a switchbox, along with “aie.wire” operations which represent physical connections between switchboxes and other components. Note that while “aie.flow” operations can express partial routes between tiles, this is not possible with “aie.connection” operations.

Example: %22 = aie.tile(2, 2) %c22 = aie.core(%22) %11 = aie.tile(1, 1) %c11 = aie.core(%11) aie.flow(%c22, “Core” : 0, %c11, “Core” : 1)

Attributes:

Attribute	MLIR Type	Description
sourceBundle	xilinx::AIE::WireBundleAttr	Bundle of wires
sourceChannel	::mlir::IntegerAttr	32-bit signless integer attribute
destBundle	xilinx::AIE::WireBundleAttr	Bundle of wires
destChannel	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
source	index
dest	index

aiex.control_packet (::xilinx::AIEX::NpuControlPacketOp)

AIE control packet

Syntax:

operation ::= `aiex.control_packet` attr-dict

The control_packet operation represents a low-level AIE control packet header and payload.

Attributes:

Attribute	MLIR Type	Description
address	::mlir::IntegerAttr	32-bit unsigned integer attribute
length	::mlir::IntegerAttr	32-bit signless integer attribute
opcode	::mlir::IntegerAttr	32-bit signless integer attribute
stream_id	::mlir::IntegerAttr	32-bit signless integer attribute
data	::mlir::DenseI32ArrayAttr	i32 dense array attribute

aiex.dma_await_task (::xilinx::AIEX::DMAAwaitTaskOp)

Await Completion of a Previously Submitted DMA Task

Syntax:

operation ::= `aiex.dma_await_task` `(` $task `)` attr-dict

This operation will block execution of the runtime sequence until the referenced previously started DMA task has completed.

DMA tasks can be started using aiex.start_task using abstract BD chains declared using aie.bd_chain, or using aiex.start_configured_task using a manually configured task.

To be able to wait on a task, it must issue a task completion token (TCT). Tasks only emit these tokens if the attribute issue_token is set to true.

Traits: HasParent<AIE::RuntimeSequenceOp>

Operands:

Operand	Description
task	index

aiex.dma_configure_task (::xilinx::AIEX::DMAConfigureTaskOp)

Concrete Instantiation of a Buffer Descriptor Chain as a Task on a Channel and Direction on a Tile

Syntax:

operation ::= `aiex.dma_configure_task` `(` $tile `,` $direction `,` $channel (`,` $packet^)? `)` regions attr-dict

Encapsulates the DMA configuration of one task, that is the (chain of) buffer descriptors to be executed on a given channel and direction on a tile.

Such configurations are generated by materializing abstract aie.bd_chains using aiex.start_task, or can be created manually using this op.

Once configured, a task can be submitted for execution using aiex.dma_start_configured_task, after which its execution completion can be awaited using aiex.dma_await_task.

Traits: HasParent<AIE::RuntimeSequenceOp>

Interfaces: OpAsmOpInterface, TileElement

Attributes:

Attribute	MLIR Type	Description
direction	xilinx::AIE::DMAChannelDirAttr	DMA Channel direction
channel	::mlir::IntegerAttr	32-bit signless integer attribute
issue_token	::mlir::BoolAttr	bool attribute
repeat_count	::mlir::IntegerAttr	32-bit signless integer attribute
packet	::xilinx::AIE::PacketInfoAttr	Tuple encoding the type and header of a packet;

Operands:

Operand	Description
tile	index

Results:

Result	Description
result	index

aiex.dma_configure_task_for (::xilinx::AIEX::DMAConfigureTaskForOp)

As dma_configure_task, but specify tile, direction and channel by reference to a Shim DMA allocation op

Syntax:

operation ::= `aiex.dma_configure_task_for` $alloc regions attr-dict

Traits: HasParent<AIE::RuntimeSequenceOp>

Attributes:

Attribute	MLIR Type	Description
alloc	::mlir::SymbolRefAttr	symbol reference attribute
issue_token	::mlir::BoolAttr	bool attribute
repeat_count	::mlir::IntegerAttr	32-bit signless integer attribute

Results:

Result	Description
result	index

aiex.dma_free_task (::xilinx::AIEX::DMAFreeTaskOp)

Free all Buffer Descriptor IDs Associated with the Given Task

Syntax:

operation ::= `aiex.dma_free_task` `(` $task `)` attr-dict

This operation informs the static buffer descriptor allocator pass in the compiler that the buffer descriptor IDs it has allocated to the BDs inside the referenced task can be reused thereafter.

Potential future implementations of dynamic buffer descriptor allocators may lower this to a free instruction.

Traits: HasParent<AIE::RuntimeSequenceOp>

Operands:

Operand	Description
task	index

aiex.dma_start_bd_chain (::xilinx::AIEX::DMAStartBdChainOp)

Materialize an Abstract BD Chain as a DMA Task on the Given Tile, Channel and Direction and Immediately Start It

Syntax:

operation ::= `aiex.dma_start_bd_chain` $symbol `(` $args `)` `:` `(` type($args) `)` ` ` `on` ` ` `(` $tile `,` $direction `,` $channel `)` attr-dict

This operation will configure a new DMA task on the given tile, channel and direction by concretizing an abstract BD chain, previously defined using aie.bd_chain, with the given input arguments.

Completion of the DMA task, i.e. the data transfer, can be awaited using aiex.await_task if the attribute issue_token is set to true.

Traits: HasParent<AIE::RuntimeSequenceOp>

Interfaces: OpAsmOpInterface, TileElement

Attributes:

Attribute	MLIR Type	Description
symbol	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
direction	xilinx::AIE::DMAChannelDirAttr	DMA Channel direction
channel	::mlir::IntegerAttr	32-bit signless integer attribute
issue_token	::mlir::BoolAttr	bool attribute
repeat_count	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
args	variadic of any type
tile	index

Results:

Result	Description
result	index

aiex.dma_start_bd_chain_for (::xilinx::AIEX::DMAStartBdChainForOp)

As dma_start_bd_chain, but specify tile, direction and channel by reference to a Shim DMA allocation op

Syntax:

operation ::= `aiex.dma_start_bd_chain_for` $symbol `(` $args `)` `:` `(` type($args) `)` ` ` `for` ` ` $alloc attr-dict

Traits: HasParent<AIE::RuntimeSequenceOp>

Attributes:

Attribute	MLIR Type	Description
symbol	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
alloc	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
issue_token	::mlir::BoolAttr	bool attribute
repeat_count	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
args	variadic of any type

Results:

Result	Description
result	index

aiex.dma_start_task (::xilinx::AIEX::DMAStartTaskOp)

Submit a Preconfigured Task to the Task Queue

Syntax:

operation ::= `aiex.dma_start_task` `(` $task `)` attr-dict

Submits the referenced task for execution on the tile, channel and direction it has been configured to run on. Once submitted, if the task is configured to issue a token, you can await completion of the task using aiex.await_task.

Traits: HasParent<AIE::RuntimeSequenceOp>

Operands:

Operand	Description
task	index

aiex.getTile (::xilinx::AIEX::GetTileOp)

Get a reference to an AIE tile

Syntax:

operation ::= `aiex.getTile` `(` $col `,` $row `)` attr-dict

Return a reference to an AIE tile, given the column and the row of the tile.

Operands:

Operand	Description
col	index
row	index

Results:

Result	Description
result	index

aiex.herd (::xilinx::AIEX::HerdOp)

Declare a herd which is a bundle of core organized in a rectangular shape

Syntax:

operation ::= `aiex.herd` `[` $width `]` `[` $height `]` attr-dict

This operation creates a group of AIE tiles in 2D shape.

Example: %herd0 = AIE.herd[1][1] // a single AIE tile. location unknown %herd1 = AIE.herd[4][1] // a row of four-AIE tile

The operation can be used in replacement of a TileOp – in case we want to select a group of hardware entities (cores, mems, switchboxes) instead of individual entity, and we don’t want to specify their locations just yet. This can be useful if we want to generate parameterizable code (the column and row values are parameterized).

Example:

%herd = AIE.herd[2][2] // a herd of 2x2 AIE tiles

AIE.core(%herd) { // all the cores belong to this herd runs the same code }

Attributes:

Attribute	MLIR Type	Description
width	::mlir::IntegerAttr	32-bit signless integer attribute
height	::mlir::IntegerAttr	32-bit signless integer attribute

Results:

Result	Description
«unnamed»	index

aiex.iter (::xilinx::AIEX::IterOp)

An iter operation

Syntax:

operation ::= `aiex.iter` `(` $start `,` $end `,` $stride `)` attr-dict

This operation generates index values that can be used with the SelectOp to select a group of tiles from a herd.

Example: %iter0 = AIE.iter(0, 15, 1) // 0, 1, 2, … , 15 %iter1 = AIE.iter(2, 8, 2) // 2, 4, 6

Attributes:

Attribute	MLIR Type	Description
start	::mlir::IntegerAttr	32-bit signless integer attribute
end	::mlir::IntegerAttr	32-bit signless integer attribute
stride	::mlir::IntegerAttr	32-bit signless integer attribute

Results:

Result	Description
«unnamed»	index

aiex.memcpy (::xilinx::AIEX::MemcpyOp)

A memcpy op

Syntax:

operation ::= `aiex.memcpy` $tokenName `(` $acqValue `,` $relValue `)` `(`
              $srcTile `:` `<` $srcBuf `,` $srcOffset `,` $srcLen `>` `,`
              $dstTile `:` `<` $dstBuf `,` $dstOffset `,` $dstLen `>` `)`
              attr-dict `:` `(` type($srcBuf) `,` type($dstBuf) `)`

This operation defines a logical data transfer of a buffer from a source tile to another buffer from a destination tile.

This operation should be lowered to Mem ops with DMA setup and Flow ops for routing data from the source tile to the dest. tile.

Attributes:

Attribute	MLIR Type	Description
tokenName	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
acqValue	::mlir::IntegerAttr	32-bit signless integer attribute
relValue	::mlir::IntegerAttr	32-bit signless integer attribute
srcOffset	::mlir::IntegerAttr	32-bit signless integer attribute
srcLen	::mlir::IntegerAttr	32-bit signless integer attribute
dstOffset	::mlir::IntegerAttr	32-bit signless integer attribute
dstLen	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
srcTile	index
srcBuf	memref of any type values
dstTile	index
dstBuf	memref of any type values

aiex.multi_dest (::xilinx::AIEX::MultiDestOp)

A destination port of multicast flow

Syntax:

operation ::= `aiex.multi_dest` `<` $tile `,` $bundle `:` $channel `>` attr-dict

An object representing the destination of a multicast flow. This must exist within an [aiex.multicast] operation. There can be multiple destinations within an aiex.multicast Op.

See [aiex.multicast]for an example.

Traits: HasParent<MulticastOp>

Attributes:

Attribute	MLIR Type	Description
bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
channel	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
tile	index

aiex.multicast (::xilinx::AIEX::MulticastOp)

An abstraction of multicast

Syntax:

operation ::= `aiex.multicast` `(` $tile `,` $bundle `:` $channel `)` regions attr-dict

An abstraction of broadcast. During place and route, it will be replaced by multiple flows.

Example:

  %70 = AIE.tile(7, 0)
  %73 = AIE.tile(7, 3)
  %74 = AIE.tile(7, 4)
  %63 = AIE.tile(6, 3)
  %64 = AIE.tile(6, 4)
  aiex.multicast(%70, "DMA" : 0){
    aiex.multi_dest<%73, "DMA" : 0>
    aiex.multi_dest<%74, "DMA" : 0>
    aiex.multi_dest<%63, "DMA" : 0>
    aiex.multi_dest<%64, "DMA" : 0>
  }

Traits: SingleBlockImplicitTerminator<AIE::EndOp>, SingleBlock

Attributes:

Attribute	MLIR Type	Description
bundle	xilinx::AIE::WireBundleAttr	Bundle of wires
channel	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
tile	index

aiex.npu.address_patch (::xilinx::AIEX::NpuAddressPatchOp)

Address patch operator

Syntax:

operation ::= `aiex.npu.address_patch` attr-dict

address patch operator

Attributes:

Attribute	MLIR Type	Description
addr	::mlir::IntegerAttr	32-bit unsigned integer attribute
arg_idx	::mlir::IntegerAttr	32-bit signless integer attribute
arg_plus	::mlir::IntegerAttr	32-bit signless integer attribute

aiex.npu.blockwrite (::xilinx::AIEX::NpuBlockWriteOp)

Blockwrite operator

Syntax:

operation ::= `aiex.npu.blockwrite` `(` $data `)` attr-dict `:` type($data)

blockwrite operator writes the data from the memref ‘data’ to the AIE array. If ‘buffer’ is present then ‘address’ is interpreted as an offset into the aie.buffer with symbol name ‘buffer’. If ‘column’ and ‘row’ are present then ‘address’ is interpreted as an offset into the memory space of aie.tile(column, row). If ‘buffer’ is not present and ‘column’ and ‘row’ are not present then ‘address’ is interpreted as a full 32-bit address in the AIE array.

Attributes:

Attribute	MLIR Type	Description
address	::mlir::IntegerAttr	32-bit unsigned integer attribute
buffer	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
column	::mlir::IntegerAttr	32-bit signless integer attribute
row	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
data	memref of any type values

aiex.npu.dma_memcpy_nd (::xilinx::AIEX::NpuDmaMemcpyNdOp)

Half DMA operator

Syntax:

operation ::= `aiex.npu.dma_memcpy_nd` `(` $memref ``
              custom<DynamicIndexList>($offsets, $static_offsets) ``
              custom<DynamicIndexList>($sizes, $static_sizes) ``
              custom<DynamicIndexList>($strides, $static_strides) ``
              (`,` `packet` `=` $packet^)? `)`
              attr-dict `:` type($memref)

An n-dimensional half DMA operator.

Programs a DMA to access a memory memref with an access pattern specified by offsets, sizes and strides or static_offsets, static_sizes and static_strides. The operator references the target DMA coordinates (x, y) and channel through the metadata symbol and specifies a descriptor id to be used, which will become the bd_id to be used when lowered further. The issue_token attribute specifies whether the execution of this operation should issue a token which can be received and read for synchronization purposes. This issue_token attribute is set to false by default for MM2S for backward compatibility and is always set to true for S2MM channels. The burst length attribute specifies the burst length in bytes for the DMA operation. A value of 0 indicates that the burst length is not specified and the maximal burst length is used.

metadata – Specifying Tile, Channel, Direction and Linking a dma_memcpy_nd to its Other Half

The metadata attribute must point to a symbol referencing a aie.shim_dma_allocation operation. The tile coordinates of the DMA to configure, the channel number and the direction (MM2S or S2MM) are taken from this operation.

To connect the DMA to its other half (i.e. a MM2S DMA to its receiving end and a S2MM to the sending end), the user must configure a flow (aie.flow) between the tile and channel referenced in the aie.shim_dma_allocation and the corresponding other end.

When using ObjectFIFOs, the aie.shim_dma_allocation operations and the aie.flows are generated automatically. The symbol of the aie.objectfifo (create) operation can be used directly in metadata in this case.

Notes on Synchronization and Reusing Buffer Descriptor IDs

When the dma_memcpy_nd operation executes, it immediately reprograms the buffer descriptor with ID bd_id on tile (x, y), even if that buffer descriptor is currently executing. Without proper synchronization, this inevitably leads to nondeterministic results.

Programming a buffer descriptor that is not currently executing is harmless. Thus, the first dma_memcpy_nd call for each bd_id requires no synchronization.

However, if you wish to later re-use a bd_id on the same tile, you must wait for the previous buffer descriptor to complete. The sync or dma_wait operations can be used for this.

sync blocks until it receives a task completion token (TCT). To properly synchronize, you must thus configure your BD to issue a TCT using the issue_token attribute, then wait on that token before reusing the BD.

dma_wait is a convenience operation that lowers to the corresponding sync operation for the refrenced symbol.

Note that if you have multiple concurrently running BDs and you can reason one BD will always complete after all others, it is not strictly necessary to issue and wait on the TC token for every BD. For example, if you have input and output BDs on the shim, and you know the cores will only push output onto the output BD after the input BDs have completed, it may be sufficient to synchronize only on the output BD before reusing input BDs.

Data Layout Transformations

The sizes and strides attributes describe a data layout transformation to be performed by the DMA. These transformations are described in more depth in the documentation for the aie.dma_bd operation. Note that the syntax here differs from that of the dma_bd operation: offsets and strides are given as separate arrays instead of tuples.

The offsets array is used to calculate a static offset into the memref. Each offset in the array is understood in relation to the shape of the memref; the lowest-dimension offset is a direct offset in units of memref element type, and the higher dimensions are multiplied by the size of the memref in those dimensions. Note that this is for convenience of the user only. The hardware only supports a single static offset, and this offset is calculated at compile time. Thus, all offsets can be equivalently expressed with the lowest dimension only.

Packet Header Attribute

The optional packet attribute defines the packet header and packet type that gets issued per DMA BD. If the attribute is set, then every time the DMA BD gets issued, a packet header is generated prior to the transmission of data. The packet header is used to guide arbitration throughout a packet-routed data flow, where each switch box arbitrates the data packet to stream to a successor based on the packet header.

Traits: AttrSizedOperandSegments

Interfaces: MyOffsetSizeAndStrideOpInterface

Attributes:

Attribute	MLIR Type	Description
static_offsets	::mlir::DenseI64ArrayAttr	i64 dense array attribute with exactly 4 elements
static_sizes	::mlir::DenseI64ArrayAttr	i64 dense array attribute with exactly 4 elements
static_strides	::mlir::DenseI64ArrayAttr	i64 dense array attribute with exactly 4 elements
packet	::xilinx::AIE::PacketInfoAttr	Tuple encoding the type and header of a packet;
metadata	::mlir::SymbolRefAttr	symbol reference attribute
id	::mlir::IntegerAttr	64-bit signless integer attribute
issue_token	::mlir::BoolAttr	bool attribute
d0_zero_before	::mlir::IntegerAttr	64-bit signless integer attribute
d1_zero_before	::mlir::IntegerAttr	64-bit signless integer attribute
d2_zero_before	::mlir::IntegerAttr	64-bit signless integer attribute
d0_zero_after	::mlir::IntegerAttr	64-bit signless integer attribute
d1_zero_after	::mlir::IntegerAttr	64-bit signless integer attribute
d2_zero_after	::mlir::IntegerAttr	64-bit signless integer attribute
burst_length	::mlir::IntegerAttr	64-bit signless integer attribute

Operands:

Operand	Description
memref	ranked or unranked memref of any type values
offsets	variadic of 64-bit signless integer
sizes	variadic of 64-bit signless integer
strides	variadic of 64-bit signless integer

aiex.npu.dma_wait (::xilinx::AIEX::NpuDmaWaitOp)

Blocking operation to wait for a DMA to complete execution.

Syntax:

operation ::= `aiex.npu.dma_wait` attr-dict

The NpuDmaWaitOp blocks until the DMA referenced through symbol completes execution and issues a task-complete-token (TCT).

symbol is a reference to a aie.shim_dma_allocation, which contains information about the column, channel and channel direction on which to wait for a TCT. The aie.shim_dma_allocation may be generated from an ObjectFIFO, in which case you can directly pass the ObjectFIFO symbol refrence. npu.dma_wait will be lowered to the corresponding npu.sync operation using the information from symbol.

Example:

  ...
  aie.objectfifo @out0(%tile_0_1, {%tile_0_0}, 4 : i32) : !aie.objectfifo<memref<32x32xi32>>
  ...
  aiex.npu.dma_memcpy_nd(0, 0, %arg2[1, 1, 0, 0][1, 1, 32, 32][1, 1, 64, 1]) {id = 0 : i64, issue_token = true, metadata = @out0} : memref<32x64xi32>
  ...
  aiex.npu.dma_wait { symbol = @out0 }

Here, we have an objectfifo with symbol name out0, which is then referenced in the npu.dma_memcpy_nd operation as the target for the respective DMA operation. Afterwards, an npu.dma_wait operation references the same symbol to block until the respective DMA has executed all of its tasks.

Attributes:

Attribute	MLIR Type	Description
symbol	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

aiex.npu.load_pdi (::xilinx::AIEX::NpuLoadPdiOp)

Load pdi operator

Syntax:

operation ::= `aiex.npu.load_pdi` attr-dict

Load a PDI (Programmable Device Image) to configure the NPU. The PDI is identified by id. address and size are typically written at runtime by the driver or host program.

If a symbol reference is provided, the compiler driver (aiecc.py) will match it to a device symbol name and assign the PDI ID field based on it.

Attributes:

Attribute	MLIR Type	Description
device_ref	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
id	::mlir::IntegerAttr	32-bit signless integer attribute
size	::mlir::IntegerAttr	32-bit signless integer attribute
address	::mlir::IntegerAttr	64-bit unsigned integer attribute

aiex.npu.maskwrite32 (::xilinx::AIEX::NpuMaskWrite32Op)

Write a masked 32-bit value to the AIE array

Syntax:

operation ::= `aiex.npu.maskwrite32` attr-dict

NPU mask write32 operator writes a masked 32bit value to the AIE array. If ‘buffer’ is present then ‘address’ is interpreted as an offset into the aie.buffer with symbol name ‘buffer’. If ‘column’ and ‘row’ are present then ‘address’ is interpreted as an offset into the memory space of aie.tile(column, row). If ‘buffer’ is not present and ‘column’ and ‘row’ are not present then ‘address’ is interpreted as a full 32-bit address in the AIE array.

Attributes:

Attribute	MLIR Type	Description
address	::mlir::IntegerAttr	32-bit unsigned integer attribute
value	::mlir::IntegerAttr	32-bit unsigned integer attribute
mask	::mlir::IntegerAttr	32-bit unsigned integer attribute
buffer	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
column	::mlir::IntegerAttr	32-bit signless integer attribute
row	::mlir::IntegerAttr	32-bit signless integer attribute

aiex.npu.preempt (::xilinx::AIEX::NpuPreemptOp)

Preempt transaction operation

Syntax:

operation ::= `aiex.npu.preempt` attr-dict

Yield to higher priority task(s). Indicates to the transaction processor that the instruction stream can be interrupted at this point. Levels: 0: Noop. 1: Mem tile. 2: AIE tile. 3: AIE registers.

Attributes:

Attribute	MLIR Type	Description
level	::mlir::IntegerAttr	8-bit unsigned integer attribute

aiex.npu.push_queue (::xilinx::AIEX::NpuPushQueueOp)

Bd queue push operator

Syntax:

operation ::= `aiex.npu.push_queue` `(` $column `,` $row `,` $direction `:` $channel `)` attr-dict

bd queue push operator

Attributes:

Attribute	MLIR Type	Description
column	::mlir::IntegerAttr	32-bit signless integer attribute
row	::mlir::IntegerAttr	32-bit signless integer attribute
direction	xilinx::AIE::DMAChannelDirAttr	DMA Channel direction
channel	::mlir::IntegerAttr	32-bit signless integer attribute
issue_token	::mlir::BoolAttr	bool attribute
repeat_count	::mlir::IntegerAttr	32-bit signless integer attribute
bd_id	::mlir::IntegerAttr	32-bit signless integer attribute

aiex.npu.rtp_write (::xilinx::AIEX::NpuWriteRTPOp)

Rtp write operator

Syntax:

operation ::= `aiex.npu.rtp_write` `(` $buffer `,` $index `,` $value `)` attr-dict

rtp write operator

Attributes:

Attribute	MLIR Type	Description
buffer	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
index	::mlir::IntegerAttr	32-bit unsigned integer attribute
value	::mlir::IntegerAttr	32-bit signless integer attribute

aiex.npu.sync (::xilinx::AIEX::NpuSyncOp)

Sync operator

Syntax:

operation ::= `aiex.npu.sync` attr-dict

The sync operation blocks execution of the instruction stream until a task-complete token (TCT) is received on column, row, channel channel, direction direction (where 0 is S2MM and 1 is MM2S).

Troubleshooting

If this operation appears to deadlock, ensure that at least one buffer descriptor is configured to issue a TCT on the channel you expect. By default, dma_memcpy_nd operations only issue tokens for S2MM channels, and issue_token must be set to true to issue tokens for MM2S channels.

Attributes:

Attribute	MLIR Type	Description
column	::mlir::IntegerAttr	32-bit signless integer attribute
row	::mlir::IntegerAttr	32-bit signless integer attribute
direction	::mlir::IntegerAttr	32-bit signless integer attribute
channel	::mlir::IntegerAttr	32-bit signless integer attribute
column_num	::mlir::IntegerAttr	32-bit signless integer attribute
row_num	::mlir::IntegerAttr	32-bit signless integer attribute

aiex.npu.write32 (::xilinx::AIEX::NpuWrite32Op)

Write32 operator

Syntax:

operation ::= `aiex.npu.write32` attr-dict

NPU write32 operator writes a 32bit value to the AIE array. If ‘buffer’ is present then ‘address’ is interpreted as an offset into the aie.buffer with symbol name ‘buffer’. If ‘column’ and ‘row’ are present then ‘address’ is interpreted as an offset into the memory space of aie.tile(column, row). If ‘buffer’ is not present and ‘column’ and ‘row’ are not present then ‘address’ is interpreted as a full 32-bit address in the AIE array.

Attributes:

Attribute	MLIR Type	Description
address	::mlir::IntegerAttr	32-bit unsigned integer attribute
value	::mlir::IntegerAttr	32-bit unsigned integer attribute
buffer	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
column	::mlir::IntegerAttr	32-bit signless integer attribute
row	::mlir::IntegerAttr	32-bit signless integer attribute

aiex.npu.writebd (::xilinx::AIEX::NpuWriteBdOp)

Dma operator

Syntax:

operation ::= `aiex.npu.writebd` attr-dict

writebd operator

Attributes:

Attribute	MLIR Type	Description
column	::mlir::IntegerAttr	32-bit signless integer attribute
bd_id	::mlir::IntegerAttr	32-bit signless integer attribute
buffer_length	::mlir::IntegerAttr	32-bit signless integer attribute
buffer_offset	::mlir::IntegerAttr	32-bit signless integer attribute
enable_packet	::mlir::IntegerAttr	32-bit signless integer attribute
out_of_order_id	::mlir::IntegerAttr	32-bit signless integer attribute
packet_id	::mlir::IntegerAttr	32-bit signless integer attribute
packet_type	::mlir::IntegerAttr	32-bit signless integer attribute
d0_size	::mlir::IntegerAttr	32-bit signless integer attribute
d0_stride	::mlir::IntegerAttr	32-bit signless integer attribute
d1_size	::mlir::IntegerAttr	32-bit signless integer attribute
d1_stride	::mlir::IntegerAttr	32-bit signless integer attribute
d2_size	::mlir::IntegerAttr	32-bit signless integer attribute
d2_stride	::mlir::IntegerAttr	32-bit signless integer attribute
iteration_current	::mlir::IntegerAttr	32-bit signless integer attribute
iteration_size	::mlir::IntegerAttr	32-bit signless integer attribute
iteration_stride	::mlir::IntegerAttr	32-bit signless integer attribute
next_bd	::mlir::IntegerAttr	32-bit signless integer attribute
row	::mlir::IntegerAttr	32-bit signless integer attribute
use_next_bd	::mlir::IntegerAttr	32-bit signless integer attribute
valid_bd	::mlir::IntegerAttr	32-bit signless integer attribute
lock_rel_val	::mlir::IntegerAttr	32-bit signless integer attribute
lock_rel_id	::mlir::IntegerAttr	32-bit signless integer attribute
lock_acq_enable	::mlir::IntegerAttr	32-bit signless integer attribute
lock_acq_val	::mlir::IntegerAttr	32-bit signless integer attribute
lock_acq_id	::mlir::IntegerAttr	32-bit signless integer attribute
d0_zero_before	::mlir::IntegerAttr	32-bit signless integer attribute
d1_zero_before	::mlir::IntegerAttr	32-bit signless integer attribute
d2_zero_before	::mlir::IntegerAttr	32-bit signless integer attribute
d0_zero_after	::mlir::IntegerAttr	32-bit signless integer attribute
d1_zero_after	::mlir::IntegerAttr	32-bit signless integer attribute
d2_zero_after	::mlir::IntegerAttr	32-bit signless integer attribute
burst_length	::mlir::IntegerAttr	32-bit signless integer attribute

aiex.place (::xilinx::AIEX::PlaceOp)

A place operation that specifies the relative placement (XY) of one herd to another

Syntax:

operation ::= `aiex.place` `(` $sourceHerd `,` $destHerd `,` $distX `,` $distY `)` attr-dict

A place operation that specifies the relative placement (XY) of one herd to another.

Attributes:

Attribute	MLIR Type	Description
distX	::mlir::IntegerAttr	32-bit signless integer attribute
distY	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
sourceHerd	index
destHerd	index

aiex.route (::xilinx::AIEX::RouteOp)

A route operation that routes one herd to another

Syntax:

operation ::= `aiex.route` `(` `<` $sourceHerds `,` $sourceBundle `:` $sourceChannel `>` `,`
              `<` $destHerds   `,` $destBundle   `:` $destChannel   `>` `)` attr-dict

A route operation that routes one herd to another.

Attributes:

Attribute	MLIR Type	Description
sourceBundle	xilinx::AIE::WireBundleAttr	Bundle of wires
sourceChannel	::mlir::IntegerAttr	32-bit signless integer attribute
destBundle	xilinx::AIE::WireBundleAttr	Bundle of wires
destChannel	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
sourceHerds	index
destHerds	index

aiex.run (::xilinx::AIEX::RunOp)

Execute a runtime sequence

Syntax:

operation ::= `aiex.run` $runtime_sequence_symbol `(` $args `)` `:` `(` type($args) `)` attr-dict

Executes an aiex.runtime_sequence with the given name and arguments by inlining its instructions at the call site.

Traits: HasParent<ConfigureOp>

Attributes:

Attribute	MLIR Type	Description
runtime_sequence_symbol	::mlir::FlatSymbolRefAttr	flat symbol reference attribute

Operands:

Operand	Description
args	variadic of any type

aiex.select (::xilinx::AIEX::SelectOp)

A select operation

Syntax:

operation ::= `aiex.select` `(` $startHerd `,` $iterX `,` $iterY `)` attr-dict

This operation selects a group of tiles based on the selected indices.

Example:

%herd = AIE.herd[4][4] // a herd of 4x4 tiles

%ix = AIE.iter(0, 4, 1) // 0, 1, 2, 3 %iy = AIE.iter(0, 1, 1) // 0

%sub_herd = AIE.select(%herd, %ix, %iy)

The SelectOp in the above example will select the tiles %herd[0][0], %herd[1][0], %herd[2][0], %herd[3][0] (the first column of the herd).

Operands:

Operand	Description
startHerd	index
iterX	index
iterY	index

Results:

Result	Description
«unnamed»	index

aiex.set_lock (::xilinx::AIEX::SetLockOp)

Set the value of a lock

Syntax:

operation ::= `aiex.set_lock` `(` $lock `,` $value `)` attr-dict

This operation sets the value of lock inside of a RuntimeSequenceOp. The operation is non blocking and does not offer any synchronization guarantees. Should be used in combination with blocking operations.

Example:

  %tile22 = aie.tile(2, 2)
  %lock22_0 = aie.lock(%tile22, 0)
  ...
  aiex.set_lock(%lock22_0, 5)

Traits: HasParent<AIE::RuntimeSequenceOp>, SkipAccessibilityCheckTrait

Attributes:

Attribute	MLIR Type	Description
value	::mlir::IntegerAttr	32-bit signless integer attribute

Operands:

Operand	Description
lock	index

aiex.token (::xilinx::AIEX::TokenOp)

Declare a token (a logical lock)

Syntax:

operation ::= `aiex.token` `(` $value `)` attr-dict

This operation creates a logical lock. We use Symbol so that it can be referenced globally. Unlike phsical locks, logical locks are unlimited, and we can specify any integer value associated with a lock. The logical lock is used to manually specify the dependence of tasks, or core executions.

The operation can also be generated automatically if the Dependence Analysis can be leveraged.

Example: AIE.token(0) {sym_name = “token0”} // Declare token0 with initial value of 0

…

AIE.useToken @token0(“Acquire”, 0) // acquire token0 if its value is 0

…

AIE.useToken @token0(“Release”, 5) // release token0 and set its value to 5

Interfaces: Symbol

Attributes:

Attribute	MLIR Type	Description
value	::mlir::IntegerAttr	32-bit signless integer attribute

aiex.useToken (::xilinx::AIEX::UseTokenOp)

Acquire/release a logical lock

Syntax:

operation ::= `aiex.useToken` $tokenName `(` $action `,` $value `)` attr-dict

This operation uses token (logical lock). A logical lock can be acquired or released with a value. Similar to UseLockOp, this operation can be understood as “blocking” op.

Attributes:

Attribute	MLIR Type	Description
tokenName	::mlir::FlatSymbolRefAttr	flat symbol reference attribute
value	::mlir::IntegerAttr	32-bit signless integer attribute
action	xilinx::AIE::LockActionAttr	lock acquire/release

Types

BlockFloatType

AIEX type representing a block floating point type.

Syntax:

!aiex.bfp<
  ::llvm::StringRef   # block_type
>

This is a type representing a block floating point. It is meant to eventually be lowered into a standard type further down the pipeline. It the meantime, it can be used for blocked fp related dataflow adaptations. Available types are v8bfp16ebs8 and v16bfp16ebs16.

Parameters:

Parameter	C++ type	Description
block_type	::llvm::StringRef

Enums

AIEArch

AIE Architecture

Cases:

Symbol	Value	String
AIE1	1	AIE1
AIE2	2	AIE2
AIE2p	3	AIE2p

AIEDevice

AIE Device

Cases:

Symbol	Value	String
xcvc1902	1	xcvc1902
xcve2302	2	xcve2302
xcve2802	3	xcve2802
npu1	4	npu1
npu1_1col	5	npu1_1col
npu1_2col	6	npu1_2col
npu1_3col	7	npu1_3col
npu2	8	npu2
npu2_1col	9	npu2_1col
npu2_2col	10	npu2_2col
npu2_3col	11	npu2_3col
npu2_4col	12	npu2_4col
npu2_5col	13	npu2_5col
npu2_6col	14	npu2_6col
npu2_7col	15	npu2_7col

CascadeDir

Directions for cascade

Cases:

Symbol	Value	String
South	3	South
West	4	West
North	5	North
East	6	East

CoreEvent

Core module event enumeration for AIE

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
PERF_CNT_2	7	PERF_CNT_2
PERF_CNT_3	8	PERF_CNT_3
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
GROUP_PC_EVENT	15	GROUP_PC_EVENT
PC_0	16	PC_0
PC_1	17	PC_1
PC_2	18	PC_2
PC_3	19	PC_3
PC_RANGE_0_1	20	PC_RANGE_0_1
PC_RANGE_2_3	21	PC_RANGE_2_3
GROUP_STALL	22	GROUP_STALL
MEMORY_STALL	23	MEMORY_STALL
STREAM_STALL	24	STREAM_STALL
CASCADE_STALL	25	CASCADE_STALL
LOCK_STALL	26	LOCK_STALL
DEBUG_HALTED	27	DEBUG_HALTED
ACTIVE	28	ACTIVE
DISABLED	29	DISABLED
ECC_ERROR_STALL	30	ECC_ERROR_STALL
ECC_SCRUBBING_STALL	31	ECC_SCRUBBING_STALL
GROUP_PROGRAM_FLOW	32	GROUP_PROGRAM_FLOW
INSTR_EVENT_0	33	INSTR_EVENT_0
INSTR_EVENT_1	34	INSTR_EVENT_1
INSTR_CALL	35	INSTR_CALL
INSTR_RETURN	36	INSTR_RETURN
INSTR_VECTOR	37	INSTR_VECTOR
INSTR_LOAD	38	INSTR_LOAD
INSTR_STORE	39	INSTR_STORE
INSTR_STREAM_GET	40	INSTR_STREAM_GET
INSTR_STREAM_PUT	41	INSTR_STREAM_PUT
INSTR_CASCADE_GET	42	INSTR_CASCADE_GET
INSTR_CASCADE_PUT	43	INSTR_CASCADE_PUT
INSTR_LOCK_ACQUIRE_REQ	44	INSTR_LOCK_ACQUIRE_REQ
INSTR_LOCK_RELEASE_REQ	45	INSTR_LOCK_RELEASE_REQ
GROUP_ERRORS_0	46	GROUP_ERRORS_0
GROUP_ERRORS_1	47	GROUP_ERRORS_1
SRS_SATURATE	48	SRS_SATURATE
UPS_SATURATE	49	UPS_SATURATE
FP_OVERFLOW	50	FP_OVERFLOW
FP_UNDERFLOW	51	FP_UNDERFLOW
FP_INVALID	52	FP_INVALID
FP_DIV_BY_ZERO	53	FP_DIV_BY_ZERO
TLAST_IN_WSS_WORDS_0_2	54	TLAST_IN_WSS_WORDS_0_2
PM_REG_ACCESS_FAILURE	55	PM_REG_ACCESS_FAILURE
STREAM_PKT_PARITY_ERROR	56	STREAM_PKT_PARITY_ERROR
CONTROL_PKT_ERROR	57	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	58	AXI_MM_SLAVE_ERROR
INSTR_DECOMPRSN_ERROR	59	INSTR_DECOMPRSN_ERROR
DM_ADDRESS_OUT_OF_RANGE	60	DM_ADDRESS_OUT_OF_RANGE
PM_ECC_ERROR_SCRUB_CORRECTED	61	PM_ECC_ERROR_SCRUB_CORRECTED
PM_ECC_ERROR_SCRUB_2BIT	62	PM_ECC_ERROR_SCRUB_2BIT
PM_ECC_ERROR_1BIT	63	PM_ECC_ERROR_1BIT
PM_ECC_ERROR_2BIT	64	PM_ECC_ERROR_2BIT
PM_ADDRESS_OUT_OF_RANGE	65	PM_ADDRESS_OUT_OF_RANGE
DM_ACCESS_TO_UNAVAILABLE	66	DM_ACCESS_TO_UNAVAILABLE
LOCK_ACCESS_TO_UNAVAILABLE	67	LOCK_ACCESS_TO_UNAVAILABLE
INSTR_EVENT_2	68	INSTR_EVENT_2
INSTR_EVENT_3	69	INSTR_EVENT_3
GROUP_STREAM_SWITCH	73	GROUP_STREAM_SWITCH
PORT_IDLE_0	74	PORT_IDLE_0
PORT_RUNNING_0	75	PORT_RUNNING_0
PORT_STALLED_0	76	PORT_STALLED_0
PORT_TLAST_0	77	PORT_TLAST_0
PORT_IDLE_1	78	PORT_IDLE_1
PORT_RUNNING_1	79	PORT_RUNNING_1
PORT_STALLED_1	80	PORT_STALLED_1
PORT_TLAST_1	81	PORT_TLAST_1
PORT_IDLE_2	82	PORT_IDLE_2
PORT_RUNNING_2	83	PORT_RUNNING_2
PORT_STALLED_2	84	PORT_STALLED_2
PORT_TLAST_2	85	PORT_TLAST_2
PORT_IDLE_3	86	PORT_IDLE_3
PORT_RUNNING_3	87	PORT_RUNNING_3
PORT_STALLED_3	88	PORT_STALLED_3
PORT_TLAST_3	89	PORT_TLAST_3
PORT_IDLE_4	90	PORT_IDLE_4
PORT_RUNNING_4	91	PORT_RUNNING_4
PORT_STALLED_4	92	PORT_STALLED_4
PORT_TLAST_4	93	PORT_TLAST_4
PORT_IDLE_5	94	PORT_IDLE_5
PORT_RUNNING_5	95	PORT_RUNNING_5
PORT_STALLED_5	96	PORT_STALLED_5
PORT_TLAST_5	97	PORT_TLAST_5
PORT_IDLE_6	98	PORT_IDLE_6
PORT_RUNNING_6	99	PORT_RUNNING_6
PORT_STALLED_6	100	PORT_STALLED_6
PORT_TLAST_6	101	PORT_TLAST_6
PORT_IDLE_7	102	PORT_IDLE_7
PORT_RUNNING_7	103	PORT_RUNNING_7
PORT_STALLED_7	104	PORT_STALLED_7
PORT_TLAST_7	105	PORT_TLAST_7
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

CoreEventAIE2

Core module event enumeration for AIE2

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
PERF_CNT_2	7	PERF_CNT_2
PERF_CNT_3	8	PERF_CNT_3
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	13	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	14	EDGE_DETECTION_EVENT_1
GROUP_PC_EVENT	15	GROUP_PC_EVENT
PC_0	16	PC_0
PC_1	17	PC_1
PC_2	18	PC_2
PC_3	19	PC_3
PC_RANGE_0_1	20	PC_RANGE_0_1
PC_RANGE_2_3	21	PC_RANGE_2_3
GROUP_STALL	22	GROUP_STALL
MEMORY_STALL	23	MEMORY_STALL
STREAM_STALL	24	STREAM_STALL
CASCADE_STALL	25	CASCADE_STALL
LOCK_STALL	26	LOCK_STALL
DEBUG_HALTED	27	DEBUG_HALTED
ACTIVE	28	ACTIVE
DISABLED	29	DISABLED
ECC_ERROR_STALL	30	ECC_ERROR_STALL
ECC_SCRUBBING_STALL	31	ECC_SCRUBBING_STALL
GROUP_PROGRAM_FLOW	32	GROUP_PROGRAM_FLOW
INSTR_EVENT_0	33	INSTR_EVENT_0
INSTR_EVENT_1	34	INSTR_EVENT_1
INSTR_CALL	35	INSTR_CALL
INSTR_RETURN	36	INSTR_RETURN
INSTR_VECTOR	37	INSTR_VECTOR
INSTR_LOAD	38	INSTR_LOAD
INSTR_STORE	39	INSTR_STORE
INSTR_STREAM_GET	40	INSTR_STREAM_GET
INSTR_STREAM_PUT	41	INSTR_STREAM_PUT
INSTR_CASCADE_GET	42	INSTR_CASCADE_GET
INSTR_CASCADE_PUT	43	INSTR_CASCADE_PUT
INSTR_LOCK_ACQUIRE_REQ	44	INSTR_LOCK_ACQUIRE_REQ
INSTR_LOCK_RELEASE_REQ	45	INSTR_LOCK_RELEASE_REQ
GROUP_ERRORS_0	46	GROUP_ERRORS_0
GROUP_ERRORS_1	47	GROUP_ERRORS_1
SRS_OVERFLOW	48	SRS_OVERFLOW
UPS_OVERFLOW	49	UPS_OVERFLOW
FP_HUGE	50	FP_HUGE
INT_FP_0	51	INT_FP_0
FP_INVALID	52	FP_INVALID
FP_INF	53	FP_INF
PM_REG_ACCESS_FAILURE	55	PM_REG_ACCESS_FAILURE
STREAM_PKT_PARITY_ERROR	56	STREAM_PKT_PARITY_ERROR
CONTROL_PKT_ERROR	57	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	58	AXI_MM_SLAVE_ERROR
INSTR_DECOMPRSN_ERROR	59	INSTR_DECOMPRSN_ERROR
DM_ADDRESS_OUT_OF_RANGE	60	DM_ADDRESS_OUT_OF_RANGE
PM_ECC_ERROR_SCRUB_CORRECTED	61	PM_ECC_ERROR_SCRUB_CORRECTED
PM_ECC_ERROR_SCRUB_2BIT	62	PM_ECC_ERROR_SCRUB_2BIT
PM_ECC_ERROR_1BIT	63	PM_ECC_ERROR_1BIT
PM_ECC_ERROR_2BIT	64	PM_ECC_ERROR_2BIT
PM_ADDRESS_OUT_OF_RANGE	65	PM_ADDRESS_OUT_OF_RANGE
DM_ACCESS_TO_UNAVAILABLE	66	DM_ACCESS_TO_UNAVAILABLE
LOCK_ACCESS_TO_UNAVAILABLE	67	LOCK_ACCESS_TO_UNAVAILABLE
INSTR_WARNING	68	INSTR_WARNING
INSTR_ERROR	69	INSTR_ERROR
DECOMPRESSION_UNDERFLOW	70	DECOMPRESSION_UNDERFLOW
STREAM_SWITCH_PORT_PARITY_ERROR	71	STREAM_SWITCH_PORT_PARITY_ERROR
PROCESSOR_BUS_ERROR	72	PROCESSOR_BUS_ERROR
GROUP_STREAM_SWITCH	73	GROUP_STREAM_SWITCH
PORT_IDLE_0	74	PORT_IDLE_0
PORT_RUNNING_0	75	PORT_RUNNING_0
PORT_STALLED_0	76	PORT_STALLED_0
PORT_TLAST_0	77	PORT_TLAST_0
PORT_IDLE_1	78	PORT_IDLE_1
PORT_RUNNING_1	79	PORT_RUNNING_1
PORT_STALLED_1	80	PORT_STALLED_1
PORT_TLAST_1	81	PORT_TLAST_1
PORT_IDLE_2	82	PORT_IDLE_2
PORT_RUNNING_2	83	PORT_RUNNING_2
PORT_STALLED_2	84	PORT_STALLED_2
PORT_TLAST_2	85	PORT_TLAST_2
PORT_IDLE_3	86	PORT_IDLE_3
PORT_RUNNING_3	87	PORT_RUNNING_3
PORT_STALLED_3	88	PORT_STALLED_3
PORT_TLAST_3	89	PORT_TLAST_3
PORT_IDLE_4	90	PORT_IDLE_4
PORT_RUNNING_4	91	PORT_RUNNING_4
PORT_STALLED_4	92	PORT_STALLED_4
PORT_TLAST_4	93	PORT_TLAST_4
PORT_IDLE_5	94	PORT_IDLE_5
PORT_RUNNING_5	95	PORT_RUNNING_5
PORT_STALLED_5	96	PORT_STALLED_5
PORT_TLAST_5	97	PORT_TLAST_5
PORT_IDLE_6	98	PORT_IDLE_6
PORT_RUNNING_6	99	PORT_RUNNING_6
PORT_STALLED_6	100	PORT_STALLED_6
PORT_TLAST_6	101	PORT_TLAST_6
PORT_IDLE_7	102	PORT_IDLE_7
PORT_RUNNING_7	103	PORT_RUNNING_7
PORT_STALLED_7	104	PORT_STALLED_7
PORT_TLAST_7	105	PORT_TLAST_7
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

CoreEventAIE2P

Core module event enumeration for AIE2P

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
PERF_CNT_2	7	PERF_CNT_2
PERF_CNT_3	8	PERF_CNT_3
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	13	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	14	EDGE_DETECTION_EVENT_1
GROUP_PC_EVENT	15	GROUP_PC_EVENT
PC_0	16	PC_0
PC_1	17	PC_1
PC_2	18	PC_2
PC_3	19	PC_3
PC_RANGE_0_1	20	PC_RANGE_0_1
PC_RANGE_2_3	21	PC_RANGE_2_3
GROUP_STALL	22	GROUP_STALL
MEMORY_STALL	23	MEMORY_STALL
STREAM_STALL	24	STREAM_STALL
CASCADE_STALL	25	CASCADE_STALL
LOCK_STALL	26	LOCK_STALL
DEBUG_HALTED	27	DEBUG_HALTED
ACTIVE	28	ACTIVE
DISABLED	29	DISABLED
ECC_ERROR_STALL	30	ECC_ERROR_STALL
ECC_SCRUBBING_STALL	31	ECC_SCRUBBING_STALL
GROUP_PROGRAM_FLOW	32	GROUP_PROGRAM_FLOW
INSTR_EVENT_0	33	INSTR_EVENT_0
INSTR_EVENT_1	34	INSTR_EVENT_1
INSTR_CALL	35	INSTR_CALL
INSTR_RETURN	36	INSTR_RETURN
INSTR_VECTOR	37	INSTR_VECTOR
INSTR_LOAD	38	INSTR_LOAD
INSTR_STORE	39	INSTR_STORE
INSTR_STREAM_GET	40	INSTR_STREAM_GET
INSTR_STREAM_PUT	41	INSTR_STREAM_PUT
INSTR_CASCADE_GET	42	INSTR_CASCADE_GET
INSTR_CASCADE_PUT	43	INSTR_CASCADE_PUT
INSTR_LOCK_ACQUIRE_REQ	44	INSTR_LOCK_ACQUIRE_REQ
INSTR_LOCK_RELEASE_REQ	45	INSTR_LOCK_RELEASE_REQ
GROUP_ERRORS_0	46	GROUP_ERRORS_0
GROUP_ERRORS_1	47	GROUP_ERRORS_1
SRS_OVERFLOW	48	SRS_OVERFLOW
UPS_OVERFLOW	49	UPS_OVERFLOW
FP_HUGE	50	FP_HUGE
INT_FP_0	51	INT_FP_0
FP_INVALID	52	FP_INVALID
FP_INF	53	FP_INF
PM_REG_ACCESS_FAILURE	55	PM_REG_ACCESS_FAILURE
STREAM_PKT_PARITY_ERROR	56	STREAM_PKT_PARITY_ERROR
CONTROL_PKT_ERROR	57	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	58	AXI_MM_SLAVE_ERROR
INSTR_DECOMPRSN_ERROR	59	INSTR_DECOMPRSN_ERROR
DM_ADDRESS_OUT_OF_RANGE	60	DM_ADDRESS_OUT_OF_RANGE
PM_ECC_ERROR_SCRUB_CORRECTED	61	PM_ECC_ERROR_SCRUB_CORRECTED
PM_ECC_ERROR_SCRUB_2BIT	62	PM_ECC_ERROR_SCRUB_2BIT
PM_ECC_ERROR_1BIT	63	PM_ECC_ERROR_1BIT
PM_ECC_ERROR_2BIT	64	PM_ECC_ERROR_2BIT
PM_ADDRESS_OUT_OF_RANGE	65	PM_ADDRESS_OUT_OF_RANGE
DM_ACCESS_TO_UNAVAILABLE	66	DM_ACCESS_TO_UNAVAILABLE
LOCK_ACCESS_TO_UNAVAILABLE	67	LOCK_ACCESS_TO_UNAVAILABLE
INSTR_WARNING	68	INSTR_WARNING
INSTR_ERROR	69	INSTR_ERROR
SPARSITY_OVERFLOW	70	SPARSITY_OVERFLOW
STREAM_SWITCH_PORT_PARITY_ERROR	71	STREAM_SWITCH_PORT_PARITY_ERROR
PROCESSOR_BUS_ERROR	72	PROCESSOR_BUS_ERROR
GROUP_STREAM_SWITCH	73	GROUP_STREAM_SWITCH
PORT_IDLE_0	74	PORT_IDLE_0
PORT_RUNNING_0	75	PORT_RUNNING_0
PORT_STALLED_0	76	PORT_STALLED_0
PORT_TLAST_0	77	PORT_TLAST_0
PORT_IDLE_1	78	PORT_IDLE_1
PORT_RUNNING_1	79	PORT_RUNNING_1
PORT_STALLED_1	80	PORT_STALLED_1
PORT_TLAST_1	81	PORT_TLAST_1
PORT_IDLE_2	82	PORT_IDLE_2
PORT_RUNNING_2	83	PORT_RUNNING_2
PORT_STALLED_2	84	PORT_STALLED_2
PORT_TLAST_2	85	PORT_TLAST_2
PORT_IDLE_3	86	PORT_IDLE_3
PORT_RUNNING_3	87	PORT_RUNNING_3
PORT_STALLED_3	88	PORT_STALLED_3
PORT_TLAST_3	89	PORT_TLAST_3
PORT_IDLE_4	90	PORT_IDLE_4
PORT_RUNNING_4	91	PORT_RUNNING_4
PORT_STALLED_4	92	PORT_STALLED_4
PORT_TLAST_4	93	PORT_TLAST_4
PORT_IDLE_5	94	PORT_IDLE_5
PORT_RUNNING_5	95	PORT_RUNNING_5
PORT_STALLED_5	96	PORT_STALLED_5
PORT_TLAST_5	97	PORT_TLAST_5
PORT_IDLE_6	98	PORT_IDLE_6
PORT_RUNNING_6	99	PORT_RUNNING_6
PORT_STALLED_6	100	PORT_STALLED_6
PORT_TLAST_6	101	PORT_TLAST_6
PORT_IDLE_7	102	PORT_IDLE_7
PORT_RUNNING_7	103	PORT_RUNNING_7
PORT_STALLED_7	104	PORT_STALLED_7
PORT_TLAST_7	105	PORT_TLAST_7
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

DMAChannelDir

DMA Channel direction

Cases:

Symbol	Value	String
S2MM	0	S2MM
MM2S	1	MM2S

LockAction

Lock acquire/release

Cases:

Symbol	Value	String
Acquire	0	Acquire
AcquireGreaterEqual	2	AcquireGreaterEqual
Release	1	Release

LockBlocking

Lock operation is blocking

Cases:

Symbol	Value	String
NonBlocking	0	NonBlocking
Blocking	1	Blocking

MemEvent

Memory module event enumeration for AIE

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
GROUP_DMA_ACTIVITY	20	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_BD	21	DMA_S2MM_0_START_BD
DMA_S2MM_1_START_BD	22	DMA_S2MM_1_START_BD
DMA_MM2S_0_START_BD	23	DMA_MM2S_0_START_BD
DMA_MM2S_1_START_BD	24	DMA_MM2S_1_START_BD
DMA_S2MM_0_FINISHED_BD	25	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	26	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	27	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	28	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_GO_TO_IDLE	29	DMA_S2MM_0_GO_TO_IDLE
DMA_S2MM_1_GO_TO_IDLE	30	DMA_S2MM_1_GO_TO_IDLE
DMA_MM2S_0_GO_TO_IDLE	31	DMA_MM2S_0_GO_TO_IDLE
DMA_MM2S_1_GO_TO_IDLE	32	DMA_MM2S_1_GO_TO_IDLE
DMA_S2MM_0_STALLED_LOCK_ACQUIRE	33	DMA_S2MM_0_STALLED_LOCK_ACQUIRE
DMA_S2MM_1_STALLED_LOCK_ACQUIRE	34	DMA_S2MM_1_STALLED_LOCK_ACQUIRE
DMA_MM2S_0_STALLED_LOCK_ACQUIRE	35	DMA_MM2S_0_STALLED_LOCK_ACQUIRE
DMA_MM2S_1_STALLED_LOCK_ACQUIRE	36	DMA_MM2S_1_STALLED_LOCK_ACQUIRE
DMA_S2MM_0_MEMORY_CONFLICT	37	DMA_S2MM_0_MEMORY_CONFLICT
DMA_S2MM_1_MEMORY_CONFLICT	38	DMA_S2MM_1_MEMORY_CONFLICT
DMA_MM2S_0_MEMORY_CONFLICT	39	DMA_MM2S_0_MEMORY_CONFLICT
DMA_MM2S_1_MEMORY_CONFLICT	40	DMA_MM2S_1_MEMORY_CONFLICT
GROUP_LOCK	43	GROUP_LOCK
LOCK_0_ACQ	44	LOCK_0_ACQ
LOCK_0_REL	45	LOCK_0_REL
LOCK_1_ACQ	46	LOCK_1_ACQ
LOCK_1_REL	47	LOCK_1_REL
LOCK_2_ACQ	48	LOCK_2_ACQ
LOCK_2_REL	49	LOCK_2_REL
LOCK_3_ACQ	50	LOCK_3_ACQ
LOCK_3_REL	51	LOCK_3_REL
LOCK_4_ACQ	52	LOCK_4_ACQ
LOCK_4_REL	53	LOCK_4_REL
LOCK_5_ACQ	54	LOCK_5_ACQ
LOCK_5_REL	55	LOCK_5_REL
LOCK_6_ACQ	56	LOCK_6_ACQ
LOCK_6_REL	57	LOCK_6_REL
LOCK_7_ACQ	58	LOCK_7_ACQ
LOCK_7_REL	59	LOCK_7_REL
LOCK_8_ACQ	60	LOCK_8_ACQ
LOCK_8_REL	61	LOCK_8_REL
LOCK_9_ACQ	62	LOCK_9_ACQ
LOCK_9_REL	63	LOCK_9_REL
LOCK_10_ACQ	64	LOCK_10_ACQ
LOCK_10_REL	65	LOCK_10_REL
LOCK_11_ACQ	66	LOCK_11_ACQ
LOCK_11_REL	67	LOCK_11_REL
LOCK_12_ACQ	68	LOCK_12_ACQ
LOCK_12_REL	69	LOCK_12_REL
LOCK_13_ACQ	70	LOCK_13_ACQ
LOCK_13_REL	71	LOCK_13_REL
LOCK_14_ACQ	72	LOCK_14_ACQ
LOCK_14_REL	73	LOCK_14_REL
LOCK_15_ACQ	74	LOCK_15_ACQ
LOCK_15_REL	75	LOCK_15_REL
GROUP_MEMORY_CONFLICT	76	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	77	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	78	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	79	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	80	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	81	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	82	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	83	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	84	CONFLICT_DM_BANK_7
GROUP_ERRORS	86	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	87	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	88	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	89	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	90	DM_ECC_ERROR_2BIT
DM_PARITY_ERROR_BANK_2	91	DM_PARITY_ERROR_BANK_2
DM_PARITY_ERROR_BANK_3	92	DM_PARITY_ERROR_BANK_3
DM_PARITY_ERROR_BANK_4	93	DM_PARITY_ERROR_BANK_4
DM_PARITY_ERROR_BANK_5	94	DM_PARITY_ERROR_BANK_5
DM_PARITY_ERROR_BANK_6	95	DM_PARITY_ERROR_BANK_6
DM_PARITY_ERROR_BANK_7	96	DM_PARITY_ERROR_BANK_7
DMA_S2MM_0_ERROR	97	DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR	98	DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR	99	DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR	100	DMA_MM2S_1_ERROR
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

MemEventAIE2

Memory module event enumeration for AIE2

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	11	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	12	EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
GROUP_DMA_ACTIVITY	18	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK	19	DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK	20	DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK	21	DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK	22	DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD	23	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	24	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	25	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	26	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK	27	DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK	28	DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK	29	DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK	30	DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK	31	DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK	32	DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK	33	DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK	34	DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION	35	DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION	36	DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE	37	DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE	38	DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE	39	DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE	40	DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION	41	DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION	42	DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK	43	GROUP_LOCK
LOCK_SEL0_ACQ_EQ	44	LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE	45	LOCK_SEL0_ACQ_GE
LOCK_0_REL	46	LOCK_0_REL
LOCK_SEL0_EQUAL_TO_VALUE	47	LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ	48	LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE	49	LOCK_SEL1_ACQ_GE
LOCK_1_REL	50	LOCK_1_REL
LOCK_SEL1_EQUAL_TO_VALUE	51	LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ	52	LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE	53	LOCK_SEL2_ACQ_GE
LOCK_2_REL	54	LOCK_2_REL
LOCK_SEL2_EQUAL_TO_VALUE	55	LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ	56	LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE	57	LOCK_SEL3_ACQ_GE
LOCK_3_REL	58	LOCK_3_REL
LOCK_SEL3_EQUAL_TO_VALUE	59	LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ	60	LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE	61	LOCK_SEL4_ACQ_GE
LOCK_4_REL	62	LOCK_4_REL
LOCK_SEL4_EQUAL_TO_VALUE	63	LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ	64	LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE	65	LOCK_SEL5_ACQ_GE
LOCK_5_REL	66	LOCK_5_REL
LOCK_SEL5_EQUAL_TO_VALUE	67	LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ	68	LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE	69	LOCK_SEL6_ACQ_GE
LOCK_6_REL	70	LOCK_6_REL
LOCK_SEL6_EQUAL_TO_VALUE	71	LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ	72	LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE	73	LOCK_SEL7_ACQ_GE
LOCK_7_REL	74	LOCK_7_REL
LOCK_SEL7_EQUAL_TO_VALUE	75	LOCK_SEL7_EQUAL_TO_VALUE
GROUP_MEMORY_CONFLICT	76	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	77	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	78	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	79	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	80	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	81	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	82	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	83	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	84	CONFLICT_DM_BANK_7
GROUP_ERRORS	86	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	87	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	88	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	89	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	90	DM_ECC_ERROR_2BIT
DM_PARITY_ERROR_BANK_2	91	DM_PARITY_ERROR_BANK_2
DM_PARITY_ERROR_BANK_3	92	DM_PARITY_ERROR_BANK_3
DM_PARITY_ERROR_BANK_4	93	DM_PARITY_ERROR_BANK_4
DM_PARITY_ERROR_BANK_5	94	DM_PARITY_ERROR_BANK_5
DM_PARITY_ERROR_BANK_6	95	DM_PARITY_ERROR_BANK_6
DM_PARITY_ERROR_BANK_7	96	DM_PARITY_ERROR_BANK_7
DMA_S2MM_0_ERROR	97	DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR	98	DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR	99	DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR	100	DMA_MM2S_1_ERROR
LOCK_ERROR	101	LOCK_ERROR
DMA_TASK_TOKEN_STALL	102	DMA_TASK_TOKEN_STALL
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

MemEventAIE2P

Memory module event enumeration for AIE2P

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	11	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	12	EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
GROUP_DMA_ACTIVITY	18	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK	19	DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK	20	DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK	21	DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK	22	DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD	23	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	24	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	25	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	26	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK	27	DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK	28	DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK	29	DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK	30	DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK	31	DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK	32	DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK	33	DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK	34	DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION	35	DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION	36	DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE	37	DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE	38	DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE	39	DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE	40	DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION	41	DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION	42	DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK	43	GROUP_LOCK
LOCK_SEL0_ACQ_EQ	44	LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE	45	LOCK_SEL0_ACQ_GE
LOCK_0_REL	46	LOCK_0_REL
LOCK_SEL0_EQUAL_TO_VALUE	47	LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ	48	LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE	49	LOCK_SEL1_ACQ_GE
LOCK_1_REL	50	LOCK_1_REL
LOCK_SEL1_EQUAL_TO_VALUE	51	LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ	52	LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE	53	LOCK_SEL2_ACQ_GE
LOCK_2_REL	54	LOCK_2_REL
LOCK_SEL2_EQUAL_TO_VALUE	55	LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ	56	LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE	57	LOCK_SEL3_ACQ_GE
LOCK_3_REL	58	LOCK_3_REL
LOCK_SEL3_EQUAL_TO_VALUE	59	LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ	60	LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE	61	LOCK_SEL4_ACQ_GE
LOCK_4_REL	62	LOCK_4_REL
LOCK_SEL4_EQUAL_TO_VALUE	63	LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ	64	LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE	65	LOCK_SEL5_ACQ_GE
LOCK_5_REL	66	LOCK_5_REL
LOCK_SEL5_EQUAL_TO_VALUE	67	LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ	68	LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE	69	LOCK_SEL6_ACQ_GE
LOCK_6_REL	70	LOCK_6_REL
LOCK_SEL6_EQUAL_TO_VALUE	71	LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ	72	LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE	73	LOCK_SEL7_ACQ_GE
LOCK_7_REL	74	LOCK_7_REL
LOCK_SEL7_EQUAL_TO_VALUE	75	LOCK_SEL7_EQUAL_TO_VALUE
GROUP_MEMORY_CONFLICT	76	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	77	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	78	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	79	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	80	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	81	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	82	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	83	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	84	CONFLICT_DM_BANK_7
GROUP_ERRORS	86	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	87	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	88	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	89	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	90	DM_ECC_ERROR_2BIT
DM_PARITY_ERROR_BANK_2	91	DM_PARITY_ERROR_BANK_2
DM_PARITY_ERROR_BANK_3	92	DM_PARITY_ERROR_BANK_3
DM_PARITY_ERROR_BANK_4	93	DM_PARITY_ERROR_BANK_4
DM_PARITY_ERROR_BANK_5	94	DM_PARITY_ERROR_BANK_5
DM_PARITY_ERROR_BANK_6	95	DM_PARITY_ERROR_BANK_6
DM_PARITY_ERROR_BANK_7	96	DM_PARITY_ERROR_BANK_7
DMA_S2MM_0_ERROR	97	DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR	98	DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR	99	DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR	100	DMA_MM2S_1_ERROR
LOCK_ERROR	101	LOCK_ERROR
DMA_TASK_TOKEN_STALL	102	DMA_TASK_TOKEN_STALL
GROUP_BROADCAST	106	GROUP_BROADCAST
BROADCAST_0	107	BROADCAST_0
BROADCAST_1	108	BROADCAST_1
BROADCAST_2	109	BROADCAST_2
BROADCAST_3	110	BROADCAST_3
BROADCAST_4	111	BROADCAST_4
BROADCAST_5	112	BROADCAST_5
BROADCAST_6	113	BROADCAST_6
BROADCAST_7	114	BROADCAST_7
BROADCAST_8	115	BROADCAST_8
BROADCAST_9	116	BROADCAST_9
BROADCAST_10	117	BROADCAST_10
BROADCAST_11	118	BROADCAST_11
BROADCAST_12	119	BROADCAST_12
BROADCAST_13	120	BROADCAST_13
BROADCAST_14	121	BROADCAST_14
BROADCAST_15	122	BROADCAST_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

MemTileEvent

Memory tile event enumeration for AIE

Cases:

| Symbol | Value | String | | :—-: | :—: | —— |

MemTileEventAIE2

Memory tile event enumeration for AIE2

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT0_EVENT	5	PERF_CNT0_EVENT
PERF_CNT1_EVENT	6	PERF_CNT1_EVENT
PERF_CNT2_EVENT	7	PERF_CNT2_EVENT
PERF_CNT3_EVENT	8	PERF_CNT3_EVENT
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	13	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	14	EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
WATCHPOINT_2	18	WATCHPOINT_2
WATCHPOINT_3	19	WATCHPOINT_3
GROUP_DMA_ACTIVITY	20	GROUP_DMA_ACTIVITY
DMA_S2MM_SEL0_START_TASK	21	DMA_S2MM_SEL0_START_TASK
DMA_S2MM_SEL1_START_TASK	22	DMA_S2MM_SEL1_START_TASK
DMA_MM2S_SEL0_START_TASK	23	DMA_MM2S_SEL0_START_TASK
DMA_MM2S_SEL1_START_TASK	24	DMA_MM2S_SEL1_START_TASK
DMA_S2MM_SEL0_FINISHED_BD	25	DMA_S2MM_SEL0_FINISHED_BD
DMA_S2MM_SEL1_FINISHED_BD	26	DMA_S2MM_SEL1_FINISHED_BD
DMA_MM2S_SEL0_FINISHED_BD	27	DMA_MM2S_SEL0_FINISHED_BD
DMA_MM2S_SEL1_FINISHED_BD	28	DMA_MM2S_SEL1_FINISHED_BD
DMA_S2MM_SEL0_FINISHED_TASK	29	DMA_S2MM_SEL0_FINISHED_TASK
DMA_S2MM_SEL1_FINISHED_TASK	30	DMA_S2MM_SEL1_FINISHED_TASK
DMA_MM2S_SEL0_FINISHED_TASK	31	DMA_MM2S_SEL0_FINISHED_TASK
DMA_MM2S_SEL1_FINISHED_TASK	32	DMA_MM2S_SEL1_FINISHED_TASK
DMA_S2MM_SEL0_STALLED_LOCK	33	DMA_S2MM_SEL0_STALLED_LOCK
DMA_S2MM_SEL1_STALLED_LOCK	34	DMA_S2MM_SEL1_STALLED_LOCK
DMA_MM2S_SEL0_STALLED_LOCK	35	DMA_MM2S_SEL0_STALLED_LOCK
DMA_MM2S_SEL1_STALLED_LOCK	36	DMA_MM2S_SEL1_STALLED_LOCK
DMA_S2MM_SEL0_STREAM_STARVATION	37	DMA_S2MM_SEL0_STREAM_STARVATION
DMA_S2MM_SEL1_STREAM_STARVATION	38	DMA_S2MM_SEL1_STREAM_STARVATION
DMA_MM2S_SEL0_STREAM_BACKPRESSURE	39	DMA_MM2S_SEL0_STREAM_BACKPRESSURE
DMA_MM2S_SEL1_STREAM_BACKPRESSURE	40	DMA_MM2S_SEL1_STREAM_BACKPRESSURE
DMA_S2MM_SEL0_MEMORY_BACKPRESSURE	41	DMA_S2MM_SEL0_MEMORY_BACKPRESSURE
DMA_S2MM_SEL1_MEMORY_BACKPRESSURE	42	DMA_S2MM_SEL1_MEMORY_BACKPRESSURE
DMA_MM2S_SEL0_MEMORY_STARVATION	43	DMA_MM2S_SEL0_MEMORY_STARVATION
DMA_MM2S_SEL1_MEMORY_STARVATION	44	DMA_MM2S_SEL1_MEMORY_STARVATION
GROUP_LOCK	45	GROUP_LOCK
LOCK_SEL0_ACQ_EQ	46	LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE	47	LOCK_SEL0_ACQ_GE
LOCK_SEL0_REL	48	LOCK_SEL0_REL
LOCK_SEL0_EQUAL_TO_VALUE	49	LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ	50	LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE	51	LOCK_SEL1_ACQ_GE
LOCK_SEL1_REL	52	LOCK_SEL1_REL
LOCK_SEL1_EQUAL_TO_VALUE	53	LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ	54	LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE	55	LOCK_SEL2_ACQ_GE
LOCK_SEL2_REL	56	LOCK_SEL2_REL
LOCK_SEL2_EQUAL_TO_VALUE	57	LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ	58	LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE	59	LOCK_SEL3_ACQ_GE
LOCK_SEL3_REL	60	LOCK_SEL3_REL
LOCK_SEL3_EQUAL_TO_VALUE	61	LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ	62	LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE	63	LOCK_SEL4_ACQ_GE
LOCK_SEL4_REL	64	LOCK_SEL4_REL
LOCK_SEL4_EQUAL_TO_VALUE	65	LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ	66	LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE	67	LOCK_SEL5_ACQ_GE
LOCK_SEL5_REL	68	LOCK_SEL5_REL
LOCK_SEL5_EQUAL_TO_VALUE	69	LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ	70	LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE	71	LOCK_SEL6_ACQ_GE
LOCK_SEL6_REL	72	LOCK_SEL6_REL
LOCK_SEL6_EQUAL_TO_VALUE	73	LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ	74	LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE	75	LOCK_SEL7_ACQ_GE
LOCK_SEL7_REL	76	LOCK_SEL7_REL
LOCK_SEL7_EQUAL_TO_VALUE	77	LOCK_SEL7_EQUAL_TO_VALUE
GROUP_STREAM_SWITCH	78	GROUP_STREAM_SWITCH
PORT_IDLE_0	79	PORT_IDLE_0
PORT_RUNNING_0	80	PORT_RUNNING_0
PORT_STALLED_0	81	PORT_STALLED_0
PORT_TLAST_0	82	PORT_TLAST_0
PORT_IDLE_1	83	PORT_IDLE_1
PORT_RUNNING_1	84	PORT_RUNNING_1
PORT_STALLED_1	85	PORT_STALLED_1
PORT_TLAST_1	86	PORT_TLAST_1
PORT_IDLE_2	87	PORT_IDLE_2
PORT_RUNNING_2	88	PORT_RUNNING_2
PORT_STALLED_2	89	PORT_STALLED_2
PORT_TLAST_2	90	PORT_TLAST_2
PORT_IDLE_3	91	PORT_IDLE_3
PORT_RUNNING_3	92	PORT_RUNNING_3
PORT_STALLED_3	93	PORT_STALLED_3
PORT_TLAST_3	94	PORT_TLAST_3
PORT_IDLE_4	95	PORT_IDLE_4
PORT_RUNNING_4	96	PORT_RUNNING_4
PORT_STALLED_4	97	PORT_STALLED_4
PORT_TLAST_4	98	PORT_TLAST_4
PORT_IDLE_5	99	PORT_IDLE_5
PORT_RUNNING_5	100	PORT_RUNNING_5
PORT_STALLED_5	101	PORT_STALLED_5
PORT_TLAST_5	102	PORT_TLAST_5
PORT_IDLE_6	103	PORT_IDLE_6
PORT_RUNNING_6	104	PORT_RUNNING_6
PORT_STALLED_6	105	PORT_STALLED_6
PORT_TLAST_6	106	PORT_TLAST_6
PORT_IDLE_7	107	PORT_IDLE_7
PORT_RUNNING_7	108	PORT_RUNNING_7
PORT_STALLED_7	109	PORT_STALLED_7
PORT_TLAST_7	110	PORT_TLAST_7
GROUP_MEMORY_CONFLICT	111	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	112	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	113	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	114	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	115	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	116	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	117	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	118	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	119	CONFLICT_DM_BANK_7
CONFLICT_DM_BANK_8	120	CONFLICT_DM_BANK_8
CONFLICT_DM_BANK_9	121	CONFLICT_DM_BANK_9
CONFLICT_DM_BANK_10	122	CONFLICT_DM_BANK_10
CONFLICT_DM_BANK_11	123	CONFLICT_DM_BANK_11
CONFLICT_DM_BANK_12	124	CONFLICT_DM_BANK_12
CONFLICT_DM_BANK_13	125	CONFLICT_DM_BANK_13
CONFLICT_DM_BANK_14	126	CONFLICT_DM_BANK_14
CONFLICT_DM_BANK_15	127	CONFLICT_DM_BANK_15
GROUP_ERRORS	128	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	129	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	130	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	131	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	132	DM_ECC_ERROR_2BIT
DMA_S2MM_ERROR	133	DMA_S2MM_ERROR
DMA_MM2S_ERROR	134	DMA_MM2S_ERROR
STREAM_SWITCH_PARITY_ERROR	135	STREAM_SWITCH_PARITY_ERROR
STREAM_PKT_ERROR	136	STREAM_PKT_ERROR
CONTROL_PKT_ERROR	137	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	138	AXI_MM_SLAVE_ERROR
LOCK_ERROR	139	LOCK_ERROR
DMA_TASK_TOKEN_STALL	140	DMA_TASK_TOKEN_STALL
GROUP_BROADCAST	141	GROUP_BROADCAST
BROADCAST_0	142	BROADCAST_0
BROADCAST_1	143	BROADCAST_1
BROADCAST_2	144	BROADCAST_2
BROADCAST_3	145	BROADCAST_3
BROADCAST_4	146	BROADCAST_4
BROADCAST_5	147	BROADCAST_5
BROADCAST_6	148	BROADCAST_6
BROADCAST_7	149	BROADCAST_7
BROADCAST_8	150	BROADCAST_8
BROADCAST_9	151	BROADCAST_9
BROADCAST_10	152	BROADCAST_10
BROADCAST_11	153	BROADCAST_11
BROADCAST_12	154	BROADCAST_12
BROADCAST_13	155	BROADCAST_13
BROADCAST_14	156	BROADCAST_14
BROADCAST_15	157	BROADCAST_15
GROUP_USER_EVENT	158	GROUP_USER_EVENT
USER_EVENT_0	159	USER_EVENT_0
USER_EVENT_1	160	USER_EVENT_1

MemTileEventAIE2P

Memory tile event enumeration for AIE2P

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT0_EVENT	5	PERF_CNT0_EVENT
PERF_CNT1_EVENT	6	PERF_CNT1_EVENT
PERF_CNT2_EVENT	7	PERF_CNT2_EVENT
PERF_CNT3_EVENT	8	PERF_CNT3_EVENT
COMBO_EVENT_0	9	COMBO_EVENT_0
COMBO_EVENT_1	10	COMBO_EVENT_1
COMBO_EVENT_2	11	COMBO_EVENT_2
COMBO_EVENT_3	12	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	13	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	14	EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT	15	GROUP_WATCHPOINT
WATCHPOINT_0	16	WATCHPOINT_0
WATCHPOINT_1	17	WATCHPOINT_1
WATCHPOINT_2	18	WATCHPOINT_2
WATCHPOINT_3	19	WATCHPOINT_3
GROUP_DMA_ACTIVITY	20	GROUP_DMA_ACTIVITY
DMA_S2MM_SEL0_START_TASK	21	DMA_S2MM_SEL0_START_TASK
DMA_S2MM_SEL1_START_TASK	22	DMA_S2MM_SEL1_START_TASK
DMA_MM2S_SEL0_START_TASK	23	DMA_MM2S_SEL0_START_TASK
DMA_MM2S_SEL1_START_TASK	24	DMA_MM2S_SEL1_START_TASK
DMA_S2MM_SEL0_FINISHED_BD	25	DMA_S2MM_SEL0_FINISHED_BD
DMA_S2MM_SEL1_FINISHED_BD	26	DMA_S2MM_SEL1_FINISHED_BD
DMA_MM2S_SEL0_FINISHED_BD	27	DMA_MM2S_SEL0_FINISHED_BD
DMA_MM2S_SEL1_FINISHED_BD	28	DMA_MM2S_SEL1_FINISHED_BD
DMA_S2MM_SEL0_FINISHED_TASK	29	DMA_S2MM_SEL0_FINISHED_TASK
DMA_S2MM_SEL1_FINISHED_TASK	30	DMA_S2MM_SEL1_FINISHED_TASK
DMA_MM2S_SEL0_FINISHED_TASK	31	DMA_MM2S_SEL0_FINISHED_TASK
DMA_MM2S_SEL1_FINISHED_TASK	32	DMA_MM2S_SEL1_FINISHED_TASK
DMA_S2MM_SEL0_STALLED_LOCK	33	DMA_S2MM_SEL0_STALLED_LOCK
DMA_S2MM_SEL1_STALLED_LOCK	34	DMA_S2MM_SEL1_STALLED_LOCK
DMA_MM2S_SEL0_STALLED_LOCK	35	DMA_MM2S_SEL0_STALLED_LOCK
DMA_MM2S_SEL1_STALLED_LOCK	36	DMA_MM2S_SEL1_STALLED_LOCK
DMA_S2MM_SEL0_STREAM_STARVATION	37	DMA_S2MM_SEL0_STREAM_STARVATION
DMA_S2MM_SEL1_STREAM_STARVATION	38	DMA_S2MM_SEL1_STREAM_STARVATION
DMA_MM2S_SEL0_STREAM_BACKPRESSURE	39	DMA_MM2S_SEL0_STREAM_BACKPRESSURE
DMA_MM2S_SEL1_STREAM_BACKPRESSURE	40	DMA_MM2S_SEL1_STREAM_BACKPRESSURE
DMA_S2MM_SEL0_MEMORY_BACKPRESSURE	41	DMA_S2MM_SEL0_MEMORY_BACKPRESSURE
DMA_S2MM_SEL1_MEMORY_BACKPRESSURE	42	DMA_S2MM_SEL1_MEMORY_BACKPRESSURE
DMA_MM2S_SEL0_MEMORY_STARVATION	43	DMA_MM2S_SEL0_MEMORY_STARVATION
DMA_MM2S_SEL1_MEMORY_STARVATION	44	DMA_MM2S_SEL1_MEMORY_STARVATION
GROUP_LOCK	45	GROUP_LOCK
LOCK_SEL0_ACQ_EQ	46	LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE	47	LOCK_SEL0_ACQ_GE
LOCK_SEL0_REL	48	LOCK_SEL0_REL
LOCK_SEL0_EQUAL_TO_VALUE	49	LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ	50	LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE	51	LOCK_SEL1_ACQ_GE
LOCK_SEL1_REL	52	LOCK_SEL1_REL
LOCK_SEL1_EQUAL_TO_VALUE	53	LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ	54	LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE	55	LOCK_SEL2_ACQ_GE
LOCK_SEL2_REL	56	LOCK_SEL2_REL
LOCK_SEL2_EQUAL_TO_VALUE	57	LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ	58	LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE	59	LOCK_SEL3_ACQ_GE
LOCK_SEL3_REL	60	LOCK_SEL3_REL
LOCK_SEL3_EQUAL_TO_VALUE	61	LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ	62	LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE	63	LOCK_SEL4_ACQ_GE
LOCK_SEL4_REL	64	LOCK_SEL4_REL
LOCK_SEL4_EQUAL_TO_VALUE	65	LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ	66	LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE	67	LOCK_SEL5_ACQ_GE
LOCK_SEL5_REL	68	LOCK_SEL5_REL
LOCK_SEL5_EQUAL_TO_VALUE	69	LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ	70	LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE	71	LOCK_SEL6_ACQ_GE
LOCK_SEL6_REL	72	LOCK_SEL6_REL
LOCK_SEL6_EQUAL_TO_VALUE	73	LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ	74	LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE	75	LOCK_SEL7_ACQ_GE
LOCK_SEL7_REL	76	LOCK_SEL7_REL
LOCK_SEL7_EQUAL_TO_VALUE	77	LOCK_SEL7_EQUAL_TO_VALUE
GROUP_STREAM_SWITCH	78	GROUP_STREAM_SWITCH
PORT_IDLE_0	79	PORT_IDLE_0
PORT_RUNNING_0	80	PORT_RUNNING_0
PORT_STALLED_0	81	PORT_STALLED_0
PORT_TLAST_0	82	PORT_TLAST_0
PORT_IDLE_1	83	PORT_IDLE_1
PORT_RUNNING_1	84	PORT_RUNNING_1
PORT_STALLED_1	85	PORT_STALLED_1
PORT_TLAST_1	86	PORT_TLAST_1
PORT_IDLE_2	87	PORT_IDLE_2
PORT_RUNNING_2	88	PORT_RUNNING_2
PORT_STALLED_2	89	PORT_STALLED_2
PORT_TLAST_2	90	PORT_TLAST_2
PORT_IDLE_3	91	PORT_IDLE_3
PORT_RUNNING_3	92	PORT_RUNNING_3
PORT_STALLED_3	93	PORT_STALLED_3
PORT_TLAST_3	94	PORT_TLAST_3
PORT_IDLE_4	95	PORT_IDLE_4
PORT_RUNNING_4	96	PORT_RUNNING_4
PORT_STALLED_4	97	PORT_STALLED_4
PORT_TLAST_4	98	PORT_TLAST_4
PORT_IDLE_5	99	PORT_IDLE_5
PORT_RUNNING_5	100	PORT_RUNNING_5
PORT_STALLED_5	101	PORT_STALLED_5
PORT_TLAST_5	102	PORT_TLAST_5
PORT_IDLE_6	103	PORT_IDLE_6
PORT_RUNNING_6	104	PORT_RUNNING_6
PORT_STALLED_6	105	PORT_STALLED_6
PORT_TLAST_6	106	PORT_TLAST_6
PORT_IDLE_7	107	PORT_IDLE_7
PORT_RUNNING_7	108	PORT_RUNNING_7
PORT_STALLED_7	109	PORT_STALLED_7
PORT_TLAST_7	110	PORT_TLAST_7
GROUP_MEMORY_CONFLICT	111	GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0	112	CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1	113	CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2	114	CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3	115	CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4	116	CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5	117	CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6	118	CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7	119	CONFLICT_DM_BANK_7
CONFLICT_DM_BANK_8	120	CONFLICT_DM_BANK_8
CONFLICT_DM_BANK_9	121	CONFLICT_DM_BANK_9
CONFLICT_DM_BANK_10	122	CONFLICT_DM_BANK_10
CONFLICT_DM_BANK_11	123	CONFLICT_DM_BANK_11
CONFLICT_DM_BANK_12	124	CONFLICT_DM_BANK_12
CONFLICT_DM_BANK_13	125	CONFLICT_DM_BANK_13
CONFLICT_DM_BANK_14	126	CONFLICT_DM_BANK_14
CONFLICT_DM_BANK_15	127	CONFLICT_DM_BANK_15
GROUP_ERRORS	128	GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED	129	DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT	130	DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT	131	DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT	132	DM_ECC_ERROR_2BIT
DMA_S2MM_ERROR	133	DMA_S2MM_ERROR
DMA_MM2S_ERROR	134	DMA_MM2S_ERROR
STREAM_SWITCH_PARITY_ERROR	135	STREAM_SWITCH_PARITY_ERROR
STREAM_PKT_ERROR	136	STREAM_PKT_ERROR
CONTROL_PKT_ERROR	137	CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR	138	AXI_MM_SLAVE_ERROR
LOCK_ERROR	139	LOCK_ERROR
DMA_TASK_TOKEN_STALL	140	DMA_TASK_TOKEN_STALL
GROUP_BROADCAST	141	GROUP_BROADCAST
BROADCAST_0	142	BROADCAST_0
BROADCAST_1	143	BROADCAST_1
BROADCAST_2	144	BROADCAST_2
BROADCAST_3	145	BROADCAST_3
BROADCAST_4	146	BROADCAST_4
BROADCAST_5	147	BROADCAST_5
BROADCAST_6	148	BROADCAST_6
BROADCAST_7	149	BROADCAST_7
BROADCAST_8	150	BROADCAST_8
BROADCAST_9	151	BROADCAST_9
BROADCAST_10	152	BROADCAST_10
BROADCAST_11	153	BROADCAST_11
BROADCAST_12	154	BROADCAST_12
BROADCAST_13	155	BROADCAST_13
BROADCAST_14	156	BROADCAST_14
BROADCAST_15	157	BROADCAST_15
GROUP_USER_EVENT	158	GROUP_USER_EVENT
USER_EVENT_0	159	USER_EVENT_0
USER_EVENT_1	160	USER_EVENT_1

ObjectFifoPort

Ports of an object FIFO

Cases:

Symbol	Value	String
Produce	0	Produce
Consume	1	Consume

ShimTileEvent

Shim tile event enumeration for AIE

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
GROUP_DMA_ACTIVITY	11	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_BD	12	DMA_S2MM_0_START_BD
DMA_S2MM_1_START_BD	13	DMA_S2MM_1_START_BD
DMA_MM2S_0_START_BD	14	DMA_MM2S_0_START_BD
DMA_MM2S_1_START_BD	15	DMA_MM2S_1_START_BD
DMA_S2MM_0_FINISHED_BD	16	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	17	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	18	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	19	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_GO_TO_IDLE	20	DMA_S2MM_0_GO_TO_IDLE
DMA_S2MM_1_GO_TO_IDLE	21	DMA_S2MM_1_GO_TO_IDLE
DMA_MM2S_0_GO_TO_IDLE	22	DMA_MM2S_0_GO_TO_IDLE
DMA_MM2S_1_GO_TO_IDLE	23	DMA_MM2S_1_GO_TO_IDLE
DMA_S2MM_0_STALLED_LOCK_ACQUIRE	24	DMA_S2MM_0_STALLED_LOCK_ACQUIRE
DMA_S2MM_1_STALLED_LOCK_ACQUIRE	25	DMA_S2MM_1_STALLED_LOCK_ACQUIRE
DMA_MM2S_0_STALLED_LOCK_ACQUIRE	26	DMA_MM2S_0_STALLED_LOCK_ACQUIRE
DMA_MM2S_1_STALLED_LOCK_ACQUIRE	27	DMA_MM2S_1_STALLED_LOCK_ACQUIRE
GROUP_LOCK	28	GROUP_LOCK
LOCK_0_ACQUIRED	29	LOCK_0_ACQUIRED
LOCK_0_RELEASED	30	LOCK_0_RELEASED
LOCK_1_ACQUIRED	31	LOCK_1_ACQUIRED
LOCK_1_RELEASED	32	LOCK_1_RELEASED
LOCK_2_ACQUIRED	33	LOCK_2_ACQUIRED
LOCK_2_RELEASED	34	LOCK_2_RELEASED
LOCK_3_ACQUIRED	35	LOCK_3_ACQUIRED
LOCK_3_RELEASED	36	LOCK_3_RELEASED
LOCK_4_ACQUIRED	37	LOCK_4_ACQUIRED
LOCK_4_RELEASED	38	LOCK_4_RELEASED
LOCK_5_ACQUIRED	39	LOCK_5_ACQUIRED
LOCK_5_RELEASED	40	LOCK_5_RELEASED
LOCK_6_ACQUIRED	41	LOCK_6_ACQUIRED
LOCK_6_RELEASED	42	LOCK_6_RELEASED
LOCK_7_ACQUIRED	43	LOCK_7_ACQUIRED
LOCK_7_RELEASED	44	LOCK_7_RELEASED
LOCK_8_ACQUIRED	45	LOCK_8_ACQUIRED
LOCK_8_RELEASED	46	LOCK_8_RELEASED
LOCK_9_ACQUIRED	47	LOCK_9_ACQUIRED
LOCK_9_RELEASED	48	LOCK_9_RELEASED
LOCK_10_ACQUIRED	49	LOCK_10_ACQUIRED
LOCK_10_RELEASED	50	LOCK_10_RELEASED
LOCK_11_ACQUIRED	51	LOCK_11_ACQUIRED
LOCK_11_RELEASED	52	LOCK_11_RELEASED
LOCK_12_ACQUIRED	53	LOCK_12_ACQUIRED
LOCK_12_RELEASED	54	LOCK_12_RELEASED
LOCK_13_ACQUIRED	55	LOCK_13_ACQUIRED
LOCK_13_RELEASED	56	LOCK_13_RELEASED
LOCK_14_ACQUIRED	57	LOCK_14_ACQUIRED
LOCK_14_RELEASED	58	LOCK_14_RELEASED
LOCK_15_ACQUIRED	59	LOCK_15_ACQUIRED
LOCK_15_RELEASED	60	LOCK_15_RELEASED
GROUP_ERRORS	61	GROUP_ERRORS
AXI_MM_SLAVE_TILE_ERROR	62	AXI_MM_SLAVE_TILE_ERROR
CONTROL_PKT_ERROR	63	CONTROL_PKT_ERROR
AXI_MM_DECODE_NSU_ERROR	64	AXI_MM_DECODE_NSU_ERROR
AXI_MM_SLAVE_NSU_ERROR	65	AXI_MM_SLAVE_NSU_ERROR
AXI_MM_UNSUPPORTED_TRAFFIC	66	AXI_MM_UNSUPPORTED_TRAFFIC
AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE	67	AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE
AXI_MM_BYTE_STROBE_ERROR	68	AXI_MM_BYTE_STROBE_ERROR
DMA_S2MM_0_ERROR	69	DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR	70	DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR	71	DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR	72	DMA_MM2S_1_ERROR
GROUP_STREAM_SWITCH	73	GROUP_STREAM_SWITCH
PORT_IDLE_0	74	PORT_IDLE_0
PORT_RUNNING_0	75	PORT_RUNNING_0
PORT_STALLED_0	76	PORT_STALLED_0
PORT_TLAST_0	77	PORT_TLAST_0
PORT_IDLE_1	78	PORT_IDLE_1
PORT_RUNNING_1	79	PORT_RUNNING_1
PORT_STALLED_1	80	PORT_STALLED_1
PORT_TLAST_1	81	PORT_TLAST_1
PORT_IDLE_2	82	PORT_IDLE_2
PORT_RUNNING_2	83	PORT_RUNNING_2
PORT_STALLED_2	84	PORT_STALLED_2
PORT_TLAST_2	85	PORT_TLAST_2
PORT_IDLE_3	86	PORT_IDLE_3
PORT_RUNNING_3	87	PORT_RUNNING_3
PORT_STALLED_3	88	PORT_STALLED_3
PORT_TLAST_3	89	PORT_TLAST_3
PORT_IDLE_4	90	PORT_IDLE_4
PORT_RUNNING_4	91	PORT_RUNNING_4
PORT_STALLED_4	92	PORT_STALLED_4
PORT_TLAST_4	93	PORT_TLAST_4
PORT_IDLE_5	94	PORT_IDLE_5
PORT_RUNNING_5	95	PORT_RUNNING_5
PORT_STALLED_5	96	PORT_STALLED_5
PORT_TLAST_5	97	PORT_TLAST_5
PORT_IDLE_6	98	PORT_IDLE_6
PORT_RUNNING_6	99	PORT_RUNNING_6
PORT_STALLED_6	100	PORT_STALLED_6
PORT_TLAST_6	101	PORT_TLAST_6
PORT_IDLE_7	102	PORT_IDLE_7
PORT_RUNNING_7	103	PORT_RUNNING_7
PORT_STALLED_7	104	PORT_STALLED_7
PORT_TLAST_7	105	PORT_TLAST_7
GROUP_BROADCAST_A	106	GROUP_BROADCAST_A
BROADCAST_A_0	107	BROADCAST_A_0
BROADCAST_A_1	108	BROADCAST_A_1
BROADCAST_A_2	109	BROADCAST_A_2
BROADCAST_A_3	110	BROADCAST_A_3
BROADCAST_A_4	111	BROADCAST_A_4
BROADCAST_A_5	112	BROADCAST_A_5
BROADCAST_A_6	113	BROADCAST_A_6
BROADCAST_A_7	114	BROADCAST_A_7
BROADCAST_A_8	115	BROADCAST_A_8
BROADCAST_A_9	116	BROADCAST_A_9
BROADCAST_A_10	117	BROADCAST_A_10
BROADCAST_A_11	118	BROADCAST_A_11
BROADCAST_A_12	119	BROADCAST_A_12
BROADCAST_A_13	120	BROADCAST_A_13
BROADCAST_A_14	121	BROADCAST_A_14
BROADCAST_A_15	122	BROADCAST_A_15
GROUP_USER_EVENT	123	GROUP_USER_EVENT
USER_EVENT_0	124	USER_EVENT_0
USER_EVENT_1	125	USER_EVENT_1
USER_EVENT_2	126	USER_EVENT_2
USER_EVENT_3	127	USER_EVENT_3

ShimTileEventAIE2

Shim tile event enumeration for AIE2

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	11	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	12	EDGE_DETECTION_EVENT_1
GROUP_DMA_ACTIVITY	13	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK	14	DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK	15	DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK	16	DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK	17	DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD	18	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	19	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	20	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	21	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK	22	DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK	23	DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK	24	DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK	25	DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK	26	DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK	27	DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK	28	DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK	29	DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION	30	DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION	31	DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE	32	DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE	33	DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE	34	DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE	35	DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION	36	DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION	37	DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK	38	GROUP_LOCK
LOCK_0_ACQ_EQ	39	LOCK_0_ACQ_EQ
LOCK_0_ACQ_GE	40	LOCK_0_ACQ_GE
LOCK_0_REL	41	LOCK_0_REL
LOCK_0_EQUAL_TO_VALUE	42	LOCK_0_EQUAL_TO_VALUE
LOCK_1_ACQ_EQ	43	LOCK_1_ACQ_EQ
LOCK_1_ACQ_GE	44	LOCK_1_ACQ_GE
LOCK_1_REL	45	LOCK_1_REL
LOCK_1_EQUAL_TO_VALUE	46	LOCK_1_EQUAL_TO_VALUE
LOCK_2_ACQ_EQ	47	LOCK_2_ACQ_EQ
LOCK_2_ACQ_GE	48	LOCK_2_ACQ_GE
LOCK_2_REL	49	LOCK_2_REL
LOCK_2_EQUAL_TO_VALUE	50	LOCK_2_EQUAL_TO_VALUE
LOCK_3_ACQ_EQ	51	LOCK_3_ACQ_EQ
LOCK_3_ACQ_GE	52	LOCK_3_ACQ_GE
LOCK_3_REL	53	LOCK_3_REL
LOCK_3_EQUAL_TO_VALUE	54	LOCK_3_EQUAL_TO_VALUE
LOCK_4_ACQ_EQ	55	LOCK_4_ACQ_EQ
LOCK_4_ACQ_GE	56	LOCK_4_ACQ_GE
LOCK_4_REL	57	LOCK_4_REL
LOCK_4_EQUAL_TO_VALUE	58	LOCK_4_EQUAL_TO_VALUE
LOCK_5_ACQ_EQ	59	LOCK_5_ACQ_EQ
LOCK_5_ACQ_GE	60	LOCK_5_ACQ_GE
LOCK_5_REL	61	LOCK_5_REL
LOCK_5_EQUAL_TO_VALUE	62	LOCK_5_EQUAL_TO_VALUE
GROUP_ERRORS	63	GROUP_ERRORS
AXI_MM_SLAVE_ERROR	64	AXI_MM_SLAVE_ERROR
CONTROL_PKT_ERROR	65	CONTROL_PKT_ERROR
STREAM_SWITCH_PARITY_ERROR	66	STREAM_SWITCH_PARITY_ERROR
AXI_MM_DECODE_NSU_ERROR	67	AXI_MM_DECODE_NSU_ERROR
AXI_MM_SLAVE_NSU_ERROR	68	AXI_MM_SLAVE_NSU_ERROR
AXI_MM_UNSUPPORTED_TRAFFIC	69	AXI_MM_UNSUPPORTED_TRAFFIC
AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE	70	AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE
AXI_MM_BYTE_STROBE_ERROR	71	AXI_MM_BYTE_STROBE_ERROR
DMA_S2MM_ERROR	72	DMA_S2MM_ERROR
DMA_MM2S_ERROR	73	DMA_MM2S_ERROR
LOCK_ERROR	74	LOCK_ERROR
DMA_TASK_TOKEN_STALL	75	DMA_TASK_TOKEN_STALL
GROUP_STREAM_SWITCH	76	GROUP_STREAM_SWITCH
PORT_IDLE_0	77	PORT_IDLE_0
PORT_RUNNING_0	78	PORT_RUNNING_0
PORT_STALLED_0	79	PORT_STALLED_0
PORT_TLAST_0	80	PORT_TLAST_0
PORT_IDLE_1	81	PORT_IDLE_1
PORT_RUNNING_1	82	PORT_RUNNING_1
PORT_STALLED_1	83	PORT_STALLED_1
PORT_TLAST_1	84	PORT_TLAST_1
PORT_IDLE_2	85	PORT_IDLE_2
PORT_RUNNING_2	86	PORT_RUNNING_2
PORT_STALLED_2	87	PORT_STALLED_2
PORT_TLAST_2	88	PORT_TLAST_2
PORT_IDLE_3	89	PORT_IDLE_3
PORT_RUNNING_3	90	PORT_RUNNING_3
PORT_STALLED_3	91	PORT_STALLED_3
PORT_TLAST_3	92	PORT_TLAST_3
PORT_IDLE_4	93	PORT_IDLE_4
PORT_RUNNING_4	94	PORT_RUNNING_4
PORT_STALLED_4	95	PORT_STALLED_4
PORT_TLAST_4	96	PORT_TLAST_4
PORT_IDLE_5	97	PORT_IDLE_5
PORT_RUNNING_5	98	PORT_RUNNING_5
PORT_STALLED_5	99	PORT_STALLED_5
PORT_TLAST_5	100	PORT_TLAST_5
PORT_IDLE_6	101	PORT_IDLE_6
PORT_RUNNING_6	102	PORT_RUNNING_6
PORT_STALLED_6	103	PORT_STALLED_6
PORT_TLAST_6	104	PORT_TLAST_6
PORT_IDLE_7	105	PORT_IDLE_7
PORT_RUNNING_7	106	PORT_RUNNING_7
PORT_STALLED_7	107	PORT_STALLED_7
PORT_TLAST_7	108	PORT_TLAST_7
GROUP_BROADCAST_A	109	GROUP_BROADCAST_A
BROADCAST_A_0	110	BROADCAST_A_0
BROADCAST_A_1	111	BROADCAST_A_1
BROADCAST_A_2	112	BROADCAST_A_2
BROADCAST_A_3	113	BROADCAST_A_3
BROADCAST_A_4	114	BROADCAST_A_4
BROADCAST_A_5	115	BROADCAST_A_5
BROADCAST_A_6	116	BROADCAST_A_6
BROADCAST_A_7	117	BROADCAST_A_7
BROADCAST_A_8	118	BROADCAST_A_8
BROADCAST_A_9	119	BROADCAST_A_9
BROADCAST_A_10	120	BROADCAST_A_10
BROADCAST_A_11	121	BROADCAST_A_11
BROADCAST_A_12	122	BROADCAST_A_12
BROADCAST_A_13	123	BROADCAST_A_13
BROADCAST_A_14	124	BROADCAST_A_14
BROADCAST_A_15	125	BROADCAST_A_15
USER_EVENT_0	126	USER_EVENT_0
USER_EVENT_1	127	USER_EVENT_1

ShimTileEventAIE2P

Shim tile event enumeration for AIE2P

Cases:

Symbol	Value	String
NONE	0	NONE
TRUE	1	TRUE
GROUP_0	2	GROUP_0
TIMER_SYNC	3	TIMER_SYNC
TIMER_VALUE_REACHED	4	TIMER_VALUE_REACHED
PERF_CNT_0	5	PERF_CNT_0
PERF_CNT_1	6	PERF_CNT_1
COMBO_EVENT_0	7	COMBO_EVENT_0
COMBO_EVENT_1	8	COMBO_EVENT_1
COMBO_EVENT_2	9	COMBO_EVENT_2
COMBO_EVENT_3	10	COMBO_EVENT_3
EDGE_DETECTION_EVENT_0	11	EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1	12	EDGE_DETECTION_EVENT_1
GROUP_DMA_ACTIVITY	13	GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK	14	DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK	15	DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK	16	DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK	17	DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD	18	DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD	19	DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD	20	DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD	21	DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK	22	DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK	23	DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK	24	DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK	25	DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK	26	DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK	27	DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK	28	DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK	29	DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION	30	DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION	31	DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE	32	DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE	33	DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE	34	DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE	35	DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION	36	DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION	37	DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK	38	GROUP_LOCK
LOCK_0_ACQ_EQ	39	LOCK_0_ACQ_EQ
LOCK_0_ACQ_GE	40	LOCK_0_ACQ_GE
LOCK_0_REL	41	LOCK_0_REL
LOCK_0_EQUAL_TO_VALUE	42	LOCK_0_EQUAL_TO_VALUE
LOCK_1_ACQ_EQ	43	LOCK_1_ACQ_EQ
LOCK_1_ACQ_GE	44	LOCK_1_ACQ_GE
LOCK_1_REL	45	LOCK_1_REL
LOCK_1_EQUAL_TO_VALUE	46	LOCK_1_EQUAL_TO_VALUE
LOCK_2_ACQ_EQ	47	LOCK_2_ACQ_EQ
LOCK_2_ACQ_GE	48	LOCK_2_ACQ_GE
LOCK_2_REL	49	LOCK_2_REL
LOCK_2_EQUAL_TO_VALUE	50	LOCK_2_EQUAL_TO_VALUE
LOCK_3_ACQ_EQ	51	LOCK_3_ACQ_EQ
LOCK_3_ACQ_GE	52	LOCK_3_ACQ_GE
LOCK_3_REL	53	LOCK_3_REL
LOCK_3_EQUAL_TO_VALUE	54	LOCK_3_EQUAL_TO_VALUE
LOCK_4_ACQ_EQ	55	LOCK_4_ACQ_EQ
LOCK_4_ACQ_GE	56	LOCK_4_ACQ_GE
LOCK_4_REL	57	LOCK_4_REL
LOCK_4_EQUAL_TO_VALUE	58	LOCK_4_EQUAL_TO_VALUE
LOCK_5_ACQ_EQ	59	LOCK_5_ACQ_EQ
LOCK_5_ACQ_GE	60	LOCK_5_ACQ_GE
LOCK_5_REL	61	LOCK_5_REL
LOCK_5_EQUAL_TO_VALUE	62	LOCK_5_EQUAL_TO_VALUE
GROUP_ERRORS	63	GROUP_ERRORS
AXI_MM_SLAVE_ERROR	64	AXI_MM_SLAVE_ERROR
CONTROL_PKT_ERROR	65	CONTROL_PKT_ERROR
STREAM_SWITCH_PARITY_ERROR	66	STREAM_SWITCH_PARITY_ERROR
AXI_MM_DECODE_NSU_ERROR	67	AXI_MM_DECODE_NSU_ERROR
AXI_MM_SLAVE_NSU_ERROR	68	AXI_MM_SLAVE_NSU_ERROR
AXI_MM_UNSUPPORTED_TRAFFIC	69	AXI_MM_UNSUPPORTED_TRAFFIC
AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE	70	AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE
AXI_MM_BYTE_STROBE_ERROR	71	AXI_MM_BYTE_STROBE_ERROR
DMA_S2MM_ERROR	72	DMA_S2MM_ERROR
DMA_MM2S_ERROR	73	DMA_MM2S_ERROR
LOCK_ERROR	74	LOCK_ERROR
DMA_TASK_TOKEN_STALL	75	DMA_TASK_TOKEN_STALL
GROUP_STREAM_SWITCH	76	GROUP_STREAM_SWITCH
PORT_IDLE_0	77	PORT_IDLE_0
PORT_RUNNING_0	78	PORT_RUNNING_0
PORT_STALLED_0	79	PORT_STALLED_0
PORT_TLAST_0	80	PORT_TLAST_0
PORT_IDLE_1	81	PORT_IDLE_1
PORT_RUNNING_1	82	PORT_RUNNING_1
PORT_STALLED_1	83	PORT_STALLED_1
PORT_TLAST_1	84	PORT_TLAST_1
PORT_IDLE_2	85	PORT_IDLE_2
PORT_RUNNING_2	86	PORT_RUNNING_2
PORT_STALLED_2	87	PORT_STALLED_2
PORT_TLAST_2	88	PORT_TLAST_2
PORT_IDLE_3	89	PORT_IDLE_3
PORT_RUNNING_3	90	PORT_RUNNING_3
PORT_STALLED_3	91	PORT_STALLED_3
PORT_TLAST_3	92	PORT_TLAST_3
PORT_IDLE_4	93	PORT_IDLE_4
PORT_RUNNING_4	94	PORT_RUNNING_4
PORT_STALLED_4	95	PORT_STALLED_4
PORT_TLAST_4	96	PORT_TLAST_4
PORT_IDLE_5	97	PORT_IDLE_5
PORT_RUNNING_5	98	PORT_RUNNING_5
PORT_STALLED_5	99	PORT_STALLED_5
PORT_TLAST_5	100	PORT_TLAST_5
PORT_IDLE_6	101	PORT_IDLE_6
PORT_RUNNING_6	102	PORT_RUNNING_6
PORT_STALLED_6	103	PORT_STALLED_6
PORT_TLAST_6	104	PORT_TLAST_6
PORT_IDLE_7	105	PORT_IDLE_7
PORT_RUNNING_7	106	PORT_RUNNING_7
PORT_STALLED_7	107	PORT_STALLED_7
PORT_TLAST_7	108	PORT_TLAST_7
GROUP_BROADCAST_A	109	GROUP_BROADCAST_A
BROADCAST_A_0	110	BROADCAST_A_0
BROADCAST_A_1	111	BROADCAST_A_1
BROADCAST_A_2	112	BROADCAST_A_2
BROADCAST_A_3	113	BROADCAST_A_3
BROADCAST_A_4	114	BROADCAST_A_4
BROADCAST_A_5	115	BROADCAST_A_5
BROADCAST_A_6	116	BROADCAST_A_6
BROADCAST_A_7	117	BROADCAST_A_7
BROADCAST_A_8	118	BROADCAST_A_8
BROADCAST_A_9	119	BROADCAST_A_9
BROADCAST_A_10	120	BROADCAST_A_10
BROADCAST_A_11	121	BROADCAST_A_11
BROADCAST_A_12	122	BROADCAST_A_12
BROADCAST_A_13	123	BROADCAST_A_13
BROADCAST_A_14	124	BROADCAST_A_14
BROADCAST_A_15	125	BROADCAST_A_15
USER_EVENT_0	126	USER_EVENT_0
USER_EVENT_1	127	USER_EVENT_1

WireBundle

Bundle of wires

Cases:

Symbol	Value	String
Core	0	Core
DMA	1	DMA
FIFO	2	FIFO
South	3	South
West	4	West
North	5	North
East	6	East
PLIO	7	PLIO
NOC	8	NOC
Trace	9	Trace
TileControl	10	TileControl