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'aievec' Dialect

Types and operations for AIE vector dialect

Operations

aievec.add_elem (::xilinx::aievec::AddElemOp)

AIE vector add elem

Syntax:

operation ::= `aievec.add_elem` $lhs `,` $rhs attr-dict `:` type($result)

AMD-specific AIE2 intrinsic that allows you to perform addition operation on all types of vectors.$result =$lhs + $rhs`.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.band (::xilinx::aievec::BandOp)

AIE vector bitwise and

Syntax:

operation ::= `aievec.band` $lhs `,` $rhs attr-dict `:` type($lhs) `,` type($rhs)
              `,` type($result)

AMD-specific intrinsic that computes bitwise and of two vectors and returns the result. $result = band($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
lhs 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type
rhs 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

Results:

Result Description
result 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

aievec.bneg (::xilinx::aievec::BnegOp)

AIE vector bitwise negation

Syntax:

operation ::= `aievec.bneg` $source attr-dict `:` type($result)

AMD-specific intrinsic that computes bitwise negation of a vector and returns the result. $result = bneg($source`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

Results:

Result Description
result 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

aievec.bor (::xilinx::aievec::BorOp)

AIE vector bitwise or

Syntax:

operation ::= `aievec.bor` $lhs `,` $rhs attr-dict `:` type($lhs) `,` type($rhs)
              `,` type($result)

AMD-specific intrinsic that computes bitwise or of two vectors and returns the result. $result = bor($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
lhs 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type
rhs 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

Results:

Result Description
result 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

aievec.broadcast (::xilinx::aievec::BroadcastOp)

AIE2 broadcast

AMD-specific broadcast intrinsic. Extract element index from vector and broadcasts its value to all lanes of the vector. $result = broadcast($source, $idx)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
idx::mlir::IntegerAttr8-bit signless integer attribute whose value is non-negative

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.broadcast_scalar (::xilinx::aievec::BroadcastScalarOp)

AIE2 broadcast scalar

AMD-specific broadcast scalar intrinsic. Broadcasts input value to all vector lanes. $result = broadcast_scalar($source)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source bfloat16 type or 32-bit float or 32-bit signless integer or 16-bit signless integer or 8-bit signless integer

Results:

Result Description
result vector of any non-token type values

aievec.bxor (::xilinx::aievec::BxorOp)

AIE vector bitwise xor

Syntax:

operation ::= `aievec.bxor` $lhs `,` $rhs attr-dict `:` type($lhs) `,` type($rhs)
              `,` type($result)

AMD-specific intrinsic that computes bitwise xor of two vectors and returns the result. $result = bxor($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
lhs 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type
rhs 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

Results:

Result Description
result 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type

aievec.cast (::xilinx::aievec::CastOp)

AIE cast

AIE2 cast intrinsic. Cast values from source data type to result data types. $result = cast($source, isResAcc)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
isResAcc::mlir::BoolAttrbool attribute

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.cmp (::xilinx::aievec::CmpOp)

AIE vector comparison

Syntax:

operation ::= `aievec.cmp` $lhs `,` $rhs ` ` `{` `pred` `=` $pred attr-dict `}` `:` type($lhs) `,` type($rhs)  `,` type($result)

AMD-specific intrinsic that performs element-wise comparisonof two input vectors. The attribute predicate defines which type of comparison is performed. The following comparisons are supported:

  • equal (mnemonic: "eq")
  • not equal (mnemonic: "ne")
  • signed less than (mnemonic: "slt")
  • unsigned less than (mnemonic: "ult")
  • signed less than or equal (mnemonic: "sle")
  • unsigned less than or equal (mnemonic: "ule")
  • signed greater than (mnemonic: "sgt")
  • unsigned greater than (mnemonic: "ugt")
  • signed greater than or equal (mnemonic: "sge")
  • unsigned greater than or equal (mnemonic: "uge")

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
pred::mlir::StringAttrstring attribute

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values

Results:

Result Description
result unsigned integer

aievec.concat (::xilinx::aievec::ConcatOp)

AIE concat

AMD-specific concat intrinsic. Concatenates two or more smaller vectors into a bigger vector. The verifier confirms that all the input vectors have the same number of lanes. $result = concat($sources[0], $sources[1], ...)

Traits: AlwaysSpeculatableImplTrait, InferTypeOpAdaptor

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
sources variadic of vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.exp (::xilinx::aievec::ExpOp)

AIE vector exponential

Syntax:

operation ::= `aievec.exp` $source attr-dict `:` type($result)

AMD-specific intrinsic that computes the exponential of the input vector. For AIE2P, this will be lowered to the exp2 intrinsic using the identity exp(x) = exp2(x * log2(e)). $result = exp($source`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.exp2 (::xilinx::aievec::Exp2Op)

AIE vector base-2 exponential

Syntax:

operation ::= `aievec.exp2` $source attr-dict `:` type($result)

AMD-specific intrinsic that computes 2 raised to each element of the input vector. For AIE2P, this is lowered to the hardware exp2 intrinsic. $result = exp2($source`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.ext (::xilinx::aievec::ExtOp)

AIE ext

AMD-specific vector extract intrinsic. Selects contiguous lanes from the source vector, and transfers the data from those lanes to the result. The source divides into equal parts as wide as the result, and index selects one of them: index 0 extracts the lowest part, index 1 the next one, and so on. The verifier requires index to be less than the number of parts. $result = ext($source, $index)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
index::mlir::IntegerAttr8-bit signless integer attribute whose value is non-negative

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.ext_elem (::xilinx::aievec::ExtElemOp)

AIE extract element

Syntax:

operation ::= `aievec.ext_elem` $source `,` $index attr-dict `:` type($source) `,` type($index) `,` type($result)

AMD - specific extract element intrinsic. Extract element determined by index from vector. $result = ext_elem($source, $index).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source vector of any non-token type values
index 32-bit signless integer

Results:

Result Description
result bfloat16 type or 32-bit float or 32-bit signless integer or 16-bit signless integer or 8-bit signless integer

aievec.fma_conv (::xilinx::aievec::FMAConvOp)

AIE2 multiply accumulate convolution

AMD-specific multiply accumulate convolution intrinsic. Multiply accumulate convolution operation of (M x N)matrix with (N x 1)kernel. $result = mac_convMxN($lhs, $rhs, $acc)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
M::mlir::IntegerAttr32-bit signless integer attribute
N::mlir::IntegerAttr32-bit signless integer attribute
fmsub::mlir::BoolAttrbool attribute

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values
acc vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.inv (::xilinx::aievec::InvOp)

AIE inverse

Syntax:

operation ::= `aievec.inv` $source attr-dict `:` type($result)

AMD-specific intrinsic that computes the inverse (1/x) of a scalar f32 or a vector of f32 elements. For AIE2P, scalar f32 is lowered to the inv intrinsic, and vector f32 is unrolled into scalar inv intrinsic calls. $result = inv($source) = 1.0 / $source.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source 32-bit float or vector of 32-bit float values of length 16/32

Results:

Result Description
result 32-bit float or vector of 32-bit float values of length 16/32

aievec.legacyshuffle (::xilinx::aievec::LegacyShuffleOp)

AIE2 shuffle

AMD-specific vector shuffle intrinsic by a specific shuffle mode. $result = shuffle($source, $mode)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
mode::mlir::IntegerAttr32-bit signless integer attribute

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.mac_elem (::xilinx::aievec::FMAElemOp)

AIE2 element-wise vector fused multiply-add

AMD-specific multiply-add operation. It multiplies two 1-D vectors in the same channel, and adds the result to an accumulator. $result =$lhs * $rhs + $acc`. Note: the same operator can be used as fmsub operator by setting the 'fmsub' bool to true.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
fmsub::mlir::BoolAttrbool attribute

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values
acc vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.matmul (::xilinx::aievec::MatMulOp)

AIE2 matrix-multiply and accummulate

Syntax:

operation ::= `aievec.matmul` $lhs `,` $rhs `,` $acc
              (`lhs_transposed` $lhs_transposed^)?
              (`rhs_transposed` $rhs_transposed^)?
              attr-dict `:` type($lhs) `,` type($rhs) `into`
              type($acc)

AMD AIEv2-specific intrinsic that performs a matrix multiplications between lhs and rhs, and accumulates the result in acc.

Operand signedness is carried in the integer element types: a signed element type (si8) sets the MAC signX/signY bit, an unsigned type (ui8) clears it. A signless element type (i8) is treated as signed. Each operand is resolved independently, and aievec.matmul_aie2p follows the same rule.

Currently, this intrinsic supports the following type combinations:

 lhs                | rhs                | Accumulator
:------------------:|:------------------:|:-----------------:
 `vector<4x16xi8>`  | `vector<16x8xi4>`  | `vector<4x8xi32>`
 `vector<4x8xi8>`   | `vector<8x8xi8>`   | `vector<4x8xi32>`
 `vector<4x4xi16>`  | `vector<4x8xi8>`   | `vector<4x8xi32>`
 `vector<4x2xi16>`  | `vector<2x8xi16>`  | `vector<4x8xi32>`
 `vector<2x8xi16>`  | `vector<8x8xi8>`   | `vector<2x8xi64>`
 `vector<4x8xi16>`  | `vector<8x4xi8>`   | `vector<4x4xi64>`
 `vector<2x4xi16>`  | `vector<4x8xi16>`  | `vector<2x8xi64>`
 `vector<4x4xi16>`  | `vector<4x4xi16>`  | `vector<4x4xi64>`
 `vector<4x2xi32>`  | `vector<2x4xi16>`  | `vector<4x4xi64>`
 `vector<4x8xbf16>` | `vector<8x4xbf16>` | `vector<4x4xf32>`

The table gives lhs as [m, k] and rhs as [k, n]. With lhs_transposed, lhs holds the [k, m] transpose instead, and with rhs_transposed, rhs holds the [n, k] transpose; the shapes change accordingly. The lowering transposes an operand with one shuffle when the multiply reads it the other way. An operand that needs a transpose no shuffle mode provides does not verify.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
lhs_transposed::mlir::UnitAttrunit attribute
rhs_transposed::mlir::UnitAttrunit attribute

Operands:

Operand Description
lhs a vector compatible with a lhs operand of matrix-multiply and accumulate
rhs a vector compatible with a rhs operand of matrix-multiply and accumulate
acc a vector compatible with an accumulator of matrix-multiply and accumulate

Results:

Result Description
result a vector compatible with an accumulator of matrix-multiply and accumulate

aievec.matmul_aie2p (::xilinx::aievec::MatMulOp_AIE2P)

AIE2P matrix-multiply and accummulate

Syntax:

operation ::= `aievec.matmul_aie2p` $lhs `,` $rhs `,` $acc
              (`lhs_transposed` $lhs_transposed^)?
              (`rhs_transposed` $rhs_transposed^)?
              attr-dict `:` type($lhs) `,` type($rhs) `into`
              type($acc)

AMD AIEv2P-specific intrinsic that performs a matrix multiplication between lhs and rhs, and accumulates the result in acc.

Operand signedness is carried in the integer element types exactly as for aievec.matmul: si8 sets the MAC signX/signY bit, ui8 clears it, and a signless element type is treated as signed.

Currently, this intrinsic supports the following type combinations:

 lhs                 | rhs                 | Accumulator
:-------------------:|:-------------------:|:------------------:
 `vector<8x8xbf16>`  | `vector<8x8xbf16>`  | `vector<8x8xf32>`
 `vector<4x8xbf16>`  | `vector<8x4xbf16>`  | `vector<4x4xf32>`
 `vector<4x8xbf16>`  | `vector<8x8xbf16>`  | `vector<4x8xf32>`
 `vector<8x1xbf16>`  | `vector<1x8xbf16>`  | `vector<8x8xf32>`
 `vector<8x8xbf16>`  | `vector<8x4xbf16>`  | `vector<8x4xf32>`
 `vector<8x8xi8>`    | `vector<8x8xi8>`    | `vector<8x8xi32>`
 `vector<8x2xi16>`   | `vector<2x8xi16>`   | `vector<8x8xi32>`

lhs_transposed and rhs_transposed mean what they do for aievec.matmul. The bf16 multiplies through bfp16 (an rhs of vector<8x8xbf16>) read rhs as [n, k], and the elementwise vector<8x8xbf16> times vector<8x4xbf16> multiply reads lhs as [k, m]; an operand stored that way needs no shuffle. Any other transposed operand takes one shuffle, or the t16_8x8_lo/t16_8x8_hi pair for an 8x8 bf16 tile.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
lhs_transposed::mlir::UnitAttrunit attribute
rhs_transposed::mlir::UnitAttrunit attribute

Operands:

Operand Description
lhs a vector compatible with a lhs operand of AIE2P matrix-multiply and accumulate
rhs a vector compatible with a rhs operand of AIE2P matrix-multiply and accumulate
acc a vector compatible with an accumulator of AIE2P matrix-multiply and accumulate

Results:

Result Description
result a vector compatible with an accumulator of AIE2P matrix-multiply and accumulate

aievec.max (::xilinx::aievec::MaxOp)

AIE vector maximum

Syntax:

operation ::= `aievec.max` $lhs `,` $rhs attr-dict `:` type($result)

AMD-specific intrinsic that calculates the maximum between two input vectors. $result = max($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.min (::xilinx::aievec::MinOp)

AIE vector minimum

Syntax:

operation ::= `aievec.min` $lhs `,` $rhs attr-dict `:` type($result)

AMD-specific intrinsic that calculates the minimum between two input vectors. $result = min($lhs, $rhs`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.mul_conv (::xilinx::aievec::MulConvOp)

AIE2 multiply convolution

AMD-specific multiply convolution intrinsic. Multiply convolution operation of (M x N)matrix with (N x 1)kernel. $result = mul_convMxN($lhs, $rhs)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
M::mlir::IntegerAttr32-bit signless integer attribute
N::mlir::IntegerAttr32-bit signless integer attribute

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.mul_elem (::xilinx::aievec::MulElemOp)

AIE2 vector element-wise multiply

AMD-specific multiply operation that multiplies two 1-D vectors in the same channel. The vector sizes are at least 512 bits. $result =$lhs * $rhs. Currently, the following are the supported type combinations: lhs | rhs | Accumulator :------------------:|:------------------:|:-----------------:vector<32xi8>|vector<32xi8>|vector<32xi32>vector<32xi16>|vector<32xi16>|vector<32xi32>vector<32xbf16>|vector<32xbf16>|vector<32xf32>(AIE2P)vector<64xbf16>|vector<64xbf16>|vector<64xf32>(AIE2P)vector<16xi32>|vector<16xi32>|vector<16xi64>vector<16xbf16>|vector<16xbf16>|vector<16xf32>vector<16xf32>|vector<16xf32>|vector<16xf32>`'

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultShape, SameOperandsShape, SameTypeOperands

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
lhs vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type or 32-bit float values of length 16/32/64
rhs vector of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or bfloat16 type or 32-bit float values of length 16/32/64

Results:

Result Description
result vector of 32-bit signless integer or 64-bit signless integer or 32-bit float values of length 16/32/64

aievec.neg (::xilinx::aievec::NegOp)

AIE vector negative

Syntax:

operation ::= `aievec.neg` $source attr-dict `:` type($result)

AMD-specific intrinsic that negates the vector and returns the result. $result = neg($source`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.pack (::xilinx::aievec::PackOp)

AIE pack

AMD-specific pack intrinsic. Pack a vector of 16-bit values into a vector of 8-bit values. $result = pack($source)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.sel (::xilinx::aievec::SelOp)

AIE vector lane wise selection

Syntax:

operation ::= `aievec.sel` $lhs `,` $rhs `,` $sel attr-dict `:` type($lhs) `,` type($rhs) `,` type($sel) `,` type($result)

AMD-specific intrinsic that performs lane wise selection between two input vectors, if a bit of sel is zero, the lane of vector lhs is selected, else the lane of vector rhs is selected. $result = sel($lhs, $rhs, $sel`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values
sel unsigned integer

Results:

Result Description
result vector of any non-token type values

aievec.shift (::xilinx::aievec::ShiftOp)

AIE2 concat and shift

AMD-specific shift intrinsic. Concatenates two vectors into a bigger vector, interprets them as a vector of 128 bytes and returns v1::v2[shift: shift+64]. shift is the number of bytes to be shifted. The verifier confirms that all the input and result vectors have the same number of lanes and element types. $result = shift($lhs, $rhs, $shift)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
isAcc::mlir::BoolAttrbool attribute

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values
shift 32-bit signless integer

Results:

Result Description
result vector of any non-token type values

aievec.shuffle (::xilinx::aievec::ShuffleOp)

AIE2 shuffle

Syntax:

operation ::= `aievec.shuffle` $lhs (`,` $rhs^)? $mode attr-dict `:` type($result)

AMD AIEv2-specific vector shuffle. It performs a shuffle of the elements of 1 or 2 input vectors using the specified shuffle mode. The shuffle mode is specified as:

t<width>_<r>x<c>(_(hi|lo))?

where <width> is the bitwidth of the vector element type, <r> and <c> are the number of rows and columns that will be transposed to perform the shuffle, and, for modes that require two 512-bit vectors, hi and lo indicate which part of the resulting extended 1024-bit vector will be assembled and returned.

E.g.: t32_4x8 would take two 512-bit vectors, lhs and rhs, with 16 elements of 32 bits each. The resulting vector would contain either the least (lo) or most (hi) significant 16 elements of the 32 element vector that would result from selecting, out of the concatenated vectors lhs:rhs, 8 blocks of 4 elements, each block taking one of every 8 elements starting from the block index.

That is, for two vector<16xi32> operands containing: 

lhs = [0,   1,  2,  3, ..., 15]
rhs = [17, 18, 19, 20, ..., 31]

The first 8 blocks would be: 

b0 = [0,  8, 16, 24]
b1 = [1,  9, 17, 25]
b2 = [2, 10, 18, 26]
b3 = [3, 11, 19, 27]
   ...
b7 = [7, 15, 23, 31]

t32_4x8_lo would return first four blocks: 

result = [0, 8, 16, 24, 1, 9, 17, 25, ..., 3, 11, 19, 27]

And t32_4x8_hi would return the last four blocks: 

result = [4, 12, 20, 28, 5, 13, 21, 29, ..., 7, 15, 24, 31]

It can be seen as flattened 4x8 matrix, split in two 16-element halfs, being tranposed to a 8x4 arrangement. In the example above:

lhs = [ 0,  1,  2,  3,  4,  5,  6,  7]
      [ 8,  9, 10, 11, 12, 13, 14, 15]
rhs = [16, 17, 18, 19, 20, 21, 22, 23]
      [24, 25, 26, 27, 28, 29, 30, 31]

Would result in: 

t32_4x8_lo = [0,  8, 16, 24]
             [1,  9, 17, 25]
             [2, 10, 18, 26]
             [3, 11, 19, 27]
t32_4x8_hi = [4, 12, 20, 28]
             [5, 13, 21, 29]
             [6, 14, 22, 30]
             [7, 15, 23, 31]

A special mode, t16_1x2_flip, swaps each pair of elements in a vector with 32 16-bit elements. E.g.: 

lhs = [0, 1, 2, 3, ..., 28, 29, 30, 31]
Would result in: 
t16_1x2_flip = [1, 0, 3, 2, ..., 29, 28, 31, 30]

In general, mode t<w>_<r>x<c> reads an rxc row-major matrix of w-bit elements and returns its transpose: out[j*r+i] = in[i*c+j]. A mode whose matrix spans 1024 bits reads lhs:rhs and returns the lo or hi 512 bits. A mode whose matrix spans fewer than 512 bits reads lhs only and transposes each such block of it on its own. A mode t<w>_1x<c>_flip reverses the order of each group of c elements.

The modes 48 to 55 (t32_8x2, t32_2x8, t64_4x2, t64_2x4, t16_8x8_lo, t16_8x8_hi, t32_1x16_flip and t8_1x4_flip) exist on AIE2P only. Inside an aie.device of another architecture they are rejected.

The list of supported shuffle modes, required operands, and associated vector types are the following:

 Shuffle Mode       | Operands           | Types Supported
:------------------:|:------------------:|:------------------:
 t8_8x4             | `lhs`              | `vector<64xi8>`
 t8_4x8             | ^                  | ^
 t8_8x8             | ^                  | ^
 t8_16x4            | ^                  | ^
 t8_4x16            | ^                  | ^
 t8_1x4_flip (AIE2P)| ^                  | ^
 t8_64x2_lo         | `lhs` & `rhs`      | ^
 t8_64x2_hi         | ^                  | ^
 t8_2x64_lo         | ^                  | ^
 t8_2x64_hi         | ^                  | ^
 t16_4x2            | `lhs`              | `vector<32xi16>` or `vector<32xbf16>`
 t16_2x4            | ^                  | ^
 t16_4x4            | ^                  | ^
 t16_8x2            | ^                  | ^
 t16_2x8            | ^                  | ^
 t16_8x4            | ^                  | ^
 t16_4x8            | ^                  | ^
 t16_16x2           | ^                  | ^
 t16_2x16           | ^                  | ^
 t16_1x2_flip       | ^                  | ^
 t16_32x2_lo        | `lhs` & `rhs`      | ^
 t16_32x2_hi        | ^                  | ^
 t16_2x32_lo        | ^                  | ^
 t16_2x32_hi        | ^                  | ^
 t16_16x4_lo        | ^                  | ^
 t16_16x4_hi        | ^                  | ^
 t16_4x16_lo        | ^                  | ^
 t16_4x16_hi        | ^                  | ^
 t16_8x8_lo (AIE2P) | ^                  | ^
 t16_8x8_hi (AIE2P) | ^                  | ^
 t32_4x4            | `lhs`              | `vector<16xi32>` or `vector<16xf32>`
 t32_8x2 (AIE2P)    | ^                  | ^
 t32_2x8 (AIE2P)    | ^                  | ^
 t32_1x16_flip (AIE2P) | ^               | ^
 t32_16x2_lo        | `lhs` & `rhs`      | ^
 t32_16x2_hi        | ^                  | ^
 t32_2x16_lo        | ^                  | ^
 t32_2x16_hi        | ^                  | ^
 t32_8x4_lo         | ^                  | ^
 t32_8x4_hi         | ^                  | ^
 t32_4x8_lo         | ^                  | ^
 t32_4x8_hi         | ^                  | ^
 t64_4x2 (AIE2P)    | `lhs`              | `vector<8xi64>`
 t64_2x4 (AIE2P)    | ^                  | ^
 t64_8x2_lo         | `lhs` & `rhs`      | ^
 t64_8x2_hi         | ^                  | ^
 t64_2x8_lo         | ^                  | ^
 t64_2x8_hi         | ^                  | ^
 t128_4x2_lo        | ^                  | `vector<4xi128>`
 t128_4x2_hi        | ^                  | ^
 t128_2x4_lo        | ^                  | ^
 t128_2x4_hi        | ^                  | ^
 t256_2x2_lo        | ^                  | `vector<2xi256>`
 t256_2x2_hi        | ^                  | ^
 t512_1x2_lo        | ^                  | `vector<1xi512>`
 t512_1x2_hi        | ^                  | ^

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
mode::xilinx::aievec::ShuffleModeAttrShuffle mode for AIEVec shuffle operations

Operands:

Operand Description
lhs 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer or 128-bit signless integer or 256-bit signless integer or 512-bit signless integer or bfloat16 type or 32-bit float
rhs 512-bit wide vector, of 8-bit signless integer or 16-bit signless integer or 32-bit signless integer or 64-bit signless integer or 128-bit signless integer or 256-bit signless integer or 512-bit signless integer or bfloat16 type or 32-bit float

Results:

Result Description
result vector of any non-token type values

aievec.srs (::xilinx::aievec::SRSOp)

AIE srs

AMD-specific shift-round-saturate intrinsic. Moves values from accumulator data type to AIE vector data types. The adjustment in precision is controlled by the shift parameter. The sign parameter controls signed (1) vs unsigned (0) saturation. $result = srs($source, $shift, $sign)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
sign::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0 whose maximum value is 1

Operands:

Operand Description
source vector of any non-token type values
shift integer

Results:

Result Description
result vector of any non-token type values

aievec.sub_elem (::xilinx::aievec::SubElemOp)

AIE vector sub elem

Syntax:

operation ::= `aievec.sub_elem` $lhs `,` $rhs attr-dict `:` type($result)

AMD-specific AIE2 intrinsic that allows you to perform substraction operation on all types of vectors.$result =$lhs - $rhs`.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
lhs vector of any non-token type values
rhs vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.tanh (::xilinx::aievec::TanhOp)

AIE vector hyperbolic tangent

Syntax:

operation ::= `aievec.tanh` $source attr-dict `:` type($result)

AMD-specific intrinsic that computes the hyperbolic tangent of the input vector. For AIE2P, this is lowered to the hardware tanh intrinsic. $result = tanh($source`).

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.unpack (::xilinx::aievec::UnpackOp)

AIE unpack

AMD-specific unpack intrinsic. Unpack a vector of 8-bit values into a vector of 16-bit values. $result = unpack($source)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.upd (::xilinx::aievec::UPDOp)

AIE upd

AMD-specific update intrinsic. General upd intrinsic updates contiguous lanes of the result vector from a smaller source vector. This form of upd intrinsic combines the load of data from memory into a vector register, and then updating the lanes of the result vector using it. $result = upd($source[$indices], $offset, $index)

Traits: AlwaysSpeculatableImplTrait, AttrSizedOperandSegments

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
offset::mlir::IntegerAttr32-bit signless integer attribute
index::mlir::IntegerAttr8-bit signless integer attribute whose minimum value is 0 whose maximum value is 1

Operands:

Operand Description
source shaped of any non-token type values
indices variadic of index
vector vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

aievec.ups (::xilinx::aievec::UPSOp)

AIE ups

AMD-specific upshift intrinsic. Moves data from AIE vector data type to accumulator data type. The adjustment in precision is controlled by the shift parameter. $result = ups($source, $shift)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
shift::mlir::IntegerAttr8-bit signless integer attribute whose value is non-negative

Operands:

Operand Description
source vector of any non-token type values

Results:

Result Description
result vector of any non-token type values

Attributes

ShuffleModeAttr

Shuffle mode for AIEVec shuffle operations

Syntax:

#aievec.mode<
  `t8_64x2_lo` | `t8_64x2_hi` | `t16_32x2_lo` | `t16_32x2_hi` | `t32_16x2_lo` | `t32_16x2_hi` | `t64_8x2_lo` | `t64_8x2_hi` | `t128_4x2_lo` | `t128_4x2_hi` | `t256_2x2_lo` | `t256_2x2_hi` | `t128_2x4_lo` | `t128_2x4_hi` | `t64_2x8_lo` | `t64_2x8_hi` | `t32_2x16_lo` | `t32_2x16_hi` | `t16_2x32_lo` | `t16_2x32_hi` | `t8_2x64_lo` | `t8_2x64_hi` | `t512_1x2_lo` | `t512_1x2_hi` | `t16_16x4_lo` | `t16_16x4_hi` | `t16_4x16_lo` | `t16_4x16_hi` | `t16_8x4` | `t16_4x8` | `t32_8x4_lo` | `t32_8x4_hi` | `t32_4x8_lo` | `t32_4x8_hi` | `t32_4x4` | `t8_8x8` | `t8_16x4` | `t8_4x16` | `t16_1x2_flip` | `t16_4x4` | `t16_4x2` | `t16_2x4` | `t16_8x2` | `t16_2x8` | `t16_16x2` | `t16_2x16` | `t8_8x4` | `t8_4x8` | `t32_8x2` | `t32_2x8` | `t64_4x2` | `t64_2x4` | `t16_8x8_lo` | `t16_8x8_hi` | `t32_1x16_flip` | `t8_1x4_flip`   # value
>

Parameters:

Parameter C++ type Description
value ::xilinx::aievec::ShuffleMode an enum of type ShuffleMode

Enums

AIEArch

AIE Architecture

Cases:

Symbol Value String
AIE1 1 AIE1
AIE2 2 AIE2
AIE2p 3 AIE2p
AIE2ps 4 AIE2ps

AIEDevice

AIE Device

Cases:

Symbol Value String
xcvc1902 1 xcvc1902
xcve2302 2 xcve2302
xcve2802 3 xcve2802
npu1 4 npu1
npu1_1col 5 npu1_1col
npu1_2col 6 npu1_2col
npu1_3col 7 npu1_3col
npu2 8 npu2
npu2_1col 9 npu2_1col
npu2_2col 10 npu2_2col
npu2_3col 11 npu2_3col
npu2_4col 12 npu2_4col
npu2_5col 13 npu2_5col
npu2_6col 14 npu2_6col
npu2_7col 15 npu2_7col
xcve3858 16 xcve3858

AIETileType

Type of AIE Tile

Cases:

Symbol Value String
CoreTile 0 CoreTile
MemTile 1 MemTile
ShimNOCTile 2 ShimNOCTile
ShimPLTile 3 ShimPLTile

CascadeDir

Directions for cascade

Cases:

Symbol Value String
South 3 South
West 4 West
North 5 North
East 6 East

ComboLogic

Combo event logic function

Cases:

Symbol Value String
AND 0 AND
AND_NOT 1 AND_NOT
OR 2 OR
OR_NOT 3 OR_NOT

CoreEventAIE

Core module event enumeration for AIE

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT_0 5 PERF_CNT_0
PERF_CNT_1 6 PERF_CNT_1
PERF_CNT_2 7 PERF_CNT_2
PERF_CNT_3 8 PERF_CNT_3
COMBO_EVENT_0 9 COMBO_EVENT_0
COMBO_EVENT_1 10 COMBO_EVENT_1
COMBO_EVENT_2 11 COMBO_EVENT_2
COMBO_EVENT_3 12 COMBO_EVENT_3
GROUP_PC_EVENT 15 GROUP_PC_EVENT
PC_0 16 PC_0
PC_1 17 PC_1
PC_2 18 PC_2
PC_3 19 PC_3
PC_RANGE_0_1 20 PC_RANGE_0_1
PC_RANGE_2_3 21 PC_RANGE_2_3
GROUP_STALL 22 GROUP_STALL
MEMORY_STALL 23 MEMORY_STALL
STREAM_STALL 24 STREAM_STALL
CASCADE_STALL 25 CASCADE_STALL
LOCK_STALL 26 LOCK_STALL
DEBUG_HALTED 27 DEBUG_HALTED
ACTIVE 28 ACTIVE
DISABLED 29 DISABLED
ECC_ERROR_STALL 30 ECC_ERROR_STALL
ECC_SCRUBBING_STALL 31 ECC_SCRUBBING_STALL
GROUP_PROGRAM_FLOW 32 GROUP_PROGRAM_FLOW
INSTR_EVENT_0 33 INSTR_EVENT_0
INSTR_EVENT_1 34 INSTR_EVENT_1
INSTR_CALL 35 INSTR_CALL
INSTR_RETURN 36 INSTR_RETURN
INSTR_VECTOR 37 INSTR_VECTOR
INSTR_LOAD 38 INSTR_LOAD
INSTR_STORE 39 INSTR_STORE
INSTR_STREAM_GET 40 INSTR_STREAM_GET
INSTR_STREAM_PUT 41 INSTR_STREAM_PUT
INSTR_CASCADE_GET 42 INSTR_CASCADE_GET
INSTR_CASCADE_PUT 43 INSTR_CASCADE_PUT
INSTR_LOCK_ACQUIRE_REQ 44 INSTR_LOCK_ACQUIRE_REQ
INSTR_LOCK_RELEASE_REQ 45 INSTR_LOCK_RELEASE_REQ
GROUP_ERRORS_0 46 GROUP_ERRORS_0
GROUP_ERRORS_1 47 GROUP_ERRORS_1
SRS_SATURATE 48 SRS_SATURATE
UPS_SATURATE 49 UPS_SATURATE
FP_OVERFLOW 50 FP_OVERFLOW
FP_UNDERFLOW 51 FP_UNDERFLOW
FP_INVALID 52 FP_INVALID
FP_DIV_BY_ZERO 53 FP_DIV_BY_ZERO
TLAST_IN_WSS_WORDS_0_2 54 TLAST_IN_WSS_WORDS_0_2
PM_REG_ACCESS_FAILURE 55 PM_REG_ACCESS_FAILURE
STREAM_PKT_PARITY_ERROR 56 STREAM_PKT_PARITY_ERROR
CONTROL_PKT_ERROR 57 CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR 58 AXI_MM_SLAVE_ERROR
INSTR_DECOMPRSN_ERROR 59 INSTR_DECOMPRSN_ERROR
DM_ADDRESS_OUT_OF_RANGE 60 DM_ADDRESS_OUT_OF_RANGE
PM_ECC_ERROR_SCRUB_CORRECTED 61 PM_ECC_ERROR_SCRUB_CORRECTED
PM_ECC_ERROR_SCRUB_2BIT 62 PM_ECC_ERROR_SCRUB_2BIT
PM_ECC_ERROR_1BIT 63 PM_ECC_ERROR_1BIT
PM_ECC_ERROR_2BIT 64 PM_ECC_ERROR_2BIT
PM_ADDRESS_OUT_OF_RANGE 65 PM_ADDRESS_OUT_OF_RANGE
DM_ACCESS_TO_UNAVAILABLE 66 DM_ACCESS_TO_UNAVAILABLE
LOCK_ACCESS_TO_UNAVAILABLE 67 LOCK_ACCESS_TO_UNAVAILABLE
INSTR_EVENT_2 68 INSTR_EVENT_2
INSTR_EVENT_3 69 INSTR_EVENT_3
GROUP_STREAM_SWITCH 73 GROUP_STREAM_SWITCH
PORT_IDLE_0 74 PORT_IDLE_0
PORT_RUNNING_0 75 PORT_RUNNING_0
PORT_STALLED_0 76 PORT_STALLED_0
PORT_TLAST_0 77 PORT_TLAST_0
PORT_IDLE_1 78 PORT_IDLE_1
PORT_RUNNING_1 79 PORT_RUNNING_1
PORT_STALLED_1 80 PORT_STALLED_1
PORT_TLAST_1 81 PORT_TLAST_1
PORT_IDLE_2 82 PORT_IDLE_2
PORT_RUNNING_2 83 PORT_RUNNING_2
PORT_STALLED_2 84 PORT_STALLED_2
PORT_TLAST_2 85 PORT_TLAST_2
PORT_IDLE_3 86 PORT_IDLE_3
PORT_RUNNING_3 87 PORT_RUNNING_3
PORT_STALLED_3 88 PORT_STALLED_3
PORT_TLAST_3 89 PORT_TLAST_3
PORT_IDLE_4 90 PORT_IDLE_4
PORT_RUNNING_4 91 PORT_RUNNING_4
PORT_STALLED_4 92 PORT_STALLED_4
PORT_TLAST_4 93 PORT_TLAST_4
PORT_IDLE_5 94 PORT_IDLE_5
PORT_RUNNING_5 95 PORT_RUNNING_5
PORT_STALLED_5 96 PORT_STALLED_5
PORT_TLAST_5 97 PORT_TLAST_5
PORT_IDLE_6 98 PORT_IDLE_6
PORT_RUNNING_6 99 PORT_RUNNING_6
PORT_STALLED_6 100 PORT_STALLED_6
PORT_TLAST_6 101 PORT_TLAST_6
PORT_IDLE_7 102 PORT_IDLE_7
PORT_RUNNING_7 103 PORT_RUNNING_7
PORT_STALLED_7 104 PORT_STALLED_7
PORT_TLAST_7 105 PORT_TLAST_7
GROUP_BROADCAST 106 GROUP_BROADCAST
BROADCAST_0 107 BROADCAST_0
BROADCAST_1 108 BROADCAST_1
BROADCAST_2 109 BROADCAST_2
BROADCAST_3 110 BROADCAST_3
BROADCAST_4 111 BROADCAST_4
BROADCAST_5 112 BROADCAST_5
BROADCAST_6 113 BROADCAST_6
BROADCAST_7 114 BROADCAST_7
BROADCAST_8 115 BROADCAST_8
BROADCAST_9 116 BROADCAST_9
BROADCAST_10 117 BROADCAST_10
BROADCAST_11 118 BROADCAST_11
BROADCAST_12 119 BROADCAST_12
BROADCAST_13 120 BROADCAST_13
BROADCAST_14 121 BROADCAST_14
BROADCAST_15 122 BROADCAST_15
GROUP_USER_EVENT 123 GROUP_USER_EVENT
USER_EVENT_0 124 USER_EVENT_0
USER_EVENT_1 125 USER_EVENT_1
USER_EVENT_2 126 USER_EVENT_2
USER_EVENT_3 127 USER_EVENT_3

CoreEventAIE2

Core module event enumeration for AIE2

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT_0 5 PERF_CNT_0
PERF_CNT_1 6 PERF_CNT_1
PERF_CNT_2 7 PERF_CNT_2
PERF_CNT_3 8 PERF_CNT_3
COMBO_EVENT_0 9 COMBO_EVENT_0
COMBO_EVENT_1 10 COMBO_EVENT_1
COMBO_EVENT_2 11 COMBO_EVENT_2
COMBO_EVENT_3 12 COMBO_EVENT_3
EDGE_DETECTION_EVENT_0 13 EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1 14 EDGE_DETECTION_EVENT_1
GROUP_PC_EVENT 15 GROUP_PC_EVENT
PC_0 16 PC_0
PC_1 17 PC_1
PC_2 18 PC_2
PC_3 19 PC_3
PC_RANGE_0_1 20 PC_RANGE_0_1
PC_RANGE_2_3 21 PC_RANGE_2_3
GROUP_STALL 22 GROUP_STALL
MEMORY_STALL 23 MEMORY_STALL
STREAM_STALL 24 STREAM_STALL
CASCADE_STALL 25 CASCADE_STALL
LOCK_STALL 26 LOCK_STALL
DEBUG_HALTED 27 DEBUG_HALTED
ACTIVE 28 ACTIVE
DISABLED 29 DISABLED
ECC_ERROR_STALL 30 ECC_ERROR_STALL
ECC_SCRUBBING_STALL 31 ECC_SCRUBBING_STALL
GROUP_PROGRAM_FLOW 32 GROUP_PROGRAM_FLOW
INSTR_EVENT_0 33 INSTR_EVENT_0
INSTR_EVENT_1 34 INSTR_EVENT_1
INSTR_CALL 35 INSTR_CALL
INSTR_RETURN 36 INSTR_RETURN
INSTR_VECTOR 37 INSTR_VECTOR
INSTR_LOAD 38 INSTR_LOAD
INSTR_STORE 39 INSTR_STORE
INSTR_STREAM_GET 40 INSTR_STREAM_GET
INSTR_STREAM_PUT 41 INSTR_STREAM_PUT
INSTR_CASCADE_GET 42 INSTR_CASCADE_GET
INSTR_CASCADE_PUT 43 INSTR_CASCADE_PUT
INSTR_LOCK_ACQUIRE_REQ 44 INSTR_LOCK_ACQUIRE_REQ
INSTR_LOCK_RELEASE_REQ 45 INSTR_LOCK_RELEASE_REQ
GROUP_ERRORS_0 46 GROUP_ERRORS_0
GROUP_ERRORS_1 47 GROUP_ERRORS_1
SRS_OVERFLOW 48 SRS_OVERFLOW
UPS_OVERFLOW 49 UPS_OVERFLOW
FP_HUGE 50 FP_HUGE
INT_FP_0 51 INT_FP_0
FP_INVALID 52 FP_INVALID
FP_INF 53 FP_INF
PM_REG_ACCESS_FAILURE 55 PM_REG_ACCESS_FAILURE
STREAM_PKT_PARITY_ERROR 56 STREAM_PKT_PARITY_ERROR
CONTROL_PKT_ERROR 57 CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR 58 AXI_MM_SLAVE_ERROR
INSTR_DECOMPRSN_ERROR 59 INSTR_DECOMPRSN_ERROR
DM_ADDRESS_OUT_OF_RANGE 60 DM_ADDRESS_OUT_OF_RANGE
PM_ECC_ERROR_SCRUB_CORRECTED 61 PM_ECC_ERROR_SCRUB_CORRECTED
PM_ECC_ERROR_SCRUB_2BIT 62 PM_ECC_ERROR_SCRUB_2BIT
PM_ECC_ERROR_1BIT 63 PM_ECC_ERROR_1BIT
PM_ECC_ERROR_2BIT 64 PM_ECC_ERROR_2BIT
PM_ADDRESS_OUT_OF_RANGE 65 PM_ADDRESS_OUT_OF_RANGE
DM_ACCESS_TO_UNAVAILABLE 66 DM_ACCESS_TO_UNAVAILABLE
LOCK_ACCESS_TO_UNAVAILABLE 67 LOCK_ACCESS_TO_UNAVAILABLE
INSTR_WARNING 68 INSTR_WARNING
INSTR_ERROR 69 INSTR_ERROR
DECOMPRESSION_UNDERFLOW 70 DECOMPRESSION_UNDERFLOW
STREAM_SWITCH_PORT_PARITY_ERROR 71 STREAM_SWITCH_PORT_PARITY_ERROR
PROCESSOR_BUS_ERROR 72 PROCESSOR_BUS_ERROR
GROUP_STREAM_SWITCH 73 GROUP_STREAM_SWITCH
PORT_IDLE_0 74 PORT_IDLE_0
PORT_RUNNING_0 75 PORT_RUNNING_0
PORT_STALLED_0 76 PORT_STALLED_0
PORT_TLAST_0 77 PORT_TLAST_0
PORT_IDLE_1 78 PORT_IDLE_1
PORT_RUNNING_1 79 PORT_RUNNING_1
PORT_STALLED_1 80 PORT_STALLED_1
PORT_TLAST_1 81 PORT_TLAST_1
PORT_IDLE_2 82 PORT_IDLE_2
PORT_RUNNING_2 83 PORT_RUNNING_2
PORT_STALLED_2 84 PORT_STALLED_2
PORT_TLAST_2 85 PORT_TLAST_2
PORT_IDLE_3 86 PORT_IDLE_3
PORT_RUNNING_3 87 PORT_RUNNING_3
PORT_STALLED_3 88 PORT_STALLED_3
PORT_TLAST_3 89 PORT_TLAST_3
PORT_IDLE_4 90 PORT_IDLE_4
PORT_RUNNING_4 91 PORT_RUNNING_4
PORT_STALLED_4 92 PORT_STALLED_4
PORT_TLAST_4 93 PORT_TLAST_4
PORT_IDLE_5 94 PORT_IDLE_5
PORT_RUNNING_5 95 PORT_RUNNING_5
PORT_STALLED_5 96 PORT_STALLED_5
PORT_TLAST_5 97 PORT_TLAST_5
PORT_IDLE_6 98 PORT_IDLE_6
PORT_RUNNING_6 99 PORT_RUNNING_6
PORT_STALLED_6 100 PORT_STALLED_6
PORT_TLAST_6 101 PORT_TLAST_6
PORT_IDLE_7 102 PORT_IDLE_7
PORT_RUNNING_7 103 PORT_RUNNING_7
PORT_STALLED_7 104 PORT_STALLED_7
PORT_TLAST_7 105 PORT_TLAST_7
GROUP_BROADCAST 106 GROUP_BROADCAST
BROADCAST_0 107 BROADCAST_0
BROADCAST_1 108 BROADCAST_1
BROADCAST_2 109 BROADCAST_2
BROADCAST_3 110 BROADCAST_3
BROADCAST_4 111 BROADCAST_4
BROADCAST_5 112 BROADCAST_5
BROADCAST_6 113 BROADCAST_6
BROADCAST_7 114 BROADCAST_7
BROADCAST_8 115 BROADCAST_8
BROADCAST_9 116 BROADCAST_9
BROADCAST_10 117 BROADCAST_10
BROADCAST_11 118 BROADCAST_11
BROADCAST_12 119 BROADCAST_12
BROADCAST_13 120 BROADCAST_13
BROADCAST_14 121 BROADCAST_14
BROADCAST_15 122 BROADCAST_15
GROUP_USER_EVENT 123 GROUP_USER_EVENT
USER_EVENT_0 124 USER_EVENT_0
USER_EVENT_1 125 USER_EVENT_1
USER_EVENT_2 126 USER_EVENT_2
USER_EVENT_3 127 USER_EVENT_3

CoreEventAIE2P

Core module event enumeration for AIE2P

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT_0 5 PERF_CNT_0
PERF_CNT_1 6 PERF_CNT_1
PERF_CNT_2 7 PERF_CNT_2
PERF_CNT_3 8 PERF_CNT_3
COMBO_EVENT_0 9 COMBO_EVENT_0
COMBO_EVENT_1 10 COMBO_EVENT_1
COMBO_EVENT_2 11 COMBO_EVENT_2
COMBO_EVENT_3 12 COMBO_EVENT_3
EDGE_DETECTION_EVENT_0 13 EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1 14 EDGE_DETECTION_EVENT_1
GROUP_PC_EVENT 15 GROUP_PC_EVENT
PC_0 16 PC_0
PC_1 17 PC_1
PC_2 18 PC_2
PC_3 19 PC_3
PC_RANGE_0_1 20 PC_RANGE_0_1
PC_RANGE_2_3 21 PC_RANGE_2_3
GROUP_STALL 22 GROUP_STALL
MEMORY_STALL 23 MEMORY_STALL
STREAM_STALL 24 STREAM_STALL
CASCADE_STALL 25 CASCADE_STALL
LOCK_STALL 26 LOCK_STALL
DEBUG_HALTED 27 DEBUG_HALTED
ACTIVE 28 ACTIVE
DISABLED 29 DISABLED
ECC_ERROR_STALL 30 ECC_ERROR_STALL
ECC_SCRUBBING_STALL 31 ECC_SCRUBBING_STALL
GROUP_PROGRAM_FLOW 32 GROUP_PROGRAM_FLOW
INSTR_EVENT_0 33 INSTR_EVENT_0
INSTR_EVENT_1 34 INSTR_EVENT_1
INSTR_CALL 35 INSTR_CALL
INSTR_RETURN 36 INSTR_RETURN
INSTR_VECTOR 37 INSTR_VECTOR
INSTR_LOAD 38 INSTR_LOAD
INSTR_STORE 39 INSTR_STORE
INSTR_STREAM_GET 40 INSTR_STREAM_GET
INSTR_STREAM_PUT 41 INSTR_STREAM_PUT
INSTR_CASCADE_GET 42 INSTR_CASCADE_GET
INSTR_CASCADE_PUT 43 INSTR_CASCADE_PUT
INSTR_LOCK_ACQUIRE_REQ 44 INSTR_LOCK_ACQUIRE_REQ
INSTR_LOCK_RELEASE_REQ 45 INSTR_LOCK_RELEASE_REQ
GROUP_ERRORS_0 46 GROUP_ERRORS_0
GROUP_ERRORS_1 47 GROUP_ERRORS_1
SRS_OVERFLOW 48 SRS_OVERFLOW
UPS_OVERFLOW 49 UPS_OVERFLOW
FP_HUGE 50 FP_HUGE
INT_FP_0 51 INT_FP_0
FP_INVALID 52 FP_INVALID
FP_INF 53 FP_INF
PM_REG_ACCESS_FAILURE 55 PM_REG_ACCESS_FAILURE
STREAM_PKT_PARITY_ERROR 56 STREAM_PKT_PARITY_ERROR
CONTROL_PKT_ERROR 57 CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR 58 AXI_MM_SLAVE_ERROR
INSTR_DECOMPRSN_ERROR 59 INSTR_DECOMPRSN_ERROR
DM_ADDRESS_OUT_OF_RANGE 60 DM_ADDRESS_OUT_OF_RANGE
PM_ECC_ERROR_SCRUB_CORRECTED 61 PM_ECC_ERROR_SCRUB_CORRECTED
PM_ECC_ERROR_SCRUB_2BIT 62 PM_ECC_ERROR_SCRUB_2BIT
PM_ECC_ERROR_1BIT 63 PM_ECC_ERROR_1BIT
PM_ECC_ERROR_2BIT 64 PM_ECC_ERROR_2BIT
PM_ADDRESS_OUT_OF_RANGE 65 PM_ADDRESS_OUT_OF_RANGE
DM_ACCESS_TO_UNAVAILABLE 66 DM_ACCESS_TO_UNAVAILABLE
LOCK_ACCESS_TO_UNAVAILABLE 67 LOCK_ACCESS_TO_UNAVAILABLE
INSTR_WARNING 68 INSTR_WARNING
INSTR_ERROR 69 INSTR_ERROR
SPARSITY_OVERFLOW 70 SPARSITY_OVERFLOW
STREAM_SWITCH_PORT_PARITY_ERROR 71 STREAM_SWITCH_PORT_PARITY_ERROR
PROCESSOR_BUS_ERROR 72 PROCESSOR_BUS_ERROR
GROUP_STREAM_SWITCH 73 GROUP_STREAM_SWITCH
PORT_IDLE_0 74 PORT_IDLE_0
PORT_RUNNING_0 75 PORT_RUNNING_0
PORT_STALLED_0 76 PORT_STALLED_0
PORT_TLAST_0 77 PORT_TLAST_0
PORT_IDLE_1 78 PORT_IDLE_1
PORT_RUNNING_1 79 PORT_RUNNING_1
PORT_STALLED_1 80 PORT_STALLED_1
PORT_TLAST_1 81 PORT_TLAST_1
PORT_IDLE_2 82 PORT_IDLE_2
PORT_RUNNING_2 83 PORT_RUNNING_2
PORT_STALLED_2 84 PORT_STALLED_2
PORT_TLAST_2 85 PORT_TLAST_2
PORT_IDLE_3 86 PORT_IDLE_3
PORT_RUNNING_3 87 PORT_RUNNING_3
PORT_STALLED_3 88 PORT_STALLED_3
PORT_TLAST_3 89 PORT_TLAST_3
PORT_IDLE_4 90 PORT_IDLE_4
PORT_RUNNING_4 91 PORT_RUNNING_4
PORT_STALLED_4 92 PORT_STALLED_4
PORT_TLAST_4 93 PORT_TLAST_4
PORT_IDLE_5 94 PORT_IDLE_5
PORT_RUNNING_5 95 PORT_RUNNING_5
PORT_STALLED_5 96 PORT_STALLED_5
PORT_TLAST_5 97 PORT_TLAST_5
PORT_IDLE_6 98 PORT_IDLE_6
PORT_RUNNING_6 99 PORT_RUNNING_6
PORT_STALLED_6 100 PORT_STALLED_6
PORT_TLAST_6 101 PORT_TLAST_6
PORT_IDLE_7 102 PORT_IDLE_7
PORT_RUNNING_7 103 PORT_RUNNING_7
PORT_STALLED_7 104 PORT_STALLED_7
PORT_TLAST_7 105 PORT_TLAST_7
GROUP_BROADCAST 106 GROUP_BROADCAST
BROADCAST_0 107 BROADCAST_0
BROADCAST_1 108 BROADCAST_1
BROADCAST_2 109 BROADCAST_2
BROADCAST_3 110 BROADCAST_3
BROADCAST_4 111 BROADCAST_4
BROADCAST_5 112 BROADCAST_5
BROADCAST_6 113 BROADCAST_6
BROADCAST_7 114 BROADCAST_7
BROADCAST_8 115 BROADCAST_8
BROADCAST_9 116 BROADCAST_9
BROADCAST_10 117 BROADCAST_10
BROADCAST_11 118 BROADCAST_11
BROADCAST_12 119 BROADCAST_12
BROADCAST_13 120 BROADCAST_13
BROADCAST_14 121 BROADCAST_14
BROADCAST_15 122 BROADCAST_15
GROUP_USER_EVENT 123 GROUP_USER_EVENT
USER_EVENT_0 124 USER_EVENT_0
USER_EVENT_1 125 USER_EVENT_1
USER_EVENT_2 126 USER_EVENT_2
USER_EVENT_3 127 USER_EVENT_3

DMAChannelDir

DMA Channel direction

Cases:

Symbol Value String
S2MM 0 S2MM
MM2S 1 MM2S

EdgeTrigger

Edge detection trigger mode

Cases:

Symbol Value String
RISING 1 RISING
FALLING 2 FALLING
BOTH 3 BOTH

LockAction

Lock acquire/release

Cases:

Symbol Value String
Acquire 0 Acquire
AcquireGreaterEqual 2 AcquireGreaterEqual
Release 1 Release

LockBlocking

Lock operation is blocking

Cases:

Symbol Value String
NonBlocking 0 NonBlocking
Blocking 1 Blocking

MemEventAIE

Memory module event enumeration for AIE

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT_0 5 PERF_CNT_0
PERF_CNT_1 6 PERF_CNT_1
COMBO_EVENT_0 7 COMBO_EVENT_0
COMBO_EVENT_1 8 COMBO_EVENT_1
COMBO_EVENT_2 9 COMBO_EVENT_2
COMBO_EVENT_3 10 COMBO_EVENT_3
GROUP_WATCHPOINT 15 GROUP_WATCHPOINT
WATCHPOINT_0 16 WATCHPOINT_0
WATCHPOINT_1 17 WATCHPOINT_1
GROUP_DMA_ACTIVITY 20 GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_BD 21 DMA_S2MM_0_START_BD
DMA_S2MM_1_START_BD 22 DMA_S2MM_1_START_BD
DMA_MM2S_0_START_BD 23 DMA_MM2S_0_START_BD
DMA_MM2S_1_START_BD 24 DMA_MM2S_1_START_BD
DMA_S2MM_0_FINISHED_BD 25 DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD 26 DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD 27 DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD 28 DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_GO_TO_IDLE 29 DMA_S2MM_0_GO_TO_IDLE
DMA_S2MM_1_GO_TO_IDLE 30 DMA_S2MM_1_GO_TO_IDLE
DMA_MM2S_0_GO_TO_IDLE 31 DMA_MM2S_0_GO_TO_IDLE
DMA_MM2S_1_GO_TO_IDLE 32 DMA_MM2S_1_GO_TO_IDLE
DMA_S2MM_0_STALLED_LOCK_ACQUIRE 33 DMA_S2MM_0_STALLED_LOCK_ACQUIRE
DMA_S2MM_1_STALLED_LOCK_ACQUIRE 34 DMA_S2MM_1_STALLED_LOCK_ACQUIRE
DMA_MM2S_0_STALLED_LOCK_ACQUIRE 35 DMA_MM2S_0_STALLED_LOCK_ACQUIRE
DMA_MM2S_1_STALLED_LOCK_ACQUIRE 36 DMA_MM2S_1_STALLED_LOCK_ACQUIRE
DMA_S2MM_0_MEMORY_CONFLICT 37 DMA_S2MM_0_MEMORY_CONFLICT
DMA_S2MM_1_MEMORY_CONFLICT 38 DMA_S2MM_1_MEMORY_CONFLICT
DMA_MM2S_0_MEMORY_CONFLICT 39 DMA_MM2S_0_MEMORY_CONFLICT
DMA_MM2S_1_MEMORY_CONFLICT 40 DMA_MM2S_1_MEMORY_CONFLICT
GROUP_LOCK 43 GROUP_LOCK
LOCK_0_ACQ 44 LOCK_0_ACQ
LOCK_0_REL 45 LOCK_0_REL
LOCK_1_ACQ 46 LOCK_1_ACQ
LOCK_1_REL 47 LOCK_1_REL
LOCK_2_ACQ 48 LOCK_2_ACQ
LOCK_2_REL 49 LOCK_2_REL
LOCK_3_ACQ 50 LOCK_3_ACQ
LOCK_3_REL 51 LOCK_3_REL
LOCK_4_ACQ 52 LOCK_4_ACQ
LOCK_4_REL 53 LOCK_4_REL
LOCK_5_ACQ 54 LOCK_5_ACQ
LOCK_5_REL 55 LOCK_5_REL
LOCK_6_ACQ 56 LOCK_6_ACQ
LOCK_6_REL 57 LOCK_6_REL
LOCK_7_ACQ 58 LOCK_7_ACQ
LOCK_7_REL 59 LOCK_7_REL
LOCK_8_ACQ 60 LOCK_8_ACQ
LOCK_8_REL 61 LOCK_8_REL
LOCK_9_ACQ 62 LOCK_9_ACQ
LOCK_9_REL 63 LOCK_9_REL
LOCK_10_ACQ 64 LOCK_10_ACQ
LOCK_10_REL 65 LOCK_10_REL
LOCK_11_ACQ 66 LOCK_11_ACQ
LOCK_11_REL 67 LOCK_11_REL
LOCK_12_ACQ 68 LOCK_12_ACQ
LOCK_12_REL 69 LOCK_12_REL
LOCK_13_ACQ 70 LOCK_13_ACQ
LOCK_13_REL 71 LOCK_13_REL
LOCK_14_ACQ 72 LOCK_14_ACQ
LOCK_14_REL 73 LOCK_14_REL
LOCK_15_ACQ 74 LOCK_15_ACQ
LOCK_15_REL 75 LOCK_15_REL
GROUP_MEMORY_CONFLICT 76 GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0 77 CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1 78 CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2 79 CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3 80 CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4 81 CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5 82 CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6 83 CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7 84 CONFLICT_DM_BANK_7
GROUP_ERRORS 86 GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED 87 DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT 88 DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT 89 DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT 90 DM_ECC_ERROR_2BIT
DM_PARITY_ERROR_BANK_2 91 DM_PARITY_ERROR_BANK_2
DM_PARITY_ERROR_BANK_3 92 DM_PARITY_ERROR_BANK_3
DM_PARITY_ERROR_BANK_4 93 DM_PARITY_ERROR_BANK_4
DM_PARITY_ERROR_BANK_5 94 DM_PARITY_ERROR_BANK_5
DM_PARITY_ERROR_BANK_6 95 DM_PARITY_ERROR_BANK_6
DM_PARITY_ERROR_BANK_7 96 DM_PARITY_ERROR_BANK_7
DMA_S2MM_0_ERROR 97 DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR 98 DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR 99 DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR 100 DMA_MM2S_1_ERROR
GROUP_BROADCAST 106 GROUP_BROADCAST
BROADCAST_0 107 BROADCAST_0
BROADCAST_1 108 BROADCAST_1
BROADCAST_2 109 BROADCAST_2
BROADCAST_3 110 BROADCAST_3
BROADCAST_4 111 BROADCAST_4
BROADCAST_5 112 BROADCAST_5
BROADCAST_6 113 BROADCAST_6
BROADCAST_7 114 BROADCAST_7
BROADCAST_8 115 BROADCAST_8
BROADCAST_9 116 BROADCAST_9
BROADCAST_10 117 BROADCAST_10
BROADCAST_11 118 BROADCAST_11
BROADCAST_12 119 BROADCAST_12
BROADCAST_13 120 BROADCAST_13
BROADCAST_14 121 BROADCAST_14
BROADCAST_15 122 BROADCAST_15
GROUP_USER_EVENT 123 GROUP_USER_EVENT
USER_EVENT_0 124 USER_EVENT_0
USER_EVENT_1 125 USER_EVENT_1
USER_EVENT_2 126 USER_EVENT_2
USER_EVENT_3 127 USER_EVENT_3

MemEventAIE2

Memory module event enumeration for AIE2

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT_0 5 PERF_CNT_0
PERF_CNT_1 6 PERF_CNT_1
COMBO_EVENT_0 7 COMBO_EVENT_0
COMBO_EVENT_1 8 COMBO_EVENT_1
COMBO_EVENT_2 9 COMBO_EVENT_2
COMBO_EVENT_3 10 COMBO_EVENT_3
EDGE_DETECTION_EVENT_0 11 EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1 12 EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT 15 GROUP_WATCHPOINT
WATCHPOINT_0 16 WATCHPOINT_0
WATCHPOINT_1 17 WATCHPOINT_1
GROUP_DMA_ACTIVITY 18 GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK 19 DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK 20 DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK 21 DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK 22 DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD 23 DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD 24 DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD 25 DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD 26 DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK 27 DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK 28 DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK 29 DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK 30 DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK 31 DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK 32 DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK 33 DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK 34 DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION 35 DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION 36 DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE 37 DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE 38 DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE 39 DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE 40 DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION 41 DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION 42 DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK 43 GROUP_LOCK
LOCK_SEL0_ACQ_EQ 44 LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE 45 LOCK_SEL0_ACQ_GE
LOCK_0_REL 46 LOCK_0_REL
LOCK_SEL0_EQUAL_TO_VALUE 47 LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ 48 LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE 49 LOCK_SEL1_ACQ_GE
LOCK_1_REL 50 LOCK_1_REL
LOCK_SEL1_EQUAL_TO_VALUE 51 LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ 52 LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE 53 LOCK_SEL2_ACQ_GE
LOCK_2_REL 54 LOCK_2_REL
LOCK_SEL2_EQUAL_TO_VALUE 55 LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ 56 LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE 57 LOCK_SEL3_ACQ_GE
LOCK_3_REL 58 LOCK_3_REL
LOCK_SEL3_EQUAL_TO_VALUE 59 LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ 60 LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE 61 LOCK_SEL4_ACQ_GE
LOCK_4_REL 62 LOCK_4_REL
LOCK_SEL4_EQUAL_TO_VALUE 63 LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ 64 LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE 65 LOCK_SEL5_ACQ_GE
LOCK_5_REL 66 LOCK_5_REL
LOCK_SEL5_EQUAL_TO_VALUE 67 LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ 68 LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE 69 LOCK_SEL6_ACQ_GE
LOCK_6_REL 70 LOCK_6_REL
LOCK_SEL6_EQUAL_TO_VALUE 71 LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ 72 LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE 73 LOCK_SEL7_ACQ_GE
LOCK_7_REL 74 LOCK_7_REL
LOCK_SEL7_EQUAL_TO_VALUE 75 LOCK_SEL7_EQUAL_TO_VALUE
GROUP_MEMORY_CONFLICT 76 GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0 77 CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1 78 CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2 79 CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3 80 CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4 81 CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5 82 CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6 83 CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7 84 CONFLICT_DM_BANK_7
GROUP_ERRORS 86 GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED 87 DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT 88 DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT 89 DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT 90 DM_ECC_ERROR_2BIT
DM_PARITY_ERROR_BANK_2 91 DM_PARITY_ERROR_BANK_2
DM_PARITY_ERROR_BANK_3 92 DM_PARITY_ERROR_BANK_3
DM_PARITY_ERROR_BANK_4 93 DM_PARITY_ERROR_BANK_4
DM_PARITY_ERROR_BANK_5 94 DM_PARITY_ERROR_BANK_5
DM_PARITY_ERROR_BANK_6 95 DM_PARITY_ERROR_BANK_6
DM_PARITY_ERROR_BANK_7 96 DM_PARITY_ERROR_BANK_7
DMA_S2MM_0_ERROR 97 DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR 98 DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR 99 DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR 100 DMA_MM2S_1_ERROR
LOCK_ERROR 101 LOCK_ERROR
DMA_TASK_TOKEN_STALL 102 DMA_TASK_TOKEN_STALL
GROUP_BROADCAST 106 GROUP_BROADCAST
BROADCAST_0 107 BROADCAST_0
BROADCAST_1 108 BROADCAST_1
BROADCAST_2 109 BROADCAST_2
BROADCAST_3 110 BROADCAST_3
BROADCAST_4 111 BROADCAST_4
BROADCAST_5 112 BROADCAST_5
BROADCAST_6 113 BROADCAST_6
BROADCAST_7 114 BROADCAST_7
BROADCAST_8 115 BROADCAST_8
BROADCAST_9 116 BROADCAST_9
BROADCAST_10 117 BROADCAST_10
BROADCAST_11 118 BROADCAST_11
BROADCAST_12 119 BROADCAST_12
BROADCAST_13 120 BROADCAST_13
BROADCAST_14 121 BROADCAST_14
BROADCAST_15 122 BROADCAST_15
GROUP_USER_EVENT 123 GROUP_USER_EVENT
USER_EVENT_0 124 USER_EVENT_0
USER_EVENT_1 125 USER_EVENT_1
USER_EVENT_2 126 USER_EVENT_2
USER_EVENT_3 127 USER_EVENT_3

MemEventAIE2P

Memory module event enumeration for AIE2P

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT_0 5 PERF_CNT_0
PERF_CNT_1 6 PERF_CNT_1
COMBO_EVENT_0 7 COMBO_EVENT_0
COMBO_EVENT_1 8 COMBO_EVENT_1
COMBO_EVENT_2 9 COMBO_EVENT_2
COMBO_EVENT_3 10 COMBO_EVENT_3
EDGE_DETECTION_EVENT_0 11 EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1 12 EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT 15 GROUP_WATCHPOINT
WATCHPOINT_0 16 WATCHPOINT_0
WATCHPOINT_1 17 WATCHPOINT_1
GROUP_DMA_ACTIVITY 18 GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK 19 DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK 20 DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK 21 DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK 22 DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD 23 DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD 24 DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD 25 DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD 26 DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK 27 DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK 28 DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK 29 DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK 30 DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK 31 DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK 32 DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK 33 DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK 34 DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION 35 DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION 36 DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE 37 DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE 38 DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE 39 DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE 40 DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION 41 DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION 42 DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK 43 GROUP_LOCK
LOCK_SEL0_ACQ_EQ 44 LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE 45 LOCK_SEL0_ACQ_GE
LOCK_0_REL 46 LOCK_0_REL
LOCK_SEL0_EQUAL_TO_VALUE 47 LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ 48 LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE 49 LOCK_SEL1_ACQ_GE
LOCK_1_REL 50 LOCK_1_REL
LOCK_SEL1_EQUAL_TO_VALUE 51 LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ 52 LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE 53 LOCK_SEL2_ACQ_GE
LOCK_2_REL 54 LOCK_2_REL
LOCK_SEL2_EQUAL_TO_VALUE 55 LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ 56 LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE 57 LOCK_SEL3_ACQ_GE
LOCK_3_REL 58 LOCK_3_REL
LOCK_SEL3_EQUAL_TO_VALUE 59 LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ 60 LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE 61 LOCK_SEL4_ACQ_GE
LOCK_4_REL 62 LOCK_4_REL
LOCK_SEL4_EQUAL_TO_VALUE 63 LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ 64 LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE 65 LOCK_SEL5_ACQ_GE
LOCK_5_REL 66 LOCK_5_REL
LOCK_SEL5_EQUAL_TO_VALUE 67 LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ 68 LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE 69 LOCK_SEL6_ACQ_GE
LOCK_6_REL 70 LOCK_6_REL
LOCK_SEL6_EQUAL_TO_VALUE 71 LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ 72 LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE 73 LOCK_SEL7_ACQ_GE
LOCK_7_REL 74 LOCK_7_REL
LOCK_SEL7_EQUAL_TO_VALUE 75 LOCK_SEL7_EQUAL_TO_VALUE
GROUP_MEMORY_CONFLICT 76 GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0 77 CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1 78 CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2 79 CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3 80 CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4 81 CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5 82 CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6 83 CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7 84 CONFLICT_DM_BANK_7
GROUP_ERRORS 86 GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED 87 DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT 88 DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT 89 DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT 90 DM_ECC_ERROR_2BIT
DM_PARITY_ERROR_BANK_2 91 DM_PARITY_ERROR_BANK_2
DM_PARITY_ERROR_BANK_3 92 DM_PARITY_ERROR_BANK_3
DM_PARITY_ERROR_BANK_4 93 DM_PARITY_ERROR_BANK_4
DM_PARITY_ERROR_BANK_5 94 DM_PARITY_ERROR_BANK_5
DM_PARITY_ERROR_BANK_6 95 DM_PARITY_ERROR_BANK_6
DM_PARITY_ERROR_BANK_7 96 DM_PARITY_ERROR_BANK_7
DMA_S2MM_0_ERROR 97 DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR 98 DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR 99 DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR 100 DMA_MM2S_1_ERROR
LOCK_ERROR 101 LOCK_ERROR
DMA_TASK_TOKEN_STALL 102 DMA_TASK_TOKEN_STALL
GROUP_BROADCAST 106 GROUP_BROADCAST
BROADCAST_0 107 BROADCAST_0
BROADCAST_1 108 BROADCAST_1
BROADCAST_2 109 BROADCAST_2
BROADCAST_3 110 BROADCAST_3
BROADCAST_4 111 BROADCAST_4
BROADCAST_5 112 BROADCAST_5
BROADCAST_6 113 BROADCAST_6
BROADCAST_7 114 BROADCAST_7
BROADCAST_8 115 BROADCAST_8
BROADCAST_9 116 BROADCAST_9
BROADCAST_10 117 BROADCAST_10
BROADCAST_11 118 BROADCAST_11
BROADCAST_12 119 BROADCAST_12
BROADCAST_13 120 BROADCAST_13
BROADCAST_14 121 BROADCAST_14
BROADCAST_15 122 BROADCAST_15
GROUP_USER_EVENT 123 GROUP_USER_EVENT
USER_EVENT_0 124 USER_EVENT_0
USER_EVENT_1 125 USER_EVENT_1
USER_EVENT_2 126 USER_EVENT_2
USER_EVENT_3 127 USER_EVENT_3

MemTileEventAIE

Memory tile event enumeration for AIE

Cases:

Symbol Value String

MemTileEventAIE2

Memory tile event enumeration for AIE2

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT0_EVENT 5 PERF_CNT0_EVENT
PERF_CNT1_EVENT 6 PERF_CNT1_EVENT
PERF_CNT2_EVENT 7 PERF_CNT2_EVENT
PERF_CNT3_EVENT 8 PERF_CNT3_EVENT
COMBO_EVENT_0 9 COMBO_EVENT_0
COMBO_EVENT_1 10 COMBO_EVENT_1
COMBO_EVENT_2 11 COMBO_EVENT_2
COMBO_EVENT_3 12 COMBO_EVENT_3
EDGE_DETECTION_EVENT_0 13 EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1 14 EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT 15 GROUP_WATCHPOINT
WATCHPOINT_0 16 WATCHPOINT_0
WATCHPOINT_1 17 WATCHPOINT_1
WATCHPOINT_2 18 WATCHPOINT_2
WATCHPOINT_3 19 WATCHPOINT_3
GROUP_DMA_ACTIVITY 20 GROUP_DMA_ACTIVITY
DMA_S2MM_SEL0_START_TASK 21 DMA_S2MM_SEL0_START_TASK
DMA_S2MM_SEL1_START_TASK 22 DMA_S2MM_SEL1_START_TASK
DMA_MM2S_SEL0_START_TASK 23 DMA_MM2S_SEL0_START_TASK
DMA_MM2S_SEL1_START_TASK 24 DMA_MM2S_SEL1_START_TASK
DMA_S2MM_SEL0_FINISHED_BD 25 DMA_S2MM_SEL0_FINISHED_BD
DMA_S2MM_SEL1_FINISHED_BD 26 DMA_S2MM_SEL1_FINISHED_BD
DMA_MM2S_SEL0_FINISHED_BD 27 DMA_MM2S_SEL0_FINISHED_BD
DMA_MM2S_SEL1_FINISHED_BD 28 DMA_MM2S_SEL1_FINISHED_BD
DMA_S2MM_SEL0_FINISHED_TASK 29 DMA_S2MM_SEL0_FINISHED_TASK
DMA_S2MM_SEL1_FINISHED_TASK 30 DMA_S2MM_SEL1_FINISHED_TASK
DMA_MM2S_SEL0_FINISHED_TASK 31 DMA_MM2S_SEL0_FINISHED_TASK
DMA_MM2S_SEL1_FINISHED_TASK 32 DMA_MM2S_SEL1_FINISHED_TASK
DMA_S2MM_SEL0_STALLED_LOCK 33 DMA_S2MM_SEL0_STALLED_LOCK
DMA_S2MM_SEL1_STALLED_LOCK 34 DMA_S2MM_SEL1_STALLED_LOCK
DMA_MM2S_SEL0_STALLED_LOCK 35 DMA_MM2S_SEL0_STALLED_LOCK
DMA_MM2S_SEL1_STALLED_LOCK 36 DMA_MM2S_SEL1_STALLED_LOCK
DMA_S2MM_SEL0_STREAM_STARVATION 37 DMA_S2MM_SEL0_STREAM_STARVATION
DMA_S2MM_SEL1_STREAM_STARVATION 38 DMA_S2MM_SEL1_STREAM_STARVATION
DMA_MM2S_SEL0_STREAM_BACKPRESSURE 39 DMA_MM2S_SEL0_STREAM_BACKPRESSURE
DMA_MM2S_SEL1_STREAM_BACKPRESSURE 40 DMA_MM2S_SEL1_STREAM_BACKPRESSURE
DMA_S2MM_SEL0_MEMORY_BACKPRESSURE 41 DMA_S2MM_SEL0_MEMORY_BACKPRESSURE
DMA_S2MM_SEL1_MEMORY_BACKPRESSURE 42 DMA_S2MM_SEL1_MEMORY_BACKPRESSURE
DMA_MM2S_SEL0_MEMORY_STARVATION 43 DMA_MM2S_SEL0_MEMORY_STARVATION
DMA_MM2S_SEL1_MEMORY_STARVATION 44 DMA_MM2S_SEL1_MEMORY_STARVATION
GROUP_LOCK 45 GROUP_LOCK
LOCK_SEL0_ACQ_EQ 46 LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE 47 LOCK_SEL0_ACQ_GE
LOCK_SEL0_REL 48 LOCK_SEL0_REL
LOCK_SEL0_EQUAL_TO_VALUE 49 LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ 50 LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE 51 LOCK_SEL1_ACQ_GE
LOCK_SEL1_REL 52 LOCK_SEL1_REL
LOCK_SEL1_EQUAL_TO_VALUE 53 LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ 54 LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE 55 LOCK_SEL2_ACQ_GE
LOCK_SEL2_REL 56 LOCK_SEL2_REL
LOCK_SEL2_EQUAL_TO_VALUE 57 LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ 58 LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE 59 LOCK_SEL3_ACQ_GE
LOCK_SEL3_REL 60 LOCK_SEL3_REL
LOCK_SEL3_EQUAL_TO_VALUE 61 LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ 62 LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE 63 LOCK_SEL4_ACQ_GE
LOCK_SEL4_REL 64 LOCK_SEL4_REL
LOCK_SEL4_EQUAL_TO_VALUE 65 LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ 66 LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE 67 LOCK_SEL5_ACQ_GE
LOCK_SEL5_REL 68 LOCK_SEL5_REL
LOCK_SEL5_EQUAL_TO_VALUE 69 LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ 70 LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE 71 LOCK_SEL6_ACQ_GE
LOCK_SEL6_REL 72 LOCK_SEL6_REL
LOCK_SEL6_EQUAL_TO_VALUE 73 LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ 74 LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE 75 LOCK_SEL7_ACQ_GE
LOCK_SEL7_REL 76 LOCK_SEL7_REL
LOCK_SEL7_EQUAL_TO_VALUE 77 LOCK_SEL7_EQUAL_TO_VALUE
GROUP_STREAM_SWITCH 78 GROUP_STREAM_SWITCH
PORT_IDLE_0 79 PORT_IDLE_0
PORT_RUNNING_0 80 PORT_RUNNING_0
PORT_STALLED_0 81 PORT_STALLED_0
PORT_TLAST_0 82 PORT_TLAST_0
PORT_IDLE_1 83 PORT_IDLE_1
PORT_RUNNING_1 84 PORT_RUNNING_1
PORT_STALLED_1 85 PORT_STALLED_1
PORT_TLAST_1 86 PORT_TLAST_1
PORT_IDLE_2 87 PORT_IDLE_2
PORT_RUNNING_2 88 PORT_RUNNING_2
PORT_STALLED_2 89 PORT_STALLED_2
PORT_TLAST_2 90 PORT_TLAST_2
PORT_IDLE_3 91 PORT_IDLE_3
PORT_RUNNING_3 92 PORT_RUNNING_3
PORT_STALLED_3 93 PORT_STALLED_3
PORT_TLAST_3 94 PORT_TLAST_3
PORT_IDLE_4 95 PORT_IDLE_4
PORT_RUNNING_4 96 PORT_RUNNING_4
PORT_STALLED_4 97 PORT_STALLED_4
PORT_TLAST_4 98 PORT_TLAST_4
PORT_IDLE_5 99 PORT_IDLE_5
PORT_RUNNING_5 100 PORT_RUNNING_5
PORT_STALLED_5 101 PORT_STALLED_5
PORT_TLAST_5 102 PORT_TLAST_5
PORT_IDLE_6 103 PORT_IDLE_6
PORT_RUNNING_6 104 PORT_RUNNING_6
PORT_STALLED_6 105 PORT_STALLED_6
PORT_TLAST_6 106 PORT_TLAST_6
PORT_IDLE_7 107 PORT_IDLE_7
PORT_RUNNING_7 108 PORT_RUNNING_7
PORT_STALLED_7 109 PORT_STALLED_7
PORT_TLAST_7 110 PORT_TLAST_7
GROUP_MEMORY_CONFLICT 111 GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0 112 CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1 113 CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2 114 CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3 115 CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4 116 CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5 117 CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6 118 CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7 119 CONFLICT_DM_BANK_7
CONFLICT_DM_BANK_8 120 CONFLICT_DM_BANK_8
CONFLICT_DM_BANK_9 121 CONFLICT_DM_BANK_9
CONFLICT_DM_BANK_10 122 CONFLICT_DM_BANK_10
CONFLICT_DM_BANK_11 123 CONFLICT_DM_BANK_11
CONFLICT_DM_BANK_12 124 CONFLICT_DM_BANK_12
CONFLICT_DM_BANK_13 125 CONFLICT_DM_BANK_13
CONFLICT_DM_BANK_14 126 CONFLICT_DM_BANK_14
CONFLICT_DM_BANK_15 127 CONFLICT_DM_BANK_15
GROUP_ERRORS 128 GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED 129 DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT 130 DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT 131 DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT 132 DM_ECC_ERROR_2BIT
DMA_S2MM_ERROR 133 DMA_S2MM_ERROR
DMA_MM2S_ERROR 134 DMA_MM2S_ERROR
STREAM_SWITCH_PARITY_ERROR 135 STREAM_SWITCH_PARITY_ERROR
STREAM_PKT_ERROR 136 STREAM_PKT_ERROR
CONTROL_PKT_ERROR 137 CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR 138 AXI_MM_SLAVE_ERROR
LOCK_ERROR 139 LOCK_ERROR
DMA_TASK_TOKEN_STALL 140 DMA_TASK_TOKEN_STALL
GROUP_BROADCAST 141 GROUP_BROADCAST
BROADCAST_0 142 BROADCAST_0
BROADCAST_1 143 BROADCAST_1
BROADCAST_2 144 BROADCAST_2
BROADCAST_3 145 BROADCAST_3
BROADCAST_4 146 BROADCAST_4
BROADCAST_5 147 BROADCAST_5
BROADCAST_6 148 BROADCAST_6
BROADCAST_7 149 BROADCAST_7
BROADCAST_8 150 BROADCAST_8
BROADCAST_9 151 BROADCAST_9
BROADCAST_10 152 BROADCAST_10
BROADCAST_11 153 BROADCAST_11
BROADCAST_12 154 BROADCAST_12
BROADCAST_13 155 BROADCAST_13
BROADCAST_14 156 BROADCAST_14
BROADCAST_15 157 BROADCAST_15
GROUP_USER_EVENT 158 GROUP_USER_EVENT
USER_EVENT_0 159 USER_EVENT_0
USER_EVENT_1 160 USER_EVENT_1

MemTileEventAIE2P

Memory tile event enumeration for AIE2P

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT0_EVENT 5 PERF_CNT0_EVENT
PERF_CNT1_EVENT 6 PERF_CNT1_EVENT
PERF_CNT2_EVENT 7 PERF_CNT2_EVENT
PERF_CNT3_EVENT 8 PERF_CNT3_EVENT
COMBO_EVENT_0 9 COMBO_EVENT_0
COMBO_EVENT_1 10 COMBO_EVENT_1
COMBO_EVENT_2 11 COMBO_EVENT_2
COMBO_EVENT_3 12 COMBO_EVENT_3
EDGE_DETECTION_EVENT_0 13 EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1 14 EDGE_DETECTION_EVENT_1
GROUP_WATCHPOINT 15 GROUP_WATCHPOINT
WATCHPOINT_0 16 WATCHPOINT_0
WATCHPOINT_1 17 WATCHPOINT_1
WATCHPOINT_2 18 WATCHPOINT_2
WATCHPOINT_3 19 WATCHPOINT_3
GROUP_DMA_ACTIVITY 20 GROUP_DMA_ACTIVITY
DMA_S2MM_SEL0_START_TASK 21 DMA_S2MM_SEL0_START_TASK
DMA_S2MM_SEL1_START_TASK 22 DMA_S2MM_SEL1_START_TASK
DMA_MM2S_SEL0_START_TASK 23 DMA_MM2S_SEL0_START_TASK
DMA_MM2S_SEL1_START_TASK 24 DMA_MM2S_SEL1_START_TASK
DMA_S2MM_SEL0_FINISHED_BD 25 DMA_S2MM_SEL0_FINISHED_BD
DMA_S2MM_SEL1_FINISHED_BD 26 DMA_S2MM_SEL1_FINISHED_BD
DMA_MM2S_SEL0_FINISHED_BD 27 DMA_MM2S_SEL0_FINISHED_BD
DMA_MM2S_SEL1_FINISHED_BD 28 DMA_MM2S_SEL1_FINISHED_BD
DMA_S2MM_SEL0_FINISHED_TASK 29 DMA_S2MM_SEL0_FINISHED_TASK
DMA_S2MM_SEL1_FINISHED_TASK 30 DMA_S2MM_SEL1_FINISHED_TASK
DMA_MM2S_SEL0_FINISHED_TASK 31 DMA_MM2S_SEL0_FINISHED_TASK
DMA_MM2S_SEL1_FINISHED_TASK 32 DMA_MM2S_SEL1_FINISHED_TASK
DMA_S2MM_SEL0_STALLED_LOCK 33 DMA_S2MM_SEL0_STALLED_LOCK
DMA_S2MM_SEL1_STALLED_LOCK 34 DMA_S2MM_SEL1_STALLED_LOCK
DMA_MM2S_SEL0_STALLED_LOCK 35 DMA_MM2S_SEL0_STALLED_LOCK
DMA_MM2S_SEL1_STALLED_LOCK 36 DMA_MM2S_SEL1_STALLED_LOCK
DMA_S2MM_SEL0_STREAM_STARVATION 37 DMA_S2MM_SEL0_STREAM_STARVATION
DMA_S2MM_SEL1_STREAM_STARVATION 38 DMA_S2MM_SEL1_STREAM_STARVATION
DMA_MM2S_SEL0_STREAM_BACKPRESSURE 39 DMA_MM2S_SEL0_STREAM_BACKPRESSURE
DMA_MM2S_SEL1_STREAM_BACKPRESSURE 40 DMA_MM2S_SEL1_STREAM_BACKPRESSURE
DMA_S2MM_SEL0_MEMORY_BACKPRESSURE 41 DMA_S2MM_SEL0_MEMORY_BACKPRESSURE
DMA_S2MM_SEL1_MEMORY_BACKPRESSURE 42 DMA_S2MM_SEL1_MEMORY_BACKPRESSURE
DMA_MM2S_SEL0_MEMORY_STARVATION 43 DMA_MM2S_SEL0_MEMORY_STARVATION
DMA_MM2S_SEL1_MEMORY_STARVATION 44 DMA_MM2S_SEL1_MEMORY_STARVATION
GROUP_LOCK 45 GROUP_LOCK
LOCK_SEL0_ACQ_EQ 46 LOCK_SEL0_ACQ_EQ
LOCK_SEL0_ACQ_GE 47 LOCK_SEL0_ACQ_GE
LOCK_SEL0_REL 48 LOCK_SEL0_REL
LOCK_SEL0_EQUAL_TO_VALUE 49 LOCK_SEL0_EQUAL_TO_VALUE
LOCK_SEL1_ACQ_EQ 50 LOCK_SEL1_ACQ_EQ
LOCK_SEL1_ACQ_GE 51 LOCK_SEL1_ACQ_GE
LOCK_SEL1_REL 52 LOCK_SEL1_REL
LOCK_SEL1_EQUAL_TO_VALUE 53 LOCK_SEL1_EQUAL_TO_VALUE
LOCK_SEL2_ACQ_EQ 54 LOCK_SEL2_ACQ_EQ
LOCK_SEL2_ACQ_GE 55 LOCK_SEL2_ACQ_GE
LOCK_SEL2_REL 56 LOCK_SEL2_REL
LOCK_SEL2_EQUAL_TO_VALUE 57 LOCK_SEL2_EQUAL_TO_VALUE
LOCK_SEL3_ACQ_EQ 58 LOCK_SEL3_ACQ_EQ
LOCK_SEL3_ACQ_GE 59 LOCK_SEL3_ACQ_GE
LOCK_SEL3_REL 60 LOCK_SEL3_REL
LOCK_SEL3_EQUAL_TO_VALUE 61 LOCK_SEL3_EQUAL_TO_VALUE
LOCK_SEL4_ACQ_EQ 62 LOCK_SEL4_ACQ_EQ
LOCK_SEL4_ACQ_GE 63 LOCK_SEL4_ACQ_GE
LOCK_SEL4_REL 64 LOCK_SEL4_REL
LOCK_SEL4_EQUAL_TO_VALUE 65 LOCK_SEL4_EQUAL_TO_VALUE
LOCK_SEL5_ACQ_EQ 66 LOCK_SEL5_ACQ_EQ
LOCK_SEL5_ACQ_GE 67 LOCK_SEL5_ACQ_GE
LOCK_SEL5_REL 68 LOCK_SEL5_REL
LOCK_SEL5_EQUAL_TO_VALUE 69 LOCK_SEL5_EQUAL_TO_VALUE
LOCK_SEL6_ACQ_EQ 70 LOCK_SEL6_ACQ_EQ
LOCK_SEL6_ACQ_GE 71 LOCK_SEL6_ACQ_GE
LOCK_SEL6_REL 72 LOCK_SEL6_REL
LOCK_SEL6_EQUAL_TO_VALUE 73 LOCK_SEL6_EQUAL_TO_VALUE
LOCK_SEL7_ACQ_EQ 74 LOCK_SEL7_ACQ_EQ
LOCK_SEL7_ACQ_GE 75 LOCK_SEL7_ACQ_GE
LOCK_SEL7_REL 76 LOCK_SEL7_REL
LOCK_SEL7_EQUAL_TO_VALUE 77 LOCK_SEL7_EQUAL_TO_VALUE
GROUP_STREAM_SWITCH 78 GROUP_STREAM_SWITCH
PORT_IDLE_0 79 PORT_IDLE_0
PORT_RUNNING_0 80 PORT_RUNNING_0
PORT_STALLED_0 81 PORT_STALLED_0
PORT_TLAST_0 82 PORT_TLAST_0
PORT_IDLE_1 83 PORT_IDLE_1
PORT_RUNNING_1 84 PORT_RUNNING_1
PORT_STALLED_1 85 PORT_STALLED_1
PORT_TLAST_1 86 PORT_TLAST_1
PORT_IDLE_2 87 PORT_IDLE_2
PORT_RUNNING_2 88 PORT_RUNNING_2
PORT_STALLED_2 89 PORT_STALLED_2
PORT_TLAST_2 90 PORT_TLAST_2
PORT_IDLE_3 91 PORT_IDLE_3
PORT_RUNNING_3 92 PORT_RUNNING_3
PORT_STALLED_3 93 PORT_STALLED_3
PORT_TLAST_3 94 PORT_TLAST_3
PORT_IDLE_4 95 PORT_IDLE_4
PORT_RUNNING_4 96 PORT_RUNNING_4
PORT_STALLED_4 97 PORT_STALLED_4
PORT_TLAST_4 98 PORT_TLAST_4
PORT_IDLE_5 99 PORT_IDLE_5
PORT_RUNNING_5 100 PORT_RUNNING_5
PORT_STALLED_5 101 PORT_STALLED_5
PORT_TLAST_5 102 PORT_TLAST_5
PORT_IDLE_6 103 PORT_IDLE_6
PORT_RUNNING_6 104 PORT_RUNNING_6
PORT_STALLED_6 105 PORT_STALLED_6
PORT_TLAST_6 106 PORT_TLAST_6
PORT_IDLE_7 107 PORT_IDLE_7
PORT_RUNNING_7 108 PORT_RUNNING_7
PORT_STALLED_7 109 PORT_STALLED_7
PORT_TLAST_7 110 PORT_TLAST_7
GROUP_MEMORY_CONFLICT 111 GROUP_MEMORY_CONFLICT
CONFLICT_DM_BANK_0 112 CONFLICT_DM_BANK_0
CONFLICT_DM_BANK_1 113 CONFLICT_DM_BANK_1
CONFLICT_DM_BANK_2 114 CONFLICT_DM_BANK_2
CONFLICT_DM_BANK_3 115 CONFLICT_DM_BANK_3
CONFLICT_DM_BANK_4 116 CONFLICT_DM_BANK_4
CONFLICT_DM_BANK_5 117 CONFLICT_DM_BANK_5
CONFLICT_DM_BANK_6 118 CONFLICT_DM_BANK_6
CONFLICT_DM_BANK_7 119 CONFLICT_DM_BANK_7
CONFLICT_DM_BANK_8 120 CONFLICT_DM_BANK_8
CONFLICT_DM_BANK_9 121 CONFLICT_DM_BANK_9
CONFLICT_DM_BANK_10 122 CONFLICT_DM_BANK_10
CONFLICT_DM_BANK_11 123 CONFLICT_DM_BANK_11
CONFLICT_DM_BANK_12 124 CONFLICT_DM_BANK_12
CONFLICT_DM_BANK_13 125 CONFLICT_DM_BANK_13
CONFLICT_DM_BANK_14 126 CONFLICT_DM_BANK_14
CONFLICT_DM_BANK_15 127 CONFLICT_DM_BANK_15
GROUP_ERRORS 128 GROUP_ERRORS
DM_ECC_ERROR_SCRUB_CORRECTED 129 DM_ECC_ERROR_SCRUB_CORRECTED
DM_ECC_ERROR_SCRUB_2BIT 130 DM_ECC_ERROR_SCRUB_2BIT
DM_ECC_ERROR_1BIT 131 DM_ECC_ERROR_1BIT
DM_ECC_ERROR_2BIT 132 DM_ECC_ERROR_2BIT
DMA_S2MM_ERROR 133 DMA_S2MM_ERROR
DMA_MM2S_ERROR 134 DMA_MM2S_ERROR
STREAM_SWITCH_PARITY_ERROR 135 STREAM_SWITCH_PARITY_ERROR
STREAM_PKT_ERROR 136 STREAM_PKT_ERROR
CONTROL_PKT_ERROR 137 CONTROL_PKT_ERROR
AXI_MM_SLAVE_ERROR 138 AXI_MM_SLAVE_ERROR
LOCK_ERROR 139 LOCK_ERROR
DMA_TASK_TOKEN_STALL 140 DMA_TASK_TOKEN_STALL
GROUP_BROADCAST 141 GROUP_BROADCAST
BROADCAST_0 142 BROADCAST_0
BROADCAST_1 143 BROADCAST_1
BROADCAST_2 144 BROADCAST_2
BROADCAST_3 145 BROADCAST_3
BROADCAST_4 146 BROADCAST_4
BROADCAST_5 147 BROADCAST_5
BROADCAST_6 148 BROADCAST_6
BROADCAST_7 149 BROADCAST_7
BROADCAST_8 150 BROADCAST_8
BROADCAST_9 151 BROADCAST_9
BROADCAST_10 152 BROADCAST_10
BROADCAST_11 153 BROADCAST_11
BROADCAST_12 154 BROADCAST_12
BROADCAST_13 155 BROADCAST_13
BROADCAST_14 156 BROADCAST_14
BROADCAST_15 157 BROADCAST_15
GROUP_USER_EVENT 158 GROUP_USER_EVENT
USER_EVENT_0 159 USER_EVENT_0
USER_EVENT_1 160 USER_EVENT_1

ObjectFifoLinkMode

How an objectFifo link's participants share its objects

Cases:

Symbol Value String
Space 0 space
Time 1 time

ObjectFifoPort

Ports of an object FIFO

Cases:

Symbol Value String
Produce 0 Produce
Consume 1 Consume

ObjectFifoRole

What an objectFifo endpoint does to its pool's buffers

Cases:

Symbol Value String
Fill 0 fills
Drain 1 drains

ObjectFifoTransportMode

The hardware path an objectFifo's objects travel over

Cases:

Symbol Value String
Auto 0 auto
SharedMem 1 shared_mem
DMA 2 dma

ShimTileEventAIE

Shim tile event enumeration for AIE

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT_0 5 PERF_CNT_0
PERF_CNT_1 6 PERF_CNT_1
COMBO_EVENT_0 7 COMBO_EVENT_0
COMBO_EVENT_1 8 COMBO_EVENT_1
COMBO_EVENT_2 9 COMBO_EVENT_2
COMBO_EVENT_3 10 COMBO_EVENT_3
GROUP_DMA_ACTIVITY 11 GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_BD 12 DMA_S2MM_0_START_BD
DMA_S2MM_1_START_BD 13 DMA_S2MM_1_START_BD
DMA_MM2S_0_START_BD 14 DMA_MM2S_0_START_BD
DMA_MM2S_1_START_BD 15 DMA_MM2S_1_START_BD
DMA_S2MM_0_FINISHED_BD 16 DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD 17 DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD 18 DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD 19 DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_GO_TO_IDLE 20 DMA_S2MM_0_GO_TO_IDLE
DMA_S2MM_1_GO_TO_IDLE 21 DMA_S2MM_1_GO_TO_IDLE
DMA_MM2S_0_GO_TO_IDLE 22 DMA_MM2S_0_GO_TO_IDLE
DMA_MM2S_1_GO_TO_IDLE 23 DMA_MM2S_1_GO_TO_IDLE
DMA_S2MM_0_STALLED_LOCK_ACQUIRE 24 DMA_S2MM_0_STALLED_LOCK_ACQUIRE
DMA_S2MM_1_STALLED_LOCK_ACQUIRE 25 DMA_S2MM_1_STALLED_LOCK_ACQUIRE
DMA_MM2S_0_STALLED_LOCK_ACQUIRE 26 DMA_MM2S_0_STALLED_LOCK_ACQUIRE
DMA_MM2S_1_STALLED_LOCK_ACQUIRE 27 DMA_MM2S_1_STALLED_LOCK_ACQUIRE
GROUP_LOCK 28 GROUP_LOCK
LOCK_0_ACQUIRED 29 LOCK_0_ACQUIRED
LOCK_0_RELEASED 30 LOCK_0_RELEASED
LOCK_1_ACQUIRED 31 LOCK_1_ACQUIRED
LOCK_1_RELEASED 32 LOCK_1_RELEASED
LOCK_2_ACQUIRED 33 LOCK_2_ACQUIRED
LOCK_2_RELEASED 34 LOCK_2_RELEASED
LOCK_3_ACQUIRED 35 LOCK_3_ACQUIRED
LOCK_3_RELEASED 36 LOCK_3_RELEASED
LOCK_4_ACQUIRED 37 LOCK_4_ACQUIRED
LOCK_4_RELEASED 38 LOCK_4_RELEASED
LOCK_5_ACQUIRED 39 LOCK_5_ACQUIRED
LOCK_5_RELEASED 40 LOCK_5_RELEASED
LOCK_6_ACQUIRED 41 LOCK_6_ACQUIRED
LOCK_6_RELEASED 42 LOCK_6_RELEASED
LOCK_7_ACQUIRED 43 LOCK_7_ACQUIRED
LOCK_7_RELEASED 44 LOCK_7_RELEASED
LOCK_8_ACQUIRED 45 LOCK_8_ACQUIRED
LOCK_8_RELEASED 46 LOCK_8_RELEASED
LOCK_9_ACQUIRED 47 LOCK_9_ACQUIRED
LOCK_9_RELEASED 48 LOCK_9_RELEASED
LOCK_10_ACQUIRED 49 LOCK_10_ACQUIRED
LOCK_10_RELEASED 50 LOCK_10_RELEASED
LOCK_11_ACQUIRED 51 LOCK_11_ACQUIRED
LOCK_11_RELEASED 52 LOCK_11_RELEASED
LOCK_12_ACQUIRED 53 LOCK_12_ACQUIRED
LOCK_12_RELEASED 54 LOCK_12_RELEASED
LOCK_13_ACQUIRED 55 LOCK_13_ACQUIRED
LOCK_13_RELEASED 56 LOCK_13_RELEASED
LOCK_14_ACQUIRED 57 LOCK_14_ACQUIRED
LOCK_14_RELEASED 58 LOCK_14_RELEASED
LOCK_15_ACQUIRED 59 LOCK_15_ACQUIRED
LOCK_15_RELEASED 60 LOCK_15_RELEASED
GROUP_ERRORS 61 GROUP_ERRORS
AXI_MM_SLAVE_TILE_ERROR 62 AXI_MM_SLAVE_TILE_ERROR
CONTROL_PKT_ERROR 63 CONTROL_PKT_ERROR
AXI_MM_DECODE_NSU_ERROR 64 AXI_MM_DECODE_NSU_ERROR
AXI_MM_SLAVE_NSU_ERROR 65 AXI_MM_SLAVE_NSU_ERROR
AXI_MM_UNSUPPORTED_TRAFFIC 66 AXI_MM_UNSUPPORTED_TRAFFIC
AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE 67 AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE
AXI_MM_BYTE_STROBE_ERROR 68 AXI_MM_BYTE_STROBE_ERROR
DMA_S2MM_0_ERROR 69 DMA_S2MM_0_ERROR
DMA_S2MM_1_ERROR 70 DMA_S2MM_1_ERROR
DMA_MM2S_0_ERROR 71 DMA_MM2S_0_ERROR
DMA_MM2S_1_ERROR 72 DMA_MM2S_1_ERROR
GROUP_STREAM_SWITCH 73 GROUP_STREAM_SWITCH
PORT_IDLE_0 74 PORT_IDLE_0
PORT_RUNNING_0 75 PORT_RUNNING_0
PORT_STALLED_0 76 PORT_STALLED_0
PORT_TLAST_0 77 PORT_TLAST_0
PORT_IDLE_1 78 PORT_IDLE_1
PORT_RUNNING_1 79 PORT_RUNNING_1
PORT_STALLED_1 80 PORT_STALLED_1
PORT_TLAST_1 81 PORT_TLAST_1
PORT_IDLE_2 82 PORT_IDLE_2
PORT_RUNNING_2 83 PORT_RUNNING_2
PORT_STALLED_2 84 PORT_STALLED_2
PORT_TLAST_2 85 PORT_TLAST_2
PORT_IDLE_3 86 PORT_IDLE_3
PORT_RUNNING_3 87 PORT_RUNNING_3
PORT_STALLED_3 88 PORT_STALLED_3
PORT_TLAST_3 89 PORT_TLAST_3
PORT_IDLE_4 90 PORT_IDLE_4
PORT_RUNNING_4 91 PORT_RUNNING_4
PORT_STALLED_4 92 PORT_STALLED_4
PORT_TLAST_4 93 PORT_TLAST_4
PORT_IDLE_5 94 PORT_IDLE_5
PORT_RUNNING_5 95 PORT_RUNNING_5
PORT_STALLED_5 96 PORT_STALLED_5
PORT_TLAST_5 97 PORT_TLAST_5
PORT_IDLE_6 98 PORT_IDLE_6
PORT_RUNNING_6 99 PORT_RUNNING_6
PORT_STALLED_6 100 PORT_STALLED_6
PORT_TLAST_6 101 PORT_TLAST_6
PORT_IDLE_7 102 PORT_IDLE_7
PORT_RUNNING_7 103 PORT_RUNNING_7
PORT_STALLED_7 104 PORT_STALLED_7
PORT_TLAST_7 105 PORT_TLAST_7
GROUP_BROADCAST_A 106 GROUP_BROADCAST_A
BROADCAST_A_0 107 BROADCAST_A_0
BROADCAST_A_1 108 BROADCAST_A_1
BROADCAST_A_2 109 BROADCAST_A_2
BROADCAST_A_3 110 BROADCAST_A_3
BROADCAST_A_4 111 BROADCAST_A_4
BROADCAST_A_5 112 BROADCAST_A_5
BROADCAST_A_6 113 BROADCAST_A_6
BROADCAST_A_7 114 BROADCAST_A_7
BROADCAST_A_8 115 BROADCAST_A_8
BROADCAST_A_9 116 BROADCAST_A_9
BROADCAST_A_10 117 BROADCAST_A_10
BROADCAST_A_11 118 BROADCAST_A_11
BROADCAST_A_12 119 BROADCAST_A_12
BROADCAST_A_13 120 BROADCAST_A_13
BROADCAST_A_14 121 BROADCAST_A_14
BROADCAST_A_15 122 BROADCAST_A_15
GROUP_USER_EVENT 123 GROUP_USER_EVENT
USER_EVENT_0 124 USER_EVENT_0
USER_EVENT_1 125 USER_EVENT_1
USER_EVENT_2 126 USER_EVENT_2
USER_EVENT_3 127 USER_EVENT_3

ShimTileEventAIE2

Shim tile event enumeration for AIE2

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT_0 5 PERF_CNT_0
PERF_CNT_1 6 PERF_CNT_1
COMBO_EVENT_0 7 COMBO_EVENT_0
COMBO_EVENT_1 8 COMBO_EVENT_1
COMBO_EVENT_2 9 COMBO_EVENT_2
COMBO_EVENT_3 10 COMBO_EVENT_3
EDGE_DETECTION_EVENT_0 11 EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1 12 EDGE_DETECTION_EVENT_1
GROUP_DMA_ACTIVITY 13 GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK 14 DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK 15 DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK 16 DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK 17 DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD 18 DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD 19 DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD 20 DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD 21 DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK 22 DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK 23 DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK 24 DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK 25 DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK 26 DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK 27 DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK 28 DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK 29 DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION 30 DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION 31 DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE 32 DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE 33 DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE 34 DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE 35 DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION 36 DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION 37 DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK 38 GROUP_LOCK
LOCK_0_ACQ_EQ 39 LOCK_0_ACQ_EQ
LOCK_0_ACQ_GE 40 LOCK_0_ACQ_GE
LOCK_0_REL 41 LOCK_0_REL
LOCK_0_EQUAL_TO_VALUE 42 LOCK_0_EQUAL_TO_VALUE
LOCK_1_ACQ_EQ 43 LOCK_1_ACQ_EQ
LOCK_1_ACQ_GE 44 LOCK_1_ACQ_GE
LOCK_1_REL 45 LOCK_1_REL
LOCK_1_EQUAL_TO_VALUE 46 LOCK_1_EQUAL_TO_VALUE
LOCK_2_ACQ_EQ 47 LOCK_2_ACQ_EQ
LOCK_2_ACQ_GE 48 LOCK_2_ACQ_GE
LOCK_2_REL 49 LOCK_2_REL
LOCK_2_EQUAL_TO_VALUE 50 LOCK_2_EQUAL_TO_VALUE
LOCK_3_ACQ_EQ 51 LOCK_3_ACQ_EQ
LOCK_3_ACQ_GE 52 LOCK_3_ACQ_GE
LOCK_3_REL 53 LOCK_3_REL
LOCK_3_EQUAL_TO_VALUE 54 LOCK_3_EQUAL_TO_VALUE
LOCK_4_ACQ_EQ 55 LOCK_4_ACQ_EQ
LOCK_4_ACQ_GE 56 LOCK_4_ACQ_GE
LOCK_4_REL 57 LOCK_4_REL
LOCK_4_EQUAL_TO_VALUE 58 LOCK_4_EQUAL_TO_VALUE
LOCK_5_ACQ_EQ 59 LOCK_5_ACQ_EQ
LOCK_5_ACQ_GE 60 LOCK_5_ACQ_GE
LOCK_5_REL 61 LOCK_5_REL
LOCK_5_EQUAL_TO_VALUE 62 LOCK_5_EQUAL_TO_VALUE
GROUP_ERRORS 63 GROUP_ERRORS
AXI_MM_SLAVE_ERROR 64 AXI_MM_SLAVE_ERROR
CONTROL_PKT_ERROR 65 CONTROL_PKT_ERROR
STREAM_SWITCH_PARITY_ERROR 66 STREAM_SWITCH_PARITY_ERROR
AXI_MM_DECODE_NSU_ERROR 67 AXI_MM_DECODE_NSU_ERROR
AXI_MM_SLAVE_NSU_ERROR 68 AXI_MM_SLAVE_NSU_ERROR
AXI_MM_UNSUPPORTED_TRAFFIC 69 AXI_MM_UNSUPPORTED_TRAFFIC
AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE 70 AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE
AXI_MM_BYTE_STROBE_ERROR 71 AXI_MM_BYTE_STROBE_ERROR
DMA_S2MM_ERROR 72 DMA_S2MM_ERROR
DMA_MM2S_ERROR 73 DMA_MM2S_ERROR
LOCK_ERROR 74 LOCK_ERROR
DMA_TASK_TOKEN_STALL 75 DMA_TASK_TOKEN_STALL
GROUP_STREAM_SWITCH 76 GROUP_STREAM_SWITCH
PORT_IDLE_0 77 PORT_IDLE_0
PORT_RUNNING_0 78 PORT_RUNNING_0
PORT_STALLED_0 79 PORT_STALLED_0
PORT_TLAST_0 80 PORT_TLAST_0
PORT_IDLE_1 81 PORT_IDLE_1
PORT_RUNNING_1 82 PORT_RUNNING_1
PORT_STALLED_1 83 PORT_STALLED_1
PORT_TLAST_1 84 PORT_TLAST_1
PORT_IDLE_2 85 PORT_IDLE_2
PORT_RUNNING_2 86 PORT_RUNNING_2
PORT_STALLED_2 87 PORT_STALLED_2
PORT_TLAST_2 88 PORT_TLAST_2
PORT_IDLE_3 89 PORT_IDLE_3
PORT_RUNNING_3 90 PORT_RUNNING_3
PORT_STALLED_3 91 PORT_STALLED_3
PORT_TLAST_3 92 PORT_TLAST_3
PORT_IDLE_4 93 PORT_IDLE_4
PORT_RUNNING_4 94 PORT_RUNNING_4
PORT_STALLED_4 95 PORT_STALLED_4
PORT_TLAST_4 96 PORT_TLAST_4
PORT_IDLE_5 97 PORT_IDLE_5
PORT_RUNNING_5 98 PORT_RUNNING_5
PORT_STALLED_5 99 PORT_STALLED_5
PORT_TLAST_5 100 PORT_TLAST_5
PORT_IDLE_6 101 PORT_IDLE_6
PORT_RUNNING_6 102 PORT_RUNNING_6
PORT_STALLED_6 103 PORT_STALLED_6
PORT_TLAST_6 104 PORT_TLAST_6
PORT_IDLE_7 105 PORT_IDLE_7
PORT_RUNNING_7 106 PORT_RUNNING_7
PORT_STALLED_7 107 PORT_STALLED_7
PORT_TLAST_7 108 PORT_TLAST_7
GROUP_BROADCAST_A 109 GROUP_BROADCAST_A
BROADCAST_A_0 110 BROADCAST_A_0
BROADCAST_A_1 111 BROADCAST_A_1
BROADCAST_A_2 112 BROADCAST_A_2
BROADCAST_A_3 113 BROADCAST_A_3
BROADCAST_A_4 114 BROADCAST_A_4
BROADCAST_A_5 115 BROADCAST_A_5
BROADCAST_A_6 116 BROADCAST_A_6
BROADCAST_A_7 117 BROADCAST_A_7
BROADCAST_A_8 118 BROADCAST_A_8
BROADCAST_A_9 119 BROADCAST_A_9
BROADCAST_A_10 120 BROADCAST_A_10
BROADCAST_A_11 121 BROADCAST_A_11
BROADCAST_A_12 122 BROADCAST_A_12
BROADCAST_A_13 123 BROADCAST_A_13
BROADCAST_A_14 124 BROADCAST_A_14
BROADCAST_A_15 125 BROADCAST_A_15
USER_EVENT_0 126 USER_EVENT_0
USER_EVENT_1 127 USER_EVENT_1

ShimTileEventAIE2P

Shim tile event enumeration for AIE2P

Cases:

Symbol Value String
NONE 0 NONE
TRUE 1 TRUE
GROUP_0 2 GROUP_0
TIMER_SYNC 3 TIMER_SYNC
TIMER_VALUE_REACHED 4 TIMER_VALUE_REACHED
PERF_CNT_0 5 PERF_CNT_0
PERF_CNT_1 6 PERF_CNT_1
COMBO_EVENT_0 7 COMBO_EVENT_0
COMBO_EVENT_1 8 COMBO_EVENT_1
COMBO_EVENT_2 9 COMBO_EVENT_2
COMBO_EVENT_3 10 COMBO_EVENT_3
EDGE_DETECTION_EVENT_0 11 EDGE_DETECTION_EVENT_0
EDGE_DETECTION_EVENT_1 12 EDGE_DETECTION_EVENT_1
GROUP_DMA_ACTIVITY 13 GROUP_DMA_ACTIVITY
DMA_S2MM_0_START_TASK 14 DMA_S2MM_0_START_TASK
DMA_S2MM_1_START_TASK 15 DMA_S2MM_1_START_TASK
DMA_MM2S_0_START_TASK 16 DMA_MM2S_0_START_TASK
DMA_MM2S_1_START_TASK 17 DMA_MM2S_1_START_TASK
DMA_S2MM_0_FINISHED_BD 18 DMA_S2MM_0_FINISHED_BD
DMA_S2MM_1_FINISHED_BD 19 DMA_S2MM_1_FINISHED_BD
DMA_MM2S_0_FINISHED_BD 20 DMA_MM2S_0_FINISHED_BD
DMA_MM2S_1_FINISHED_BD 21 DMA_MM2S_1_FINISHED_BD
DMA_S2MM_0_FINISHED_TASK 22 DMA_S2MM_0_FINISHED_TASK
DMA_S2MM_1_FINISHED_TASK 23 DMA_S2MM_1_FINISHED_TASK
DMA_MM2S_0_FINISHED_TASK 24 DMA_MM2S_0_FINISHED_TASK
DMA_MM2S_1_FINISHED_TASK 25 DMA_MM2S_1_FINISHED_TASK
DMA_S2MM_0_STALLED_LOCK 26 DMA_S2MM_0_STALLED_LOCK
DMA_S2MM_1_STALLED_LOCK 27 DMA_S2MM_1_STALLED_LOCK
DMA_MM2S_0_STALLED_LOCK 28 DMA_MM2S_0_STALLED_LOCK
DMA_MM2S_1_STALLED_LOCK 29 DMA_MM2S_1_STALLED_LOCK
DMA_S2MM_0_STREAM_STARVATION 30 DMA_S2MM_0_STREAM_STARVATION
DMA_S2MM_1_STREAM_STARVATION 31 DMA_S2MM_1_STREAM_STARVATION
DMA_MM2S_0_STREAM_BACKPRESSURE 32 DMA_MM2S_0_STREAM_BACKPRESSURE
DMA_MM2S_1_STREAM_BACKPRESSURE 33 DMA_MM2S_1_STREAM_BACKPRESSURE
DMA_S2MM_0_MEMORY_BACKPRESSURE 34 DMA_S2MM_0_MEMORY_BACKPRESSURE
DMA_S2MM_1_MEMORY_BACKPRESSURE 35 DMA_S2MM_1_MEMORY_BACKPRESSURE
DMA_MM2S_0_MEMORY_STARVATION 36 DMA_MM2S_0_MEMORY_STARVATION
DMA_MM2S_1_MEMORY_STARVATION 37 DMA_MM2S_1_MEMORY_STARVATION
GROUP_LOCK 38 GROUP_LOCK
LOCK_0_ACQ_EQ 39 LOCK_0_ACQ_EQ
LOCK_0_ACQ_GE 40 LOCK_0_ACQ_GE
LOCK_0_REL 41 LOCK_0_REL
LOCK_0_EQUAL_TO_VALUE 42 LOCK_0_EQUAL_TO_VALUE
LOCK_1_ACQ_EQ 43 LOCK_1_ACQ_EQ
LOCK_1_ACQ_GE 44 LOCK_1_ACQ_GE
LOCK_1_REL 45 LOCK_1_REL
LOCK_1_EQUAL_TO_VALUE 46 LOCK_1_EQUAL_TO_VALUE
LOCK_2_ACQ_EQ 47 LOCK_2_ACQ_EQ
LOCK_2_ACQ_GE 48 LOCK_2_ACQ_GE
LOCK_2_REL 49 LOCK_2_REL
LOCK_2_EQUAL_TO_VALUE 50 LOCK_2_EQUAL_TO_VALUE
LOCK_3_ACQ_EQ 51 LOCK_3_ACQ_EQ
LOCK_3_ACQ_GE 52 LOCK_3_ACQ_GE
LOCK_3_REL 53 LOCK_3_REL
LOCK_3_EQUAL_TO_VALUE 54 LOCK_3_EQUAL_TO_VALUE
LOCK_4_ACQ_EQ 55 LOCK_4_ACQ_EQ
LOCK_4_ACQ_GE 56 LOCK_4_ACQ_GE
LOCK_4_REL 57 LOCK_4_REL
LOCK_4_EQUAL_TO_VALUE 58 LOCK_4_EQUAL_TO_VALUE
LOCK_5_ACQ_EQ 59 LOCK_5_ACQ_EQ
LOCK_5_ACQ_GE 60 LOCK_5_ACQ_GE
LOCK_5_REL 61 LOCK_5_REL
LOCK_5_EQUAL_TO_VALUE 62 LOCK_5_EQUAL_TO_VALUE
GROUP_ERRORS 63 GROUP_ERRORS
AXI_MM_SLAVE_ERROR 64 AXI_MM_SLAVE_ERROR
CONTROL_PKT_ERROR 65 CONTROL_PKT_ERROR
STREAM_SWITCH_PARITY_ERROR 66 STREAM_SWITCH_PARITY_ERROR
AXI_MM_DECODE_NSU_ERROR 67 AXI_MM_DECODE_NSU_ERROR
AXI_MM_SLAVE_NSU_ERROR 68 AXI_MM_SLAVE_NSU_ERROR
AXI_MM_UNSUPPORTED_TRAFFIC 69 AXI_MM_UNSUPPORTED_TRAFFIC
AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE 70 AXI_MM_UNSECURE_ACCESS_IN_SECURE_MODE
AXI_MM_BYTE_STROBE_ERROR 71 AXI_MM_BYTE_STROBE_ERROR
DMA_S2MM_ERROR 72 DMA_S2MM_ERROR
DMA_MM2S_ERROR 73 DMA_MM2S_ERROR
LOCK_ERROR 74 LOCK_ERROR
DMA_TASK_TOKEN_STALL 75 DMA_TASK_TOKEN_STALL
GROUP_STREAM_SWITCH 76 GROUP_STREAM_SWITCH
PORT_IDLE_0 77 PORT_IDLE_0
PORT_RUNNING_0 78 PORT_RUNNING_0
PORT_STALLED_0 79 PORT_STALLED_0
PORT_TLAST_0 80 PORT_TLAST_0
PORT_IDLE_1 81 PORT_IDLE_1
PORT_RUNNING_1 82 PORT_RUNNING_1
PORT_STALLED_1 83 PORT_STALLED_1
PORT_TLAST_1 84 PORT_TLAST_1
PORT_IDLE_2 85 PORT_IDLE_2
PORT_RUNNING_2 86 PORT_RUNNING_2
PORT_STALLED_2 87 PORT_STALLED_2
PORT_TLAST_2 88 PORT_TLAST_2
PORT_IDLE_3 89 PORT_IDLE_3
PORT_RUNNING_3 90 PORT_RUNNING_3
PORT_STALLED_3 91 PORT_STALLED_3
PORT_TLAST_3 92 PORT_TLAST_3
PORT_IDLE_4 93 PORT_IDLE_4
PORT_RUNNING_4 94 PORT_RUNNING_4
PORT_STALLED_4 95 PORT_STALLED_4
PORT_TLAST_4 96 PORT_TLAST_4
PORT_IDLE_5 97 PORT_IDLE_5
PORT_RUNNING_5 98 PORT_RUNNING_5
PORT_STALLED_5 99 PORT_STALLED_5
PORT_TLAST_5 100 PORT_TLAST_5
PORT_IDLE_6 101 PORT_IDLE_6
PORT_RUNNING_6 102 PORT_RUNNING_6
PORT_STALLED_6 103 PORT_STALLED_6
PORT_TLAST_6 104 PORT_TLAST_6
PORT_IDLE_7 105 PORT_IDLE_7
PORT_RUNNING_7 106 PORT_RUNNING_7
PORT_STALLED_7 107 PORT_STALLED_7
PORT_TLAST_7 108 PORT_TLAST_7
GROUP_BROADCAST_A 109 GROUP_BROADCAST_A
BROADCAST_A_0 110 BROADCAST_A_0
BROADCAST_A_1 111 BROADCAST_A_1
BROADCAST_A_2 112 BROADCAST_A_2
BROADCAST_A_3 113 BROADCAST_A_3
BROADCAST_A_4 114 BROADCAST_A_4
BROADCAST_A_5 115 BROADCAST_A_5
BROADCAST_A_6 116 BROADCAST_A_6
BROADCAST_A_7 117 BROADCAST_A_7
BROADCAST_A_8 118 BROADCAST_A_8
BROADCAST_A_9 119 BROADCAST_A_9
BROADCAST_A_10 120 BROADCAST_A_10
BROADCAST_A_11 121 BROADCAST_A_11
BROADCAST_A_12 122 BROADCAST_A_12
BROADCAST_A_13 123 BROADCAST_A_13
BROADCAST_A_14 124 BROADCAST_A_14
BROADCAST_A_15 125 BROADCAST_A_15
USER_EVENT_0 126 USER_EVENT_0
USER_EVENT_1 127 USER_EVENT_1

ShuffleMode

Shuffle mode for AIEVec shuffle operations

Cases:

Symbol Value String
T8_64X2_LO 0 t8_64x2_lo
T8_64X2_HI 1 t8_64x2_hi
T16_32X2_LO 2 t16_32x2_lo
T16_32X2_HI 3 t16_32x2_hi
T32_16X2_LO 4 t32_16x2_lo
T32_16X2_HI 5 t32_16x2_hi
T64_8X2_LO 6 t64_8x2_lo
T64_8X2_HI 7 t64_8x2_hi
T128_4X2_LO 8 t128_4x2_lo
T128_4X2_HI 9 t128_4x2_hi
T256_2X2_LO 10 t256_2x2_lo
T256_2X2_HI 11 t256_2x2_hi
T128_2X4_LO 12 t128_2x4_lo
T128_2X4_HI 13 t128_2x4_hi
T64_2X8_LO 14 t64_2x8_lo
T64_2X8_HI 15 t64_2x8_hi
T32_2X16_LO 16 t32_2x16_lo
T32_2X16_HI 17 t32_2x16_hi
T16_2X32_LO 18 t16_2x32_lo
T16_2X32_HI 19 t16_2x32_hi
T8_2X64_LO 20 t8_2x64_lo
T8_2X64_HI 21 t8_2x64_hi
T512_1X2_LO 22 t512_1x2_lo
T512_1X2_HI 23 t512_1x2_hi
T16_16X4_LO 24 t16_16x4_lo
T16_16X4_HI 25 t16_16x4_hi
T16_4X16_LO 26 t16_4x16_lo
T16_4X16_HI 27 t16_4x16_hi
T16_8X4 28 t16_8x4
T16_4X8 29 t16_4x8
T32_8X4_LO 30 t32_8x4_lo
T32_8X4_HI 31 t32_8x4_hi
T32_4X8_LO 32 t32_4x8_lo
T32_4X8_HI 33 t32_4x8_hi
T32_4X4 34 t32_4x4
T8_8X8 35 t8_8x8
T8_16X4 36 t8_16x4
T8_4X16 37 t8_4x16
T16_1X2_flip 38 t16_1x2_flip
T16_4X4 39 t16_4x4
T16_4X2 40 t16_4x2
T16_2X4 41 t16_2x4
T16_8X2 42 t16_8x2
T16_2X8 43 t16_2x8
T16_16X2 44 t16_16x2
T16_2X16 45 t16_2x16
T8_8X4 46 t8_8x4
T8_4X8 47 t8_4x8
T32_8X2 48 t32_8x2
T32_2X8 49 t32_2x8
T64_4X2 50 t64_4x2
T64_2X4 51 t64_2x4
T16_8X8_LO 52 t16_8x8_lo
T16_8X8_HI 53 t16_8x8_hi
T32_1X16_flip 54 t32_1x16_flip
T8_1X4_flip 55 t8_1x4_flip

TraceMode

Trace capture mode

Cases:

Symbol Value String
EventTime 0 Event-Time
EventPC 1 Event-PC
Execution 2 Execution

TracePacketType

Packet type identifier for parsing

Cases:

Symbol Value String
Core 0 core
Mem 1 mem
ShimTile 2 shimtile
MemTile 3 memtile

TraceShimRouting

Shim tile routing strategy for trace collection

Cases:

Symbol Value String
Single 0 single

WireBundle

Bundle of wires

Cases:

Symbol Value String
Core 0 Core
DMA 1 DMA
FIFO 2 FIFO
South 3 South
West 4 West
North 5 North
East 6 East
PLIO 7 PLIO
NOC 8 NOC
Trace 9 Trace
TileControl 10 TileControl
Controller32 11 Controller32