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Used in / Cited in

IRON and the MLIR-AIE toolchain are used across a growing body of work on AI Engine and Ryzen AI NPU programming — from research papers that build on or benchmark against them, to higher-level compilers and DSLs that target IRON as a backend, to runtimes and products that ship it as their kernel layer. This page collects a representative selection of that work, alongside the project's relationship to the wider LLVM/MLIR ecosystem. It is curated rather than exhaustive, and favors entries that others can verify and follow.

If you have built on IRON or MLIR-AIE and would like your work considered for this page, open a pull request. Submissions are reviewed for relevance and are not guaranteed to be listed.

How to cite

Work that uses IRON should cite:

E. Hunhoff, J. Melber, K. Denolf, A. Bisca, S. Bayliss, S. Neuendorffer, J. Fifield, J. Lo, P. Vasireddy, P. James-Roxby, and E. Keller. "Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface." 33rd IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2025. DOI: 10.1109/FCCM62733.2025.00043

Repositories

  • amd/IRON — IRON operators, AIE kernels, and example applications, built on the MLIR-AIE Python bindings.
  • Xilinx/mlir-aie — the MLIR-based toolchain, dialects, lowering passes, and the IRON Python API bindings for AI Engine devices.
  • Xilinx/llvm-aie (Peano) — the LLVM fork adding the AI Engine as a target architecture.

Research using IRON / MLIR-AIE

Frameworks and DSLs that target IRON

  • MLIR-AIR — a spatial-compute compiler stack whose backend maps AIR constructs onto MLIR-AIE (per-tile code, DMA descriptors, hardware locks), installing MLIR-AIE as a pinned dependency. Described in Erwei Wang et al., "From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR" (arXiv:2510.14871, 2025), with matrix-multiplication and LLaMA-2 multi-head-attention case studies.
  • Triton-XDNA — an experimental Triton compiler backend for AMD Ryzen AI NPUs that lowers standard @triton.jit kernels through the MLIR Transform dialect (tiling, bufferization, vectorization) and MLIR-AIR — which in turn lowers to MLIR-AIE — to produce XRT binaries, with no prebuilt kernel libraries.
  • Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, and Peipei Zhou. "ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines." FPGA '25. An independent MLIR compilation flow for AIE devices, with and without FPGA fabric.
  • Shihan Fang, Hongzheng Chen, Niansong Zhang, Jiajie Li, Han Meng, Adrian Liu, and Zhiru Zhang. "Dato: A Task-Based Programming Model for Dataflow Accelerators." arXiv:2509.06794, 2025. A Python-embedded task-based model for FPGA and NPU dataflow accelerators; emits MLIR-AIE as its NPU backend and benchmarks against IRON, demonstrating GEMM and fused attention on XDNA.
  • Stream (package stream-dse) — a design-space-exploration and constraint-optimization framework for heterogeneous dataflow accelerators. Treats AIE as a native dataflow core type and provides AIE MLIR code generation for the Ryzen AI NPU (GEMM and SwiGLU on AMD Strix), feeding the MLIR-AIE / IRON toolchain. Described in A. Symons, L. Mei, S. Colleman, P. Houshmand, S. Karl, and M. Verhelst, "Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators," IEEE Transactions on Computers, 2025.

Runtimes and products built on IRON

  • FastFlowLM (FLM) — an NPU-first LLM and vision runtime for Ryzen AI XDNA2 with an Ollama-style interface. Its low-level compute kernels are optimized with IRON and MLIR-AIE. The orchestration and CLI are open source (MIT); the NPU-accelerated kernels are distributed as proprietary binaries.
  • Lemonade — an open-source, OpenAI-compatible local LLM server. Provides Ryzen AI NPU acceleration through its FastFlowLM (flm) backend, and therefore relies on the IRON / MLIR-AIE kernel path for NPU execution. It is multi-backend, also orchestrating llama.cpp, OnnxRuntime GenAI, and whisper.cpp, and provides a separate Windows Ryzen AI NPU path distinct from FLM.

Relationship to the LLVM / MLIR ecosystem

MLIR-AIE is built on LLVM/MLIR infrastructure and tracks it closely; releases pin the toolchain to specific LLVM commits. The host LLVM/MLIR distribution is sourced from AMD's ROCm/llvm-project fork, a downstream fork that tracks upstream LLVM. AI Engine code generation is provided separately through Peano (llvm-aie), an LLVM fork that adds the AI Engine as a target architecture and enables clang-based frontends. This is a maintained fork that tracks upstream rather than a merge of the AIE dialects into the LLVM monorepo.

Coverage

Presentations

Tutorials and workshop presentations on IRON and MLIR-AIE, delivered at academic conferences. Each links to the slide deck (PDF) and, where available, a description of the session.

Venue Year Title Links
ASPLOS 2026 IRON AI Engine API for Ryzen AI NPU PDF · Details
ISCA 2025 Leveraging the IRON AI Engine API to Program the Ryzen AI NPU PDF · Details
IPDPS 2025 Leveraging the IRON AI Engine API to Program the Ryzen AI NPU PDF · Details
MICRO 2024 Leveraging the IRON AI Engine API to Program the Ryzen AI NPU PDF · Details
ASPLOS 2024 Spatial Computing with AIR for Ryzen™ AI PDF · Details
FCCM 2023 Leveraging MLIR to Design for AI Engines PDF
ISFPGA 2023 Leveraging MLIR to Design for AI Engines PDF

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