QDMA Global Port Descriptions¶
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AXI4 Memory Mapped Master Bridge Read Address Interface Port Descriptions¶
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AXI4 Memory Mapped Master Bridge Read Interface Port Descriptions¶
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AXI4 Memory Mapped Master Bridge Write Address Interface Port Descriptions¶
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AXI4 Memory Mapped Master Bridge Write Interface Port Descriptions¶
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AXI4 Memory Mapped Master Bridge Write Response Interface Port Descriptions¶
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AXI4 Bridge Slave Write Address Interface Port Descriptions¶
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AXI4 Bridge Slave Write Interface Port Descriptions¶
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AXI4 Bridge Slave Write Response Interface Port Descriptions¶
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AXI4 Bridge Slave Read Address Interface Port Descriptions¶
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AXI4 Bridge Slave Read Interface Port Descriptions¶
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Config AXI4-Lite Memory Mapped Write Master Interface Port Descriptions¶
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Config AXI4-Lite Memory Mapped Read Master Interface Port Descriptions¶
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Config AXI4-Lite Memory Mapped Write Slave Interface Signals¶
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Config AXI4-Lite Memory Mapped Read Slave Interface Signals¶
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AXI4 Memory Mapped DMA Read Address Interface Signals¶
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AXI4 Memory Mapped DMA Read Interface Signals¶
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AXI4 Memory Mapped DMA Write Address Interface Signals¶
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AXI4 Memory Mapped DMA Write Interface Signals¶
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AXI4 Memory Mapped DMA Write Response Interface Signals¶
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AXI4-Stream H2C Port Descriptions¶
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AXI4-Stream C2H Port Descriptions¶
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AXI4-Stream C2H Completion Port Descriptions¶
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AXI-ST C2H Status Port Descriptions¶
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AXI-ST C2H Write Cmp Port Descriptions¶
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VDM Port Descriptions¶
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Configuration Extend Interface Port Descriptions¶
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FLR Port Descriptions¶
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QDMA H2C-Streaming Bypass Input Port Descriptions¶
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QDMA H2C-MM Descriptor Bypass Input Port Descriptions¶
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QDMA C2H-Streaming Cache Bypass Input Port Descriptions¶
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QDMA C2H-MM Descriptor Bypass Input Port Descriptions¶
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QDMA H2C Descriptor Bypass Output Port Descriptions¶
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QDMA C2H Descriptor Bypass Output Port Descriptions¶
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QDMA Descriptor Credit Input Port Descriptions¶
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QDMA TM Credit Output Port Descriptions¶
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User Interrupts Port Descriptions¶
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Queue Status Ports¶
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Queue status data¶
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AXI4 Memory Mapped C2H Flow¶
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AXI4 Memory Mapped H2C Flow¶
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AXI4-Stream C2H Flow¶
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AXI4-Stream H2C Flow¶
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Context Programming¶
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Descriptor Fetch Flow¶
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Software Descriptor Context Structure Definition¶
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Hardware Descriptor Structure Definition¶
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Credit Descriptor Context Structure Definition¶
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C2H Prefetch Context Structure¶
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H2C Internal Mode Flow¶
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H2C Bypass Mode Flow¶
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Handling Exception Events¶
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H2C and C2H Queue¶
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Completion Queue Flow¶
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C2H Simple Bypass Mode Flow¶
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C2H Cache Bypass Mode Flow¶
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AXI Memory Mapped Writeback Status Structure for H2C and C2H¶
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AXI4-Stream Completion Status Structure¶
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AXI4-Stream H2C Writeback Status Descriptor Structure¶
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