QDMA Global Port Descriptions

../../../../_images/001_qdma_global_port_descriptions.png

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AXI4 Memory Mapped Master Bridge Read Address Interface Port Descriptions

../../../../_images/002_axi4_memory_mapped_master_bridge_read_address_interface_port_descriptions.png

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AXI4 Memory Mapped Master Bridge Read Interface Port Descriptions

../../../../_images/003_axi4_memory_mapped_master_bridge_read_interface_port_descriptions.png

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AXI4 Memory Mapped Master Bridge Write Address Interface Port Descriptions

../../../../_images/004_axi4_memory_mapped_master_bridge_write_address_interface_port_descriptions.png

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AXI4 Memory Mapped Master Bridge Write Interface Port Descriptions

../../../../_images/005_axi4_memory_mapped_master_bridge_write_interface_port_descriptions.png

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AXI4 Memory Mapped Master Bridge Write Response Interface Port Descriptions

../../../../_images/006_axi4_memory_mapped_master_bridge_write_response_interface_port_descriptions.png

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AXI4 Bridge Slave Write Address Interface Port Descriptions

../../../../_images/007_axi4_bridge_slave_write_address_interface_port_descriptions.png

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AXI4 Bridge Slave Write Interface Port Descriptions

../../../../_images/008_axi4_bridge_slave_write_interface_port_descriptions.png

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AXI4 Bridge Slave Write Response Interface Port Descriptions

../../../../_images/009_axi4_bridge_slave_write_response_interface_port_descriptions.png

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AXI4 Bridge Slave Read Address Interface Port Descriptions

../../../../_images/010_axi4_bridge_slave_read_address_interface_port_descriptions.png

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AXI4 Bridge Slave Read Interface Port Descriptions

../../../../_images/011_axi4_bridge_slave_read_interface_port_descriptions.png

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Config AXI4-Lite Memory Mapped Write Master Interface Port Descriptions

../../../../_images/012_config_axi4-lite_memory_mapped_write_master_interface_port_descriptions.png

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Config AXI4-Lite Memory Mapped Read Master Interface Port Descriptions

../../../../_images/013_config_axi4-lite_memory_mapped_read_master_interface_port_descriptions.png

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Config AXI4-Lite Memory Mapped Write Slave Interface Signals

../../../../_images/014_config_axi4-lite_memory_mapped_write_slave_interface_signals.png

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Config AXI4-Lite Memory Mapped Read Slave Interface Signals

../../../../_images/015_config_axi4-lite_memory_mapped_read_slave_interface_signals.png

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AXI4 Memory Mapped DMA Read Address Interface Signals

../../../../_images/016_axi4_memory_mapped_dma_read_address_interface_signals.png

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AXI4 Memory Mapped DMA Read Interface Signals

../../../../_images/017_axi4_memory_mapped_dma_read_interface_signals.png

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AXI4 Memory Mapped DMA Write Address Interface Signals

../../../../_images/018_axi4_memory_mapped_dma_write_address_interface_signals.png

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AXI4 Memory Mapped DMA Write Interface Signals

../../../../_images/019_axi4_memory_mapped_dma_write_interface_signals.png

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AXI4 Memory Mapped DMA Write Response Interface Signals

../../../../_images/020_axi4_memory_mapped_dma_write_response_interface_signals.png

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AXI4-Stream H2C Port Descriptions

../../../../_images/021_axi4-stream_h2c_port_descriptions.png

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AXI4-Stream C2H Port Descriptions

../../../../_images/022_axi4-stream_c2h_port_descriptions.png

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AXI4-Stream C2H Completion Port Descriptions

../../../../_images/023_axi4-stream_c2h_completion_port_descriptions.png

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AXI-ST C2H Status Port Descriptions

../../../../_images/024_axi-st_c2h_status_port_descriptions.png

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AXI-ST C2H Write Cmp Port Descriptions

../../../../_images/025_axi-st_c2h_write_cmp_port_descriptions.png

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VDM Port Descriptions

../../../../_images/026_vdm_port_descriptions.png

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Configuration Extend Interface Port Descriptions

../../../../_images/027_configuration_extend_interface_port_descriptions.png

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FLR Port Descriptions

../../../../_images/028_flr_port_descriptions.png

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QDMA H2C-Streaming Bypass Input Port Descriptions

../../../../_images/029_qdma_h2c-streaming_bypass_input_port_descriptions.png

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QDMA H2C-MM Descriptor Bypass Input Port Descriptions

../../../../_images/030_qdma_h2c-mm_descriptor_bypass_input_port_descriptions.png

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QDMA C2H-Streaming Cache Bypass Input Port Descriptions

../../../../_images/031_qdma_c2h-streaming_cache_bypass_input_port_descriptions.png

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QDMA C2H-MM Descriptor Bypass Input Port Descriptions

../../../../_images/032_qdma_c2h-mm_descriptor_bypass_input_port_descriptions.png

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QDMA H2C Descriptor Bypass Output Port Descriptions

../../../../_images/033_qdma_h2c_descriptor_bypass_output_port_descriptions.png

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QDMA C2H Descriptor Bypass Output Port Descriptions

../../../../_images/034_qdma_c2h_descriptor_bypass_output_port_descriptions.png

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QDMA Descriptor Credit Input Port Descriptions

../../../../_images/035_qdma_descriptor_credit_input_port_descriptions.png

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QDMA TM Credit Output Port Descriptions

../../../../_images/036_qdma_tm_credit_output_port_descriptions.png

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User Interrupts Port Descriptions

../../../../_images/037_user_interrupts_port_descriptions.png

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Queue Status Ports

../../../../_images/038_queue_status_ports.png

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Queue status data

../../../../_images/039_queue_status_data.png

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AXI4 Memory Mapped C2H Flow

../../../../_images/040_axi4_memory_mapped_c2h_flow.png

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AXI4 Memory Mapped H2C Flow

../../../../_images/041_axi4_memory_mapped_h2c_flow.png

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AXI4-Stream C2H Flow

../../../../_images/042_axi4-stream_c2h_flow.png

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AXI4-Stream H2C Flow

../../../../_images/043_axi4-stream_h2c_flow.png

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Context Programming

../../../../_images/044_context_programming.png

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Descriptor Fetch Flow

../../../../_images/045_descriptor_fetch_flow.png

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Software Descriptor Context Structure Definition

../../../../_images/046_software_descriptor_context_structure_definition.png

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Hardware Descriptor Structure Definition

../../../../_images/047_hardware_descriptor_structure_definition.png

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Credit Descriptor Context Structure Definition

../../../../_images/048_credit_descriptor_context_structure_definition.png

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C2H Prefetch Context Structure

../../../../_images/049_c2h_prefetch_context_structure.png

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H2C Internal Mode Flow

../../../../_images/050_h2c_internal_mode_flow.png

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H2C Bypass Mode Flow

../../../../_images/051_h2c_bypass_mode_flow.png

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Handling Exception Events

../../../../_images/052_handling_exception_events.png

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H2C and C2H Queue

../../../../_images/053_h2c_and_c2h_queue.png

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Completion Queue Flow

../../../../_images/054_completion_queue_flow.png

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C2H Simple Bypass Mode Flow

../../../../_images/055_c2h_simple_bypass_mode_flow.png

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C2H Cache Bypass Mode Flow

../../../../_images/056_c2h_cache_bypass_mode_flow.png

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AXI Memory Mapped Writeback Status Structure for H2C and C2H

../../../../_images/057_axi_memory_mapped_writeback_status_structure_for_h2c_and_c2h.png

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AXI4-Stream Completion Status Structure

../../../../_images/058_axi4-stream_h2c_writeback_status_descriptor_structure.png

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AXI4-Stream H2C Writeback Status Descriptor Structure

../../../../_images/059_axi4-stream_completion_status_structure.png

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