QDMA Global Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped Master Bridge Read Address Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Master-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Master-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped Master Bridge Read Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Master-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Master-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped Master Bridge Write Address Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Master-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Master-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped Master Bridge Write Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Master-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Master-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped Master Bridge Write Response Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Master-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Master-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Bridge Slave Write Address Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Slave-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Slave-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Bridge Slave Write Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Slave-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Slave-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Bridge Slave Write Response Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Slave-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Slave-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Bridge Slave Read Address Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Slave-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Slave-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Bridge Slave Read Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Bridge-Slave-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Bridge-Slave-Ports

See the latest version of PG302, PG344, PG347 for updates

Config AXI4-Lite Memory Mapped Write Master Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Lite-Master-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Lite-Master-Ports

See the latest version of PG302, PG344, PG347 for updates

Config AXI4-Lite Memory Mapped Read Master Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Lite-Master-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Lite-Master-Ports

See the latest version of PG302, PG344, PG347 for updates

Config AXI4-Lite Memory Mapped Write Slave Interface Signals¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Lite-Slave-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Lite-Slave-Ports

See the latest version of PG302, PG344, PG347 for updates

Config AXI4-Lite Memory Mapped Read Slave Interface Signals¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Lite-Slave-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Lite-Slave-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped DMA Read Address Interface Signals¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Memory-Mapped-DMA-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Memory-Mapped-DMA-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Memory-Mapped-Interface?tocId=nHCC~3lUKCHYh9MZrllDrA

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped DMA Read Interface Signals¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Memory-Mapped-DMA-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Memory-Mapped-DMA-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Memory-Mapped-Interface?tocId=nHCC~3lUKCHYh9MZrllDrA

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped DMA Write Address Interface Signals¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Memory-Mapped-DMA-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Memory-Mapped-DMA-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Memory-Mapped-Interface?tocId=nHCC~3lUKCHYh9MZrllDrA

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped DMA Write Interface Signals¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Memory-Mapped-DMA-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Memory-Mapped-DMA-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Memory-Mapped-Interface?tocId=nHCC~3lUKCHYh9MZrllDrA

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped DMA Write Response Interface Signals¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Memory-Mapped-DMA-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Memory-Mapped-DMA-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Memory-Mapped-Interface?tocId=nHCC~3lUKCHYh9MZrllDrA

See the latest version of PG302, PG344, PG347 for updates

AXI4-Stream H2C Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Stream-H2C-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Stream-H2C-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Stream-H2C-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4-Stream C2H Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Stream-C2H-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Stream-C2H-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Stream-C2H-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI4-Stream C2H Completion Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Stream-C2H-Completion-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Stream-C2H-Completion-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Stream-C2H-Completion-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI-ST C2H Status Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Stream-Status-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Stream-Status-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Stream-Status-Ports

See the latest version of PG302, PG344, PG347 for updates

AXI-ST C2H Write Cmp Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Stream-C2H-Write-Completion-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Stream-C2H-Write-Completion-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Stream-C2H-Write-Completion-Ports

See the latest version of PG302, PG344, PG347 for updates

VDM Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/VDM-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/VDM-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/VDM-Ports

See the latest version of PG302, PG344, PG347 for updates

Configuration Extend Interface Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Configuration-Extend-Interface-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Configuration-Extend-Interface-Ports

See the latest version of PG302, PG344, PG347 for updates

FLR Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/FLR-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/FLR-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/FLR-Ports

See the latest version of PG302, PG344, PG347 for updates

QDMA H2C-Streaming Bypass Input Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Descriptor-Bypass-Input-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Descriptor-Bypass-Input-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Descriptor-Bypass-Input-Ports

See the latest version of PG302, PG344, PG347 for updates

QDMA H2C-MM Descriptor Bypass Input Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Descriptor-Bypass-Input-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Descriptor-Bypass-Input-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Descriptor-Bypass-Input-Ports

See the latest version of PG302, PG344, PG347 for updates

QDMA C2H-Streaming Cache Bypass Input Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Descriptor-Bypass-Input-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Descriptor-Bypass-Input-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Descriptor-Bypass-Input-Ports

See the latest version of PG302, PG344, PG347 for updates

QDMA C2H-MM Descriptor Bypass Input Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Descriptor-Bypass-Input-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Descriptor-Bypass-Input-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Descriptor-Bypass-Input-Ports

See the latest version of PG302, PG344, PG347 for updates

QDMA H2C Descriptor Bypass Output Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Descriptor-Bypass-Output-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Descriptor-Bypass-Output-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Descriptor-Bypass-Output-Ports

See the latest version of PG302, PG344, PG347 for updates

QDMA C2H Descriptor Bypass Output Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Descriptor-Bypass-Output-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Descriptor-Bypass-Output-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Descriptor-Bypass-Output-Ports

See the latest version of PG302, PG344, PG347 for updates

QDMA Descriptor Credit Input Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Descriptor-Credit-Input-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Descriptor-Credit-Input-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Descriptor-Credit-Input-Ports

See the latest version of PG302, PG344, PG347 for updates

QDMA TM Credit Output Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/QDMA-Traffic-Manager-Credit-Output-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Traffic-Manager-Credit-Output-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/QDMA-Traffic-Manager-Credit-Output-Ports

See the latest version of PG302, PG344, PG347 for updates

User Interrupts Port Descriptions¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/User-Interrupts

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/User-Interrupts?tocId=JDdZMAsujF8XvOqyC4QD7w

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/User-Interrupts?tocId=Bitp2ey_91KNCZTqp1MyFA

See the latest version of PG302, PG344, PG347 for updates

Queue Status Ports¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Queue-Status-Ports

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Queue-Status-Ports

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Queue-Status-Ports

See the latest version of PG302, PG344, PG347 for updates

Queue status data¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Queue-Status-Data-qsts_out_data

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Queue-Status-Data-qsts_out_data

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Queue-Status-Data

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped C2H Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Memory-Mapped-C2H-Flow

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Memory-Mapped-C2H-Flow

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Memory-Mapped-C2H-Flow

See the latest version of PG302, PG344, PG347 for updates

AXI4 Memory Mapped H2C Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Memory-Mapped-C2H-Flow

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Memory-Mapped-C2H-Flow

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Memory-Mapped-C2H-Flow

See the latest version of PG302, PG344, PG347 for updates

AXI4-Stream C2H Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Stream-C2H-Flow

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Stream-C2H-Flow

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Stream-C2H-Flow

See the latest version of PG302, PG344, PG347 for updates

AXI4-Stream H2C Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI4-Stream-H2C-Flow

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Stream-H2C-Flow

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI4-Stream-H2C-Flow

See the latest version of PG302, PG344, PG347 for updates

Context Programming¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Context-Programming

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Context-Programming

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Context-Programming

See the latest version of PG302, PG344, PG347 for updates

Descriptor Fetch Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Descriptor-Fetch

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Descriptor-Fetch

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Descriptor-Fetch

See the latest version of PG302, PG344, PG347 for updates

Software Descriptor Context Structure Definition¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Software-Descriptor-Context-Structure-0x0-C2H-and-0x1-H2C

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Software-Descriptor-Context-Structure-0x0-C2H-and-0x1-H2C

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Software-Descriptor-Context-Structure-0x0-C2H-and-0x1-H2C

See the latest version of PG302, PG344, PG347 for updates

Hardware Descriptor Structure Definition¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Hardware-Descriptor-Context-Structure-0x2-C2H-and-0x3-H2C

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Hardware-Descriptor-Context-Structure-0x2-C2H-and-0x3-H2C

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Hardware-Descriptor-Context-Structure-0x2-C2H-and-0x3-H2C

See the latest version of PG302, PG344, PG347 for updates

Credit Descriptor Context Structure Definition¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Credit-Descriptor-Context-Structure

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Credit-Descriptor-Context-Structure

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Credit-Descriptor-Context-Structure

See the latest version of PG302, PG344, PG347 for updates

C2H Prefetch Context Structure¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/C2H-Prefetch-Engine

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/C2H-Prefetch-Engine

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/C2H-Prefetch-Engine

See the latest version of PG302, PG344, PG347 for updates

H2C Internal Mode Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Internal-and-Bypass-Modes

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Internal-and-Bypass-Modes

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Internal-and-Bypass-Modes

See the latest version of PG302, PG344, PG347 for updates

H2C Bypass Mode Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Internal-and-Bypass-Modes

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Internal-and-Bypass-Modes

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Internal-and-Bypass-Modes

See the latest version of PG302, PG344, PG347 for updates

Handling Exception Events¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Handling-Exception-Events

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Handling-Exception-Events

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Handling-Exception-Events

See the latest version of PG302, PG344, PG347 for updates

H2C and C2H Queue¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/H2C-and-C2H-Queues

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/H2C-and-C2H-Queues

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/H2C-and-C2H-Queues

See the latest version of PG302, PG344, PG347 for updates

Completion Queue Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Completion-Queue

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Completion-Queue

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Completion-Queue

See the latest version of PG302, PG344, PG347 for updates

C2H Simple Bypass Mode Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/C2H-Stream-Modes

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/C2H-Stream-Modes

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/C2H-Stream-Modes

See the latest version of PG302, PG344, PG347 for updates

C2H Cache Bypass Mode Flow¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/C2H-Stream-Modes

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/C2H-Stream-Modes

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/C2H-Stream-Modes

See the latest version of PG302, PG344, PG347 for updates

AXI Memory Mapped Writeback Status Structure for H2C and C2H¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/AXI-Memory-Mapped-Writeback-Status-Structure-for-H2C-and-C2H

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-Memory-Mapped-Writeback-Status-Structure-for-H2C-and-C2H

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/AXI-Memory-Mapped-Writeback-Status-Structure-for-H2C-and-C2H

See the latest version of PG302, PG344, PG347 for updates

AXI4-Stream H2C Writeback Status Descriptor Structure¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/H2C-Stream-Status-Descriptor-Writeback

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/H2C-Stream-Status-Descriptor-Writeback

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/H2C-Stream-Status-Descriptor-Writeback

See the latest version of PG302, PG344, PG347 for updates

AXI4-Stream Completion Status Structure¶

Note

The table above is sourced from PG302. Refer to the links below for the latest relevant IP table.

PG302: https://docs.amd.com/r/en-US/pg302-qdma/Completion-Status-Structure

PG344: https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Completion-Status-Structure

PG347: https://docs.amd.com/r/en-US/pg347-cpm-dma-bridge/Completion-Status-Structure

See the latest version of PG302, PG344, PG347 for updates