Training

This page presents a list of resources to get you started with the different Xilinx tools to carry out your research successfully.

Xilinx also provides commercial training courses on a wide range of topics. Find the latest courses on the Xilinx training webpage

Hands-on examples

This list cover examples and tutorials hosted on Xilinx GitHub

  1. Vitis In Depth Tutorial
  2. Vitis AWS F1 Developer Labs
  3. Vitis Tutorials
  4. Vitis Accel Examples
  5. Vitis HLS Tutorial
  6. Vitis Accelerated Libraries
  7. Vitis AI Tutorials

Third Party

Productive Parallel Programming for FPGA with HLS

Johannes de Fine Licht and Torsten Hoefler from SPCL at ETH Zurich offer this HPC-oriented tutorial that shows how high-level synthesis (HLS) can be harnessed to productively achieve scalable pipeline parallelism on FPGAs. Using familiar codes known from software, it is shown how FPGA resources are targeted from high-level C++ code, guiding the mapping from imperative code to hardware to enable massively parallel designs.

You can find out more information in this link and watch the presentation here.

Books

This following books may also be relevant in the context of XACC and compute acceleration in general

  1. Parallel Programming for FPGAs Book by Ryan Kastner, Janarbek Matai, and Stephen Neuendorffer. Covers HLS and parallel hardware concepts.
    Source code on GitHub Projects and Labs
  2. The ZYNQ Book, the earlier chapters of the book cover basic HLS concepts, such as pipeline and dataflow which may be relevant for researchers developing accelerators.

Copyright© 2021 Xilinx