AVED V80 - Source File Overview¶

Hardware Directory Tree¶

Hardware Source

aved
├── fw/AMC
└── hw
    └── amd_v80_gen5x8_24.1
        ├── build_all.sh
        ├── fpt
        │   ├── fpt_pdi_gen.py
        │   └── pdi_combine.bif
        └── src
            ├── bd
            │   └── create_bd_design.tcl
            ├── build_design.tcl
            ├── constraints
            │   ├── impl.pins.xdc
            │   ├── impl.xdc
            │   ├── opt.post.tcl
            │   ├── place.pre.tcl
            │   └── write_device_image.pre.tcl
            ├── create_design.tcl
            └── iprepo
                ├── cmd_queue_v2_0
                ├── hw_discovery_v1_0
                ├── shell_utils_uuid_rom_v2_0
                └── smbus_v1_1*

*       : This location does not exist. The user must populate this location.

aved¶

This is the top level directory containing the source files for creating the AVED design and the build script. When executed, the build_all.sh script builds the hardware design, firmware, FPT binary, and final PDI.

hw¶

The hw directory contains the files necessary to build the hardware design.

amd_v80_gen5x8_24.1¶

This is the top level directory for the AMD Gen5x8 example design. The directory name is the same as the VBNV, and is used throughout the design.

build_all.sh¶

This is the main build shell. Executing this shell will launch VivadoTM, build the AVED hardware design, compile the AMC firmware, and generate the PDI files. For the AMC FW to be compiled, this script expects the fw/AMC folder at the same level as the hw directory. This is indicated by the asterisk in the Hardware Directory Tree above.

fpt¶

pdi_combine.bif - This file is used in the build_all.sh to combine the FW amc.elf with the HW PDI.
- output: build/amd_v80_gen5x8_24.1_nofpt.pdi
fpt_pdi_gen.py - This file is used in the build_all.sh to create the final FPT PDI
- output: amd_v80_gen5x8_24.1.pdi

src¶

bd - This is the Block Design generation directory which contains the TCL file necessary to build the AMD Vivado™ AVED design.
- create_bd_design.tcl - This TCL file is used by Vivado to create the base AVED design. Since the GTs are not used in this design, the interface ports have been commented out. The user may uncomment them as required for their design.
build_design.tcl - This script uses Vivado to create the XSA and run synthesis and implementation.
contraints - This directory contains the constraints required for Vivado implementation to generate a PDI.
- impl.pins.xdc - This file contains the top level I/O pin names, locations, and IO standards for the DDR, DIMM, GTYPs, GTMs, and clocks.
  - Note: Since the GTs are not used in the base V80 design, these pins have been commented out.
- impl.xdc - This file defines strictly enforced pblocks for each SLR. A strictly enforced pblock does not allow cells to be moved outside pblock boundaries. The base logic is assigned to SLR0, while user logic can be assigned to SLR0, SLR1, and SLR2 as needed. The NMU for the PCIe Management SmartConnect (pcie_slr0_mgmt_sc) is LOC’d to keep the base logic resources close to the CIPS in SLR0.
- opt.post.tcl - This file turns on bitstream compression and enables NPI DMA mode to accelerate device download. It also disables BUFG insertion in placement to prevent clock changes.
- place.pre.tcl - The PCIe Management PDI Reset logic currently is not used in AVED, but it was added for future growth. Currently, the settings in this file connect the reset to a PMC interrupt. The response to this interrupt has not been defined.
- write_device_image.pre.tcl - This file generates the UUID for the AVED design which is stored in the UUID of the base logic.
create_design.tcl - This file is used by Vivado to create the project, create the BD, add the constraint files, and set the processing order for creating the AVED design.
iprepo - This directory contains all the additional IP necessary to build the AVED design that is not included in the Vivado released SW.
- cmd_queue_v2_0
- hw_discovery_v1_0
- shell_utils_uuid_rom_v2_0
- smbus_v1_1 - This IP must be added from the lounge by the user due to licensing requirements (https://www.xilinx.com/member/v80.html). Vivado will not build the AVED design if this IP is not present. This is indicated by the asterisk in the Hardware Directory Tree above.

Page Revision: v. 55