ASPLOS 2026 Tutorial: Leveraging the IRON AI Engine API to program the Ryzen™ AI NPU¶
Introduction¶
The NPU of AMD Ryzen™ AI devices includes an AI Engine array comprised of a set of VLIW vector processors, Direct Memory Access channels (DMAs) and adaptable interconnect. This tutorial is targeted at performance engineers who are looking to develop designs targeting the NPU with open source design tools. We provide a close-to-metal Python API: Interface Representation for hands-ON (IRON) AIE-array programming. IRON is an open access toolkit enabling performance engineers to build fast and efficient, often specialized, designs through a set of Python language bindings around the mlir-aie dialect. Participants will first get insight into the AI Engine compute and data movement capabilities. Through small design examples expressed in the IRON API and executed on an Ryzen™ AI device, participants will leverage AI Engine features for optimizing performance of increasingly complex designs. The labs will be done on Ryzen™ AI-enabled mini-PCs, giving participants the ability to execute their own designs on real hardware.
This tutorial will cover the following key topics: 1. NPU and AI Engine architecture introduction 1. AIE core, array configuration, and host application code compilation 1. Data movement and communication abstraction layers 1. Tracing for performance monitoring 1. Putting it all together on larger examples: matrix multiplication, convolutions as building blocks for ML and computer vision examples
Agenda¶
Date: Monday, March 23, 2026
Start time: 8 AM
Location: Pittsburgh, PA, USA
Prerequisites:¶
- Please bring your laptop so that you can SSH into our Ryzen™ AI-enabled miniPCs for the hands-on exercises.
- Knowledge in basic computer architecture, basic programming (Python), basic algorithms is required.
- Knowledge of vision pipelines and ML is not necessary but a plus.
Contents and Timeline (tentative)¶
| Time | Topic | Presenter | Slides or Code |
|---|---|---|---|
| 08:00am | Intro to spatial compute and explicit data movement | Joe | Programming Guide |
| 08:15am | "Hello World" from Ryzen™ AI | Joe | AI Engine Basic Building Blocks |
| 08:35am | Exercise 1: Build and run your first program | All | Passthrough |
| 08:50am | Data movement on Ryzen™ AI with objectFIFOs | Erika | Data Movement |
| 09:10am | Exercise 2: Explore AIE DMA capabilities | All | DMA Transpose |
| 09:20am | Your First Program | Erika | My First Program |
| 09:50am | Exercise 3: Vector-scalar mul | All | Vector Scalar Mul |
| 10:00am | Coffee Break | ||
| 10:30am | Tracing and performance analysis | Jack | Timers and Tracing |
| 10:50am | Exercise 4: Tracing vector-scalar mul | All | Vector Scalar Mul |
| 11:00am | Vectorizing on AIE | Jack | Kernel Vectorization |
| 11:20am | Exercise 5: Tracing vectorized vector-scalar | All | Vector Scalar Mul |
| 11:30pm | Dataflow and larger designs | Erika | Example Vector Designs and Large Example Designs |
| 11:40pm | Exercise 6: More examples | All | Programming Examples |
| 11:50pm | Close Tutorial | All |
Organizers¶
Joseph Melber is a Senior Member of Technical Staff in AMD’s Research and Advanced Development group. At AMD, he is working on hardware architectures and compiler technologies for current and future AMD devices. He received a BS in electrical engineering from the University Buffalo, as well as MS and PhD degrees from the electrical and computer engineering department at Carnegie Mellon University. His research interests include runtime systems, compiler abstractions for data movement, and hardware prototypes for future adaptive heterogeneous computing architectures.
Erika Hunhoff is a Senior Member of Technical Staff in AMD’s Research and Advanced Development group. At AMD, she is working on compiler technologies for current and future AMD devices. She received a BS in Computer Science and Mathematics from George Fox University, as well as MS and PhD degrees from the computer science department at the University of Colorado, Boulder. Her research interests include programming abstractions for complex systems and compiler abstractions for heterogeneous computing architectures.
Jack Lo is a Senior Member of Technical Staff in AMD’s Research and Advanced Development group. At AMD, he is focused on developing tool frameworks and optimizing applications for current and future AMD devices, particularly in the area of adaptive computing and AI processing.