GT test cases description¶
The various GTs are tested by sending and receiving traffic at 10GbE, 25GbE, 32Gb/s or 56GbE rate. The simplest test consists of looping back each individual lane to themselves (Tx to Rx). Although all xbtest hardware IP (xbtIP) are designed to test the 4 lanes simultaneously, each lane can be configured (or disabled) individually.
There are 4 types of xbtest hardware IP (xbtIP) to test the GT, each offering different test capabilities:
GT MAC xbtIP: generates & checks Ethernet packet at 10GbE and 25GbE rate in GT MAC test case.
Allows, per lane, complex GbE traffic configuration (packet size & rate …) via the support of 10G/25G High Speed Ethernet Subsystem xbtIP core (see 10G/25G High speed ethernet subsystem product guide (PG210)).
Can be connected to itself, to another instance of itself or to a switch (to support cross lane traffic).
GTyp, GTM PRBS xbtIP: generates & checks PRBS-31 data at respectively 32Gb/s and 56GbE rate in GTYP/GTM PRBS test case.
Requires to be looped back to itself.
Note
Not all rates are supported for all modes or card. The SW reports when the wrong rate is used. Alternatively, you can check the pre-canned tests available for your card (see Pre-canned tests description for more information).
Warning
Resetting a GT creates a load transient resulting in a temporary spike or dip in the power supply voltage. The voltage at the input pin of the device must remain within the operating limits as specified in the data sheets.
It’s highly recommended to not reset multiple GT xbtIP simultaneously.
This can be achieved by e.g. giving a different duration to the configuration phase of the test_sequence of each GT test cases
(see each GT test case test_sequence description).
xbtIP included in Alveo Versal Example Design (AVED) dictates which test can be performed and how the GT should/could (or not) be interconnected. The choice of the xbtIP is done during Alveo Versal Example Design (AVED) generation. It’s mainly based on how many xbtIP can be inserted. Ideally GT MAC xbtIP should be used but its huge resource utilization could make it impossible to insert multiple times within the FPGA.
Here are some examples of how to interconnect the GT when Alveo Versal Example Design (AVED) contains more than one GT xbtIP.
GT MAC xbtIP can be:
Looped back to itself via module or cable: each individual lane is expecting to receive (Rx) what it has transmitted (Tx).
Looped back to itself via a switch: cross lane traffic. Lanes must be paired: one lane sends & receives traffic only to & from another one.
Connected to another GT MAC xbtIP present in same Alveo Versal Example Design (AVED): this interconnects individual lanes from both xbtIP. E.g. Lane[i] of one GT MAC xbtIP receives and sends traffic to Lane[i] of the other GT MAC xbtIP.
