Test cases overview

Different test cases can be run by xbtest depending on capabilities of your Alveo Versal Example Design (AVED). A failure in a test case does not stop other test cases.

Apart from the Verify test case, a test case is composed of, at minimum, a test sequence which contains the duration and some configuration parameters.

The following tables provides an overview of the supported test cases:

Test cases overview

Test case

Overview

Verify

  • Detects and reports available xbtest hardware IP (xbtIP).

  • Checks compatibility.

  • Displays design definition.

  • Checks capabilities of all xbtIP.

  • Checks basic communication between the host and the xbtIP:

    • Read/write of a scratch register.

MMIO

  • Checks data transfer between the host and the PCIe BAR registers on the device.

  • Uses counter for data integrity check.

  • Measures read and write bandwidths between the host and the PCIe BARs.

Note

The MMIO test case does not use any xbtIP.

../../../../../_images/test-case-mmio.svg

MMIO test case

DMA

  • Checks data transfer between host and memories available on the card (for example: DDR/HBM).

  • Tests each memory individually.

  • Uses counter for data integrity check.

  • Measures read and write bandwidths between host and memories available on the card.

Note

The DMA test case does not use any xbtIP.

../../../../../_images/test-case-dma.svg

DMA test case

Memory

  • Checks data transfer between xbtIP and memories available on the card (for example: DDR HBM).

  • Tests all memories separately with a different configuration for each memory type.

  • Uses PRBS31 for data integrity check and linear addressing.

  • Measure read and write bandwidths and latencies.

../../../../../_images/test-case-memory.svg

Memory test case

Power

  • Sets power consumed by the card by controlling the toggle rate of resources present in xbtIP.

Power xbtIP only exercises the logic of Alveo Versal Example Design (AVED). The maximum and minimum power depend on the following:

GT MAC

  • Checks GT transceivers at 10 Gigabit Ethernet (10 GbE) and 25 Gigabit Ethernet (25 GbE) lane rates.

  • Uses the AMD XXV Ethernet IP core (see 10G/25G High speed ethernet subsystem product guide (PG210)).

  • Includes packet generators, checkers and counters to verify that all expected packets are received error free.

  • Supports configurable GT settings which allows the GT MAC xbtIP to be connected to:

    1. A switch: optical or electrical cables.

    2. Directly Itself: loopback module or cables.

    3. Another GT MAC xbtIP (present in the same Alveo Versal Example Design (AVED)): optical or electrical cables.

    Note

    With the 2 first methods, traffic is ultimately looped back to the GT MAC xbtIP itself. With the last method, traffic flows between GT MAC xbtIP instances.

../../../../../_images/test-case-gt-mac.svg

GT MAC test case

GTYP/GTM PRBS

GT lanes are checked by generating and checking PRBS-31 data. BER is computed

  • Checks GTYp transceiver at 32Gb/s lane rates

  • Checks GTM transceiver at 56 Gigabit Ethernet (56 GbE) lane rates

../../../../../_images/test-case-multi-gt-prbs.svg

GTYp, GTM PRBS test case