AVED V80/V80P - Source File Overview¶

Hardware Directory Tree¶

Hardware Source

hw
└── amd_v80*_gen5x8_23.2_exdes_1
    ├── bd
    │   ├── create_bd_design.tcl
    │   └── customize_bd_xbtest.tcl
    ├── build_hw.tcl
    ├── conf_user.json
    ├── conf_xbtest.json
    ├── conf_xbtest_stress.json
    ├── constraints
    │   ├── impl.pins.xdc
    │   ├── impl.xbtest.xdc
    │   ├── impl.xdc
    │   ├── opt.post.tcl
    │   ├── place.pre.tcl
    │   └── write_device_image.pre.tcl
    ├── fpt
    │   └── fpt_pdi_gen.py
    ├── iprepo
    │   ├── cmd_queue_v2_0
    │   ├── hw_discovery_v1_0
    │   ├── shell_utils_uuid_rom_v2_0
    │   └── xbtest
     └── metadata
        └── generate_xbtest_metadata.tcl

hw¶

The hw directory contains the files necessary to build the hardware design.

amd_<board>_gen5x8_23.2_exdes_1¶

This is the top level directory for the AMD Gen5x8 example design, where the board is v80 or v80p. The directory name is the same as the VBNV, and is used throughout the design.

bd¶

This is the Block Design generation directory which contains the TCL files necessary to build the AMD Vivado™ AVED Example design.

create_bd_design.tcl - This TCL file is used by Vivado to create the base AVED design.
customize_bd_xbtest.tcl - This TCL file is used by Vivado to add xbtest to the above base AVED design.

build_hw.tcl¶

This file creates the AMD Vivado™ project and calls the bd TCL files above to create the block design. It then runs synthesis and implementation to generate the top_wrapper.pdi. This file is copied and renamed to <board>_initialization.pdi later in the deployment step of the design flow.

conf_user.json¶

This configuration file is used to build the base design without xbtest. This design will take the shortest amount of time to build. This design will typically take 2-4 hours to build.

conf_xbtest.json¶

This configuration file is used to build the base design with xbtest, but without the additional rAMD Versal™ device resources specifically for stressing device power consumption. This design will typically take 3-5 hours to build.

conf_xbtest_stress.json¶

This configuration file is used to build the base design with xbtest and the additional Versal device resources to stress device power consumption. With the added BRAM, URAM, and DSPs this build will typically take 11-14 hours to build. It is highly dependent on the machine and the amount of resources used.

constraints¶

This directory contains the constraints required for Vivado implementation to generate a PDI.

impl.pins.xdc - This file contains the top level I/O pin names, locations, and IO standards for the DDR, DIMM, GTYPs, GTMs, and clocks.
impl.xbtest.xdc - This file assigns xbtest logic for the DDR, DIMM, HBM, and power kernels to particular SLRs. It also assigns specific xbtest interfaces to the DDR, DIMM, and HBM NoC resources (NMUs and NSUs). This aids the Vivado tool in routing and helps optimize the overall performance of the design.
impl.xdc - This file defines strictly enforced pblocks for each SLR. A strictly enforced pblock does not allow cells to be moved outside pblock boundaries. The base logic is assigned to SLR0, while xbtest logic is added to each SLR pblock using impl.xbtest.xdc. The NMU for the PCIe Management SmartConnect (pcie_slr0_mgmt_sc) is LOC’d to keep the base logic resources close to the CIPS in SLR0.
opt.post.tcl - This file turns on bitstream compression and enables NPI DMA mode to accelerate device download. It also disables BUFG insertion in placement to prevent clock changes.
place.pre.tcl - The PCIe Management PDI Reset logic currently is not used in AVED, but it was added for future growth. Currently, the settings in this file connect the reset to a PMC interrupt. The response to this interrupt has not been defined.
write_device_image.pre.tcl - This file generates the UUID for the AVED design which is stored in the UUID of the base logic.

fpt¶

fpt_pdi_gen.py - This file creates the Flash Partition Table (FPT) PDI that is included in the deployment package.
- fpt_setup_amd_<board>_gen5x8_23.2_exdes_1_<release>.pdi

iprepo¶

This directory contains all the additional IP necessary to build the AVED design that is not included in the Vivado released SW.

cmd_queue_v2_0
hw_discovery_v1_0
shell_utils_uuid_rom_v2_0
xbtest - This directory contains the xbtest IP and metadata needed to implement the xbtest IP for creating traffic generators to monitor the bandwidth of the memory and GT interfaces in the AVED design.

Refer to AVED V80/V80P - XBTEST Design for information on the xbtest IP. For all other IP, refer to AVED V80/V80P - Base Logic.

metadata¶

generate_xbtest_metadata.tcl - This file generates the metadata needed for xbtest.

Page Revision: v. 22